fan7392 high-current, high- and low-side, gate-drive...
TRANSCRIPT
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
FAN7392 Rev. 1.0.2
July 2009
FAN7392High-Current, High- and Low-Side, Gate-Drive IC
FeaturesFloating Channel for Bootstrap Operation to +600V3A/3A Sourcing/Sinking Current Driving CapabilityCommon-Mode dv/dt Noise Canceling Circuit3.3V Logic CompatibleSeparate Logic Supply (VDD) Range from 3.3V to 20VUnder-Voltage Lockout for VCC and VBSCycle-by-Cycle Edge-Triggered Shutdown LogicMatched Propagation Delay for Both ChannelsOutputs In-phase with Input SignalsAvailable in 14-DIP and 16-SOP (Wide) Packages
ApplicationsHigh-Speed Power MOSFET and IGBT Gate Driver Server Power SupplyUninterrupted Power Supply (UPS)Telecom System Power SupplyDistributed Power SupplyMotor Drive Inverter
DescriptionThe FAN7392 is a monolithic high- and low-side gatedrive IC, that can drive high-speed MOSFETs and IGBTsthat operate up to +600V. It has a buffered output stagewith all NMOS transistors designed for high pulse currentdriving capability and minimum cross-conduction. Fair-child’s high-voltage process and common-mode noisecanceling techniques provide stable operation of thehigh-side driver under high dv/dt noise circumstances.An advanced level-shift circuit offers high-side gate driveroperation up to VS=-9.8V (typical) for VBS=15V. Logicinputs are compatible with standard CMOS or LSTTLoutput, down to 3.3V logic. The UVLO circuit preventsmalfunction when VCC and VBS are lower than the speci-fied threshold voltage. The high-current and low-outputvoltage drop feature makes this device suitable for half-and full-bridge inverters, like switching-mode power sup-ply and high-power DC-DC converter applications.
Ordering Information
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
14-PDIP 16-SOP
Part Number OperatingTemperature Range Package Eco Status Packing Method
FAN7392N
-40°C to +125°C
14-PDIP
RoHS
Tube
FAN7392M16-SOP
Tube
FAN7392MX Tape and Reel
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 2
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Typical Application Diagrams
Figure 1. Typical Application Circuit (Referenced 14-DIP)
Figure 2. Typical Application Circuit (Referenced 16-SOP)
DBOOT
Q1
RBOOT
CBOOT
15V
Q2C1
R2
R1
Up to 600V
Controller
HIN
LIN
LO
COM
VB
VS
VDD
SD
HIN
NC
13
NC
HO
VSS
NC
12
14
11
10
9
8
2
3
1
4
7
5
6
LIN VCC
SD
15V
Load
DBOOT
Q1
RBOOT
CBOOT
15V
Q2C1
R2
R1
Up to 600V
Controller
HIN
LIN
LO
COM
VB
VSVDD
SD
HIN
NC
15
NC
HO
VSS
NC
14
16
13
12
11
10
2
3
1
4
8
6
7
LIN VCC
SD
15V
Load
NC 5
NC9
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 3
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Internal Block Diagram
Figure 3. Functional Block Diagram (Referenced 14-Pin)
Figure 4. Functional Block Diagram (Referenced 16-SOP)
UVLO DR
IVERPULSE
GEN
ERA
TORHIN
VCC
COM
VB
VS
RRS Q
DR
IVER
HS(ON/OFF)
LS(ON/OFF) DELAY
LIN UVLO
HO
LO
SCHMITT TRIGGER INPUT
CYCLE-By-CYCLE EDGE TRIGGERED
SHUTDOWN
NOISECANCELLER
VSS/COMLEVELSHIFT
VSS
10
12
13
Pin 4, 8, and 14 are no connection
SD 11
VDD 9
3
2
6
5
1
7
UVLO DR
IVERPULSE
GEN
ERA
TORHIN
VCC
COM
VB
VS
RRS Q
DR
IVER
HS(ON/OFF)
LS(ON/OFF) DELAY
LIN UVLO
HO
LO
SCHMITT TRIGGER INPUT
CYCLE-By-CYCLE EDGE TRIGGERED
SHUTDOWN
NOISECANCELLER
VSS/COMLEVELSHIFT
VSS
12
14
15
Pin 4, 5, 9,10 and 16 are no connection
SD 13
VDD 11
3
2
7
6
1
8
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 4
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Pin Configuration
Figure 5. Pin Configurations (Top View)
Pin Definitions14-Pin 16-Pin Name Description
1 1 LO Low-Side Driver Output
2 2 COM Low-Side Return
3 3 VCC Low-Side Supply Voltage
5 6 VS High-Voltage Floating Supply Return
6 7 VB High-Side Floating Supply
7 8 HO High-Side Driver Output
9 11 VDD Logic Supply Voltage
10 12 HIN Logic Input for High-Side Gate Driver Output
11 13 SD Logic Input for Shutdown Function
12 14 LIN Logic Input for Low-Side Gate Driver Output
13 15 VSS Logic Ground
4,8,14 4, 5, 9, 10, 16 NC No Connect
LO
NC
FAN
7392 HIN
HO NC
VDD
COM
VB
VS
VSS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SD
NC
VCC LIN
LO
NC
FAN
7392MHIN
HO
NC
VDD
COM
VB
VS
VSS
1
2
3
4
5
6
7
16
15
14
13 SD
NC
VCC LIN
12
11
10
98
NC
NC
(a) 14-DIP (b) 16-SOP (Wide Body)
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 5
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Absolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. Theabsolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified.
Notes: 1. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material).2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions, natural convection; andJESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
3. Do not exceed power dissipation (PD) under any circumstances.
Recommended Operating ConditionsThe Recommended Operating Conditions table defines the conditions for actual device operation. Recommendedoperating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does notrecommend exceeding them or designing to absolute maximum ratings.
Symbol Characteristics Min. Max. UnitVB High-Side Floating Supply Voltage -0.3 625.0 V
VS High-Side Floating Offset Voltage VB-25.0 VB+0.3 V
VHO High-Side Floating Output Voltage VS-0.3 VB+0.3 V
VCC Low-Side Supply Voltage -0.3 25.0 V
VLO Low-Side Floating Output Voltage -0.3 VCC+0.3 V
VDD Logic Supply Voltage -0.3 VSS+25.0 V
VSS Logic Supply Offset Voltage VCC-25.0 VCC+0.3 V
VIN Logic Input Voltage (HIN, LIN and SD) VSS-0.3 VDD+0.3 V
dVS/dt Allowable Offset Voltage Slew Rate ±50 V/ns
PD Power Dissipation(1, 2, 3) 14-PDIP 1.6W
16-SOP 1.3
θJA Thermal Resistance14-PDIP 75
°C/W 16-SOP 95
TJ Maximum Junction Temperature +150 °C
TSTG Storage Temperature -55 +150 °C
Symbol Parameter Min. Max. UnitVB High-Side Floating Supply Voltage VS+10 VS+20 V
VS High-Side Floating Supply Offset Voltage 6-VCC 600 V
VHO High-Side Output Voltage VS VB V
VCC Low-Side Supply Voltage 10 20 V
VLO Low-Side Output Voltage 0 VCC V
VDD Logic Supply Voltage VSS+3 VSS+20 V
VSS Logic Supply Offset Voltage -5 5 V
VIN Logic Input Voltage VSS VDD V
TA Operating Ambient Temperature -40 +125 °C
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 6
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Electrical Characteristics VBIAS(VCC, VBS, VDD)=15.0V, VSS=COM=0V and TA=25°C, unless otherwise specified. The VIH, VIL, and IINparameters are referenced to VSS and are applicable to the respective input leads: HIN, LIN, and SD. The VO and IOparameters are referenced to VS and COM and are applicable to the respective output leads: HO and LO.
Symbol Characteristics Test Condition Min. Typ. Max. UnitLow-Side Power Supply Section
IQCC Quiescent VCC Supply Current VIN=0V or VDD 40 80 μA
IQDD Quiescent VDD Supply Current VIN=0V or VDD 10 μA
IPCC Operating VCC Supply Current fIN=20kHz, rms, VIN=15VPP 430 μA
IPDD Operating VDD Supply Current fIN=20kHz, rms, VIN=15VPP 300 μA
ISD Shutdown Supply Current SD=VDD 120 μA
VCCUV+VCC Supply Under-Voltage Positive-Going Threshold Voltage
VIN=0V, VCC=Sweep 7.7 8.8 9.9 V
VCCUV-VCC Supply Under-Voltage Negative-Going Threshold Voltage
VIN=0V, VCC=Sweep 7.3 8.4 9.5 V
VCCUVHVCC Supply Under-Voltage Lockout Hysteresis Voltage
VIN=0V, VCC=Sweep 0.4 V
Bootstrapped Supply Section
IQBS Quiescent VBS Supply Current VIN=0V or VDD 60 130 μA
IPBS Operating VBS Supply Current fIN=20kHz, rms value 500 μA
VBSUV+VBS Supply Under-Voltage Positive-Going Threshold Voltage
VIN=0V, VBS=Sweep 7.7 8.8 9.9 V
VBSUV-VBS Supply Under-Voltage Negative-Going Threshold Voltage
VIN=0V, VBS=Sweep 7.3 8.4 9.5 V
VBSUVHVBS Supply Under-Voltage Lockout Hysteresis Voltage
VIN=0V, VBS=Sweep 0.4 V
ILK Offset Supply Leakage Current VB=VS=600V 50 μA
Input Locic Section (HIN, LIN, and SD)
VIH Logic “1” Input Threshold VoltageVDD=3V 2.4 V
VDD=15V 9.5 V
VIL Logic “0” Input Threshold VoltageVDD=3V 0.8 V
VDD=15V 6.0 V
IIN+ Logic Input High Bias Current VIN=VDD 20 40 μA
IIN- Logic Input Low Bias Current VIN=0V 3 μA
RIN Logic Input Pull-Down Resistance 375 750 KΩ
Gate Driver Output Section
VOH High-Level Output Voltage (VBIAS - VO) No Load (IO=0A) 1.5 V
VOL Low-Level Output Voltage No Load (IO=0A) 200 mV
IO+ Output High, Short-Circuit Pulsed Current(4) VO=0V, PW ≤10µs 2.5 3.0 A
IO- Output Low, Short-Circuit Pulsed Current(4) VO=15V, PW ≤10µs 2.5 3.0 A
VSS/COM VSS-COM/COM-VSS Voltage Educability -5.0 5.0 V
- VSAllowable Negative VS Pin Voltage for HIN Signal Propagation to HO -9.8 -7.0 V
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 7
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Dynamic Electrical Characteristics VBIAS(VCC, VBS, VDD)=15.0V, VSS=COM=0V, CLOAD=1000pF, TA=25°C, unless otherwise specified.
Note: 4. These parameters guaranteed by design.
Symbol Parameter Conditions Min. Typ. Max. Unitton Turn-On Propagation Delay Time VS=0V 130 180 ns
toff Turn-Off Propagation Delay Time VS=0V 150 200 ns
tsd Shutdown propagation Delay Time(4) 130 180 ns
tr Turn-On Rise Time 25 50 ns
tf Turn-Off Fall Time 20 45 ns
MT Delay Matching, HO & LO Turn-On/Off 35 ns
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 8
Typical Characteristics
Figure 6. Turn-On Propagation Delay vs. Temperature
Figure 7. Turn-Off Propagation Delay vs. Temperature
Figure 8. Turn-On Rise Time vs. Temperature
Figure 9. Turn-Off Fall Time vs. Temperature
Figure 10. Turn-On Delay Matching vs. Temperature Figure 11. Turn-Off Delay Matching vs. Temperature
-40 -20 0 20 40 60 80 100 12080
100
120
140
160
180
t ON [n
s]
Temperature [°C]-40 -20 0 20 40 60 80 100 120
100
120
140
160
180
200
t OFF
[ns]
Temperature [°C]
-40 -20 0 20 40 60 80 100 1200
10
20
30
40
50
t R [n
s]
Temperature [°C]-40 -20 0 20 40 60 80 100 1200
10
20
30
40
50
t F [n
s]
Temperature [°C]
-40 -20 0 20 40 60 80 100 1200
10
20
30
MT O
N [n
s]
Temperature [°C]-40 -20 0 20 40 60 80 100 1200
10
20
30
MT O
FF [n
s]
Temperature [°C]
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 9
Typical Characteristics (Continued)
Figure 12. Shutdown Propagation Delay vs. Temperature
Figure 13. Logic Input High Bias Current vs. Temperature
Figure 14. Quiescent VCC Supply Current vs. Temperature
Figure 15. Quiescent VBS Supply Current vs. Temperature
Figure 16. Operating VCC Supply Current vs. Temperature
Figure 17. Operating VBS Supply Current vs. Temperature
-40 -20 0 20 40 60 80 100 12080
100
120
140
160
180
t SD [n
s]
Temperature [°C]-40 -20 0 20 40 60 80 100 1200
10
20
30
40
I IN+ [
μA]
Temperature [°C]
-40 -20 0 20 40 60 80 100 1200
10
20
30
40
50
60
70
80
I QC
C [
μA]
Temperature [°C]-40 -20 0 20 40 60 80 100 1200
20
40
60
80
100
120
I Q
BS [
μA]
Temperature [°C]
-40 -20 0 20 40 60 80 100 1200
200
400
600
800
1000
I PC
C [
μA]
Temperature [°C]-40 -20 0 20 40 60 80 100 1200
200
400
600
800
1000
I PBS [
μA]
Temperature [°C]
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 10
Typical Characteristics (Continued)
Figure 18. VCC UVLO+ vs. Temperature Figure 19. VCC UVLO- vs. Temperature
Figure 20. VBS UVLO+ vs. Temperature Figure 21. VBS UVLO- vs. Temperature
Figure 22. High-Level Output Voltage vs. Temperature
Figure 23. Low-Level Output Voltage vs. Temperature
-40 -20 0 20 40 60 80 100 120
8.0
8.5
9.0
9.5
V CC
UV
+ [V]
Temperature [°C]-40 -20 0 20 40 60 80 100 120
7.5
8.0
8.5
9.0
9.5
VC
CU
V- [V
]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120
8.0
8.5
9.0
9.5
VB
SUV+
[V]
Temperature [°C]-40 -20 0 20 40 60 80 100 120
7.5
8.0
8.5
9.0
9.5
V B
SU
V- [V
]
Temperature [°C]
-40 -20 0 20 40 60 80 100 1200.0
0.5
1.0
1.5
VO
H [V
]
Temperature [°C]-40 -20 0 20 40 60 80 100 120
-20
-15
-10
-5
0
5
10
15
20
VO
L [mV
]
Temperature [°C]
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 11
Typical Characteristics (Continued)
Figure 24. Logic High Input Voltage vs. Temperature
Figure 25. Logic Low Input Voltage vs. Temperature
Figure 26. Allowable Negative VS Voltage vs. Temperature
Figure 27. Input Logic (HIN & LIN) Threshold Voltage vs. VDD Supply Voltage
.
Figure 28. Allowable Negative Vs Voltage for HIN Signal Propagation to High Side vs. Supply Voltage
-40 -20 0 20 40 60 80 100 1206
7
8
9
10
11
V IH [V
]
Temperature [°C]-40 -20 0 20 40 60 80 100 1203
4
5
6
7
8
9
10
VIL [V
]
Temperature [°C]
-40 -20 0 20 40 60 80 100 120-12
-11
-10
-9
-8
-7
V S [V
]
Temperature [°C]0 2 4 6 8 10 12 14 16 18 20
0
2
4
6
8
10
12
Lo
gic
Thre
shol
d Vo
ltage
[V]
VDD Logic Supply Voltage [V]
VIH
VIL
10 11 12 13 14 15 16 17 18 19 20
-16
-14
-12
-10
-8
-6
-4
VS
[V]
Supply Voltage [V]
VCC=VBSCOM=0VTA=25°C
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 12
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Switching Time Definitions
Figure 29. Switching Time Test Circuit (Referenced 14-DIP)
Figure 30. Input/Output Timing Diagram
Figure 31. Switching Time Waveform Definitions
1nF 100nF
1nF
100nF
15V
LO
COM
VB
VS
VDD
SD
HIN
NC
13
NC
HO
VSS
NC14
11
10
9
8
LIN VCC
15V
12
2
3
1
4
7
5
6
15V
LO
HO
(0 to 600V)HIN
SD
LIN
10μF
10μF
10μF
Shutdown Skip
HINLIN
HOLO
SD
50%
90%
50%
tON
10%
tR tOFF tF
10%
90%
HINLIN
HOLO
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 13
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Switching Time Definitions (Continued)
Figure 32. Shutdown Waveform Definition
Figure 33. Delay Matching Waveform Definitions
90%
50%
tSD
HOLO
SD
HINLIN
LO
50% 50%
10%
90%
HO
MTHOLO
MT
90%
10%
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 14
Application InformationNegative VS TransientThe bootstrap circuit has the advantage of being simpleand low cost, but has some limitations. The biggest diffi-culty with this circuit is the negative voltage present atthe emitter of the high-side switching device when high-side switch is turned-off in half-bridge application.
If the high-side switch, Q1, turns-off while the load cur-rent is flowing to an inductive load, a current commuta-tion occurs from high-side switch, Q1, to the diode, D2,in parallel with the low-side switch of the same inverterleg. Then the negative voltage present at the emitter ofthe high-side switching device, just before the freewheel-ing diode, D2, starts clamping, causes load current tosuddenly flow to the low-side freewheeling diode, D2, asshown in Figure 34.
Figure 34. Half-Bridge Application CircuitsThis negative voltage can be trouble for the gate driver’s output stage, there is the possibility to develop an over-voltage condition of the bootstrap capacitor, input signal missing and latch-up problems because it directly affects the source VS pin of the gate driver, as shown in Figure 35. This undershoot voltage is called “negative VS tran-sient”.
Figure 35. VS Waveforms During Q1 Turn-Off
Figure 36 and Figure 37 show the commutation of theload current between high-side switch, Q1, and low-sidefreewheelling diode, D3, in same inverter leg. The para-sitic inductances in the inverter circuit from the die wirebonding to the PCB tracks are jumped together in LC andLE for each IGBT. When the high-side switch, Q1, andlow-side switch, Q4, are turned on, the VS1 node isbelow DC+ voltage by the voltage drops associated withthe power switch and the parasitic inductances of the cir-cuit due to load current is flows from Q1 and Q4, asshown in Figure 36. When the high-side switch, Q1, isturned off and Q4, remained turned on, the load currentto flows the low-side freewheeling diode, D3, due to theinductive load connected to VS1 as shown in Figure 37.The current flows from ground (which is connected to theCOM pin of the gate driver) to the load and the negativevoltage present at the emitter of the high-side switchingdevice.
In this case, the COM pin of the gate driver is at a higherpotential than the VS pin due to the voltage drops associ-ated with freewheeling diode, D3, and parasitic ele-ments, LC3 and LE3.
Figure 36. Q1 and Q4 Turn-On
Figure 37. Q1 Turn-Off and D3 Conducting
Q1
Q2
DC+ Bus
VS
iLOAD
ifreewheeling
Load
D1
D2
Q1
VS
Freewheeling
GND
GND
Q1
Q3
DC+ Bus
VS1
iLOAD
ifreewheeling
Q2
Q4
VS2
LC2
LE2
LC4
LE4
LC1
LE1
LC3
LE3
VLC1
VLE1
VLC4
VLE4
Load
D1
D3
D2
D4
Q1
Q3
DC+ Bus
VS1
iLOAD
ifreewheeling
Q2
Q4
VS2
LC2
LE2
LC4
LE4
LC1
LE1
LC3
LE3
VLC3
VLE3
VLC4
VLE4
D1
D3
D2
D4
Load
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 15
The FAN7392 has a negative VS transient performancecurve, as shown in Figure 38.
Figure 38. Negative VS Transient Chracteristic
Even though the FAN7392 has been shown able to han-dle these negative VS tranient conditions, it is stronglyrecommended that the circuit designer limit the negativeVS transient as much as possible by careful PCB layoutto minimized the value of parasitic elements and compo-nent use. The amplitude of negative VS voltage is pro-portional to the parasitic inductances and the turn-offspeed, di/dt, of the switching device.
General GuidelinesPrinted Circuit Board Layout The relayout recommended for minimized parasitic ele-ments is as follows:
Direct tracks between switches with no loops or devia-tion.Avoid interconnect links. These can add significant inductance.Reduce the effect of lead-inductance by lowering package height above the PCB.Consider co-locating both power switches to reduce track length. To minimize noise coupling, the ground plane should not be placed under or near the high-voltage floating side.To reduce the EM coupling and improve the power switch turn-on/off performance, the gate drive loops must be reduced as much as possible.
Placement of ComponentsThe recommended placement and selection of compo-nent as follows:
Place a bypass capacitor between the VDD and VSS pins. A ceramic 1µF capacitor is suitable for most applications. This component should be placed as close as possible to the pins to reduce parasitic ele-ments.The bypass capacitor from VCC to COM supports both the low-side driver and bootstrap capacitor recharge. A value at least ten times higher than the bootstrap capacitor is recommended. The bootstrap resistor, RBOOT, must be considered in sizing the bootstrap resistance and the current devel-oped during initial bootstrap charge. If the resistor is needed in series with the bootstrap diode, verify that VB does not fall below COM (ground). Recommended use is typically 5 ~ 10Ω that increase the VBS time constant. If the votage drop of of bootstrap resistor and diode is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra-fast recovery diode can be used.The bootstrap capacitor, CBOOT, uses a low-ESR capacitor, such as ceramic capacitor.
It is stongly recommended that the placement of compo-nents is as follows:
Place components tied to the floating voltage pins (VB and VS) near the respective high-voltage portions of the device and the FAN7392. NC (not connected) pins in this package maximize the distance between the high-voltage and low-voltage pins (see Figure 5).Place and route for bypass capacitors and gate resis-tors as close as possible to gate drive IC.Locate the bootstrap diode, DBOOT, as close as possi-ble to bootstrap capacitor, CBOOT.The bootstrap diode must use a lower forward voltage drop and minimal switching time as soon as possible for fast recovery or ultra-fast diode.
0
-10
100 200 300 400 500 600 700 800 900 1000
Pulse Width [ns]
V S [V
]
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 16
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Physical Dimensions .
Figure 39. 14-Lead Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any mannerwithout notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify orobtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:http://www.fairchildsemi.com/packaging/.
14 8
71
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS.
C)DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER
ASME Y14.5-1994E) DRAWING FILE NAME: MKT-N14AREV7
6.606.09
8.127.62
0.350.20
19.5618.80
3.563.30 5.33 MAX
0.38 MIN
1.771.14
0.580.35 2.54
3.813.17 8.82
(1.74)
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 17
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
Physical Dimensions (Continued)
.
Figure 40. 16-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any mannerwithout notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify orobtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:http://www.fairchildsemi.com/packaging/.
pdip8_dim.pdf
2.65 MAX
M16BREV2
0.20±0.10
0.10 C
C
10.30±0.20 A
SEE DETAIL A
0.330.20
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC MS-013, ISSUE E, DATED SEPT 2005.
B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P1030X265-16L
9.44
PIN ONEINDICATOR
0.25
1
1.270.510.35
8
BC AM
10.325
16 9
8.890
7.50±0.10
B
X 45°0.750.25
(R0.10)
(R0.10)
0.40~1.27
8°0°
SEATING PLANE
(1.40)
0.25
GAGE PLANE
DETAIL ASCALE: 2:1
SEATING PLANE
1.27 TYP
0.55 TYP
LAND PATTERN RECOMMENDATION
1.75 TYP
9.2 10.95
E) DRAWING FILENAME: MKT-16Brev2
FAN
7392 — H
igh-Current, H
igh- and Low-Side, G
ate-Drive IC
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.comFAN7392 Rev. 1.0.2 18