AbstractIn today’s technologies,resistiveshortingandopendefectsare becomingmore predominant.Conventionalfault mod-els,and tools basedon thesemodelsare becominginade-quatein addressingthesedefectsresultingfromnew failuremechanisms.In prior works iDDT testingtechniqueshavebeenshownto detectresistivedefects.However, in order toincorporateiDDT basedmethodsinto productiontestflows,it is necessaryto develop a fault simulation strategy toenableATPG and fault coverage to be determined.To ourknowledge, no practical techniqueexists to perform faultsimulationfor iDDT basedmethods.At theheartof thediffi-cultyof developinga fault simulationstrategy is theanalognature of thetestobservable. In this paperweinvestigateafault simulationmodelthatpartitionsthetaskof simulatingthe CUT (chip undertest)into linear and non-linearcom-ponents.Wealsoproposea pathisolationstrategy for core-logic asa meansof reducingthecomputationalcomplexityinvolvedin derivingiDDT signalsin thenon-linearportion.More specificallyan ImpulseResponsebasedmethodisderivedto eliminatethe needfor transientsimulationsofthe entire CUT.��� ������� ��������������

Existing fault modelsarebecomingincreasinglyinef-fective in modelingdefectmechanismsin DSM technolo-gies.For example,thechangefrom asubtractivealuminumprocessto damasceneCu mayleadto moreparticle-relatedblocked-etchresistive opens[1]. Also, technologyscalingincreasestheprobabilityof resistive viascausedby incom-plete etch. This suggeststhe needfor screeningmecha-nisms that can target such resistive type of defects.

Previous researchon iDDT test,suchas[2-8], [11-12],shows thatchangesin thecircuit configurationcausedby adefect,manifestsitself asanomaliesin thetransientsignalsmeasuredat thepower supplyports.Themethodologypre-sentedin this paperis applicableto any of theseiDDT testmethods.However, we feel that the methoddescribedin[17], calledTransientSignalAnalysis(TSA), is betterableto exploit the full potentialof iDDT testing.Therefore,weuseTSA asa vehiclefor screeningdefectsin theproposedfault simulationflow. TSA is an iDDT testtechniquebasedon crosscorrelationof multiple iDDT signalsmeasuredatpower supply ports in a CUT.

The integrationof TSA or other iDDT test techniquesinto existing productiontest flows requirestools for per-forming ATPG and fault simulations.A fault simulation

engine,for such techniques,must generateiDDT signalsthat aresubsequentlyprocessedusingthedefectscreeningprocedure.This implies the needfor performingtransientsimulations on the entire CUT. The memory and timerequirementsof such simulationsare prohibitive. In thispaperwe proposea modelthatcanbeusedto implementapracticalfault simulatorfor iDDT testing.This is achievedby decomposingthe CUT into two systemsand individu-ally analyzingthe meansof reducingthe simulationcom-plexity of thesesystems.The two systemsinvolve, 1) alinearconstituent,namely, thepower grid and2) a non-lin-earcore logic circuit. A uniquemethodbasedon impulseresponse(IR) and convolution is proposedfor the linearpowergrid component.Thismethodallowssimulation-lesscomputationof thepower grid responseto transientinputsproducedfrom thecorelogic (non-linear)component.Fur-thermore,a path isolation schemeis proposedto addressthe simulation complexity of the non-linear component.� � ������������ ������

Testingmethodsbasedontheanalysisof powersupplytransientsignalsaredescribedin [2-6], [11-12] for digitalcircuitsandin [7-8] for analogcircuits.However, we havenotuncoveredany prior work thatproposesmodelsthatcanenablefault simulationof iDDT testvectors.In additiontoproviding a practicalmethodologyfor iDDT fault simula-tion, we believe that this work canbe leveragedfor powerverification and signal integrity analysis. This is truebecausethesetaskssharetherequirementof transientsim-ulations. The former analyzesthese signals to identifyanomaliescausedby defectswhereas,the latter processesdynamic IR and Ldi/dt drop, and package/on-chipreso-nance.

Due to signal integrity problemscausedby aggres-sively increasingdevice densities,simulationof transientpowerdistribution in achiphasbecomeanessentialstepinpower verification.To meetthis growing requirementsev-eral static and transientsimulation techniqueshave beenproposedin thepastdecade.Mathematicaltoolsthatspeed-up the power grid simulations,suchas [15], [18-20] andmethodsbasedon TransientCurrent Simulation of logiccircuits[9], [13] and[16] have beenproposed.Theseallowderivation of transient currents drawn by logic circuitswithout running SPICE level transient simulations.

Fault Simulation Model for iDDT Testing:An Investigation

Abhishek Singh, Chintan Patel and Jim Plusquellic

Department of Computer Engineering, University of Maryland, Baltimore County

abhishek, cpatel2, plusquel@cs.umbc.edu

� � �� "!$#%��&�')(+*$&�,*-��&�.Any digital CMOSchip canbemodeledasacombina-

tion of two complementaryelectricalsystems,a linear RCsystemformed by the power (VDD and GND) grid and anon-linearRC-transistorsystemformedby the underlyingCMOSlogic circuit. For example,Figure1 showsaportionof a typical row basedstandard-celldesign.Theupperhalf

of the figure depictsthe power grid, laid out asa stackofuniformly spacedmetal runnersat alternatinglayerscon-nectedusing stacked contacts.(For simplicity only a twolayer structure is shown) The parasitic resistanceandcapacitanceof the power grid along with the on-chipdecouplingcapacitorsform a linearRC system.This linearsystemis referredto asPowerGrid Circuit (PGC). In real-ity thephysicalstructureof metalrails comprisinga powergrid alsocontributesa significantamountof inductance(L),therebyrenderingit a three-dimensionalRLC laddercir-cuit. In thiswork, weignoretheinductivecomponentof thepower grid for simplicity. It mustberealizedthat this doesnot have any bearingon the proposedconceptof systempartitioning.This is truebecauseL, likeR andC, is a linearcomponentand does not affect the linear nature of thePGC.

Thelower half of thefigureshows thecorelogic com-prising thestandard-cells(MOS-transistors)andthesignalrouting of the chip. Since,MOS-transistorsare inherentlynon-lineardevices,this portion forms a non-linearelectri-cal system,referredto as Core Logic Circuit (CLC). Thelocal VDD andGND runnerson thestandard-cellsarecon-nectedto the global power grid at variouspoints throughspecialnets/viascalledfollow-pins, asindicatedin thefig-ure.

A transitionsequenceappliedat theprimaryinputs(oroutputsof scanlatches)causesthegatesalonga sensitizedpathto switchin a temporalsequence.Eachswitchinggatedraws transientcurrent(iDS) from the power grid, sourcedby theexternalpower supplypadsor C4s.ThePGCtrans-forms theseiDS signalsinto compositecurrent transients(iDDT) that are measuredat the C4s.Therefore,the CUTcan be modeledas a cascadeof two electrical systemswherein,theoutputstheCLC feedstheinputsof PGC.Thetransientcurrentdrawn by aCMOSgatecanbemodeledas

Figure 1. Linear and non-linear systemrepresentation of a chip.

SUBSTRATE

VDD Runners GND RunnersVDD C4

GND C4

StackedContacts

Follow-Pin

Power

(linear

Core

(non-linear

Std. CellLocal GND

Local VDD

Local Signal Routing

Grid

system)

Logic

system)

a PWL current sourceconnectedbetweenthe VDD andGND grid. Themetallayeratwhich theCUT is partitionedinto the above two systems,determinesthe sparsenessofthe input and output ports in the PGC and CLC respec-tively./ � �10$���2��3 "��'4�2����������50-2���.768��9�;:�:�<>=$&?#%�������

Thefault simulationprocedurefor iDDT testingcanbedescribedusing a flow diagramshown in Figure 2. Thesubsequentsectionsof this paperelaborateon eachpartofthe flow diagram.

Step1: System Partitioning: The most importantstepin the flow is the partitioning of the CUT into a linear(PGC) and a non-linear (CLC) electrical system.

Step2: Power Grid Characterization: Powergrid char-acterizationinvolvesthederivationof IR functionsbetweeneachinput-outputport of thepower grid. TheIR functions,by definition, completelycharacterizethe power grid andcanusedto derive its responseto any arbitraryinput usingconvolution.

Step3: Generation of Iso-IR Bands: An iso-IR banddefinesa physical region in the grid layout consistingofinput locationsthatarecharacterizedby a similar IR. Sucha categorizationhelpsin significantlyreducingthenumberof convolution operationsrequiredto generatethe powergrid response.

Step4: Fault Injection: A fault is injectedbetweentwonodesin the layout of the CUT by introducing resistiveconnectionmodelingresistive shorts/bridgesor opens.Theadvantagesof using layout information are 1) the faultmodel closely representsthe physical defectsand2) onlyphysicallyadjacentnetsareconsideredasshort/bridgecan-didates.We believe that this fault injectionschemecloselyfollows the defect based test paradigm.

Step5: Isolated-Path Transient Simulation: An iso-latedpathcorrespondsto asensitizedpaththatis physicallyseparatedfrom the chip layout by breakingconnectionswith theunsensitizedlogic andthepower grid, while, pre-servingthe fanoutloadsandthe signalconnectionsof thegates within the sensitizedpath. The transient currentwaveformgeneratedby thecorelogic ateachinput locationin theCLC canbederived throughSPICEor time-domainCurrent Waveform Simulations of these isolated paths.

Step6: Iso-IR Band Selection: Basedon the physicallocationof the input currentsource,the iso-IR bandcorre-sponding to that input is identified.

Figure 2. Flow diagram of the fault simulationprocedure for iDDT testing.

Power Grid Characterization

Iso-Impulse Response (IR) Band Generation IR Band Selection

Convolution

SuperpositioniDDT Generation using

Defect DetectioniDDT Analysis for

Test Pattern Application

Upd

ate

Cove

rage

YesNo

Cha

nge

Test

Pat

tern

/Faul

t

Isolated-Path Simulation(SPICE or Current Waveform

Simulation)

FaultDetected?

Delay Fault Injection

System Partitioning

Step7: Convolution: TheiDDT or iDS waveformsmea-suredat specificnodesduringtheisolatedpathsimulationsare convolved with the IR functions of the iso-IR bandselected in the previous step.

Step8: Linear Superposition: By the virtue of super-positionpropertyof linear time invariant(LTI) systemsthepower grid responseto individual currentinput sourcecanbe combinedthrough linear superpositionto derive theoverall responseof the grid at a given C4. This propertyallowsusto simulateall thesensitizedpathsindependently.Another major advantageof this property is to limit themaximum numberof convolution operationsrequired toderive theoverall responseof thePGC.This is detailedfur-ther in the paper.

Step9: iDDT analysis for fault detection: The iDDTsthusobtainedat theC4s,includesthecurrentdrawn by thedefectandthedefect-freelogic. TheseiDDTscanbeusedasthe input for TSA or asinput to a similar techniqueusingthe RLC modelof the probecardasa meansof obtainingtheoverall response.In eithercase,theoutputof this faultsimulation procedureis the basis for a) determiningtheiDDT-testcoverageof agivensetof testpatterns,b) guidingthe ATPG algorithm to generatevectorsthat canenhancethedetectabilityof thedefectandc) determiningtherangeof resistancevaluesfor which a resistive short, open orbridging defect is detectable.@ � �� "!$#%��&�')A��B���������C������

The CUT is decomposedinto a linear andnon-linearsystemby breakingthe physical connectionsbetweenthepower grid and the core logic cells. The metal layer atwhich the connectionsare broken definesthe partitioningscheme.For example,Figure 3 shows two possibleparti-tioning schemes.In onecasethepartitioningis doneat the

follow-pins whereas,in the secondcasethe partitioningisdoneat thenodeswhereMOS transistorsin eachstandard-cell connectsto thelocalVDD/GND rails.The“cross”sym-bol indicatesthenodesatwhich theconnectionsarebrokenin eachscheme.Thesameis true for GND grid not shownin thefigure.In thefirst case,referredto asFP-scheme(forfollow-pins), the linearsystem(PGC)consistof theglobalpower-grid andthenon-linearsystem(CLC) consistsof thestandard-cells,includingtheir localVDD/GND railsandthesignal routing. In the secondcase,referredto as the TR-scheme(for transistors),thePGCincludestheglobalpowergrid aswell asthelocal VDD/GND rails in eachrow of thecorelogic andtheCLC includesthestandard-cells(without

Figure 3. Partitioning schemes of a chip intolinear and non-linear systems.

Global VDD Grid

Local VDD Railsof Std. Cells

Standard-Cells

FP-Scheme

Follow-Pins

TR-Scheme

VDD/GND rails) and the signal routing. The locations(ornodes)at which the systemsare partitionedrepresenttheinput-portsof the PGC and output-portsof the CLC. Forthe TR-scheme,when the sourcenodesof more thanoneMOS-transistorare connecteddirectly to the local VDD/GND rails, which may be true for complex standardcells,any onenodecanbeconsideredasanoutput.This is a rea-sonableassumptiongiven that the impedancebetweenanytwo pointson the local VDD (or GND) rail in a standard-cell is sufficiently small.TheFP-schemeoffersfewer num-berof input-outputports,reducingthecomplexity involvedin thePGCcharacterizationbut mayincreasethecomplex-ity of core-logic(non-linear)simulationdueto inclusionoflocal VDD/GND metal rails in the CLC. In contrast,theTR-schemeoffers larger number of input-output portswhich increasesthe complexity of PGC characterizationbut simplifies the core-logicsimulations.Thesetrade-offswill be revisited in the subsequent sections.D � ��A��.E&�GF+,���IH3��B������3J�A�FKH3LHNM��� ������&�B��O����������

In current technologiesthe VDD/GND routing canoccupy morethan25% of the total routing areaon a chipandthusconsistof millions of linearelements.SPICEsim-ulationson thesegridscanbeveryexpensiveandtherefore,several techniques,suchas[15], [18], [19] and[20], havebeenproposedfor fast power grid simulation.Even thesetools may prove infeasibleas the basesimulationenginefor an iDDT fault simulator, due to the large numberoffaultsandtestvectors.We demonstratea convolution pro-cedurebasedon the linearity property of the PGC thatenablesusto computethepower-grid responseto theinputswitching transientsfrom the core logic without runningsimulations.

Any linear time invariant (LTI) systemcan be com-pletelycharacterizedby its ImpulseResponse(IR) functiondenotedash(t). The impulseresponseh(t), is theoutputofthesystemto aunit impulsefunction,δ(t). OncetheIR of alinearsystemis known, wemayconstructtheresponseof athesystemto anarbitraryinput signalasa sumof suitablydelayed and scaled impulse responses.This processiscalled convolution and is mathematicallydescribedusingEq.1. Here,f(t) is theinput signal,g(t) is theoutputsignal

andh(t) is theIR function.Theresponseof a linearsystemto anarbitraryinputsignalcanthusbecomputedby convo-lution using the IR function in time domain.

The PGC representsa multi-input and multi-outputlinear system.Eachinput on the grid seesa differentRCnetwork to eachof theoutputs(C4s)therefore,thereexistsa uniqueIR functionfor eachinput-outputpair, denotedas

g t( ) h t( ) f t( )⊗ h u( ) f t u–( ) ud∞–∞∫= = PRQRSUTUS

h t u–( ) f u( ) ud∞–∞∫=

hij(t), wherei and j representsthe input andoutputport ofthePGCrespectively. A setof suchIR functions,hij(t), canbeusedto characterizethePGC.Oncethegrid is character-ized, its responseto transientinputscanbe determinedbyconvolving the transientswith the correspondingIR func-tions. Superpositionand shift-invariancepropertiesof aLTI systemareusedto determinetheoutputsdueto 1) mul-tiple switchinggateswithin a sensitizedpathand2) multi-ple sensitizedpathsunder the sameinput sequence.Thiscaneliminatetheneedto simulatemillions of RC elementswith a fixed numberof multiplication andadditionopera-tions during the fault simulation.V � ��W"X?YZ&�,��'[&������23 &�����Y

Figure4(a) shows a portion of the commercialpowergrid subsequentlyreferredto astheQuad.TheQuadoccu-

piesa 10,000by 10,000unit areaandinterfacesto a setofexternalpower suppliesthroughan areaarrayof VDD andGND C4 pads.As indicatedin thefigure, thereare4 VDD

C4sand6 GND C4sin this portionof thegrid. Figure4(b)shows that the grid is constructedover 4 layersof metal,with metal1 (M1) andmetal3 (M3) runningvertically andM2 andM4 runninghorizontally. TheC4sareconnectedtowide runnersof verticalM5, shown in Figure4(a),thatarein turn connectedto the M1-M4 grid. In each layer ofmetal,the VDD andGND rails alternate.Stacked contactsareplacedat theappropriatecrossingsof thehorizontalandvertical rails.

We derivedanRC modelof theQuadusinganextrac-tion scriptthatpreservesthephysicalstructureof themetalinterconnectin thetopologyof theRC network, i.e. no net-work reductionheuristicsare applied.The resistancepersquare and the overlap capacitancesper unit area ofTSMC’s 0.25µm 5 metal processused in the extractionprocess were obtained from published parametersbyMOSIS [21].

In this experimentwe considerthe Quadas the PGCand a custom designed16-bit logarithmic adder as theCLC. Weinserted~3000labelsat theM1-M2 crossoversinthe grid layout to representpossibleinput locationson thePGC.

Figure 4. The “Quad”: A portion of thecommercial power grid used in the simulation

experiments.

Vdd Rail

Gnd Rail

M1

M2

M3

M4

Contacts

VDD1

C4Pads

(a) (b)

M5

VDD0 VDD2

VDD3Gnd2 Gnd5

Gnd1

Gnd0

Gnd4

Gnd3

The impulseresponsefrom eachof the input ports totheC4sareobtainedby first stimulatingthegrid at eachofthe input ports with a unit stepinput. This gives the stepresponse,sij(t), of the grid with respectto input location i

andoutput j. The impulseresponse,hij(t), canbe derivedfrom the step response,sij(t), using the differentiationintime domain.This is again dueto the linearity propertyofthesystemandcanbedescribedusingEq.2, whereδ(t) andu(t) representunit impulseandstepinput functions,respec-tively andh(t) ands(t) representthe unit impulseandstepresponse of the linear system, respectively.

Figure5(a) shows a subsetof the possibleinput loca-tions in the quad. It also indicatesthe IR functions that

existsbetweena sourcelocation,i, to eachof thefour out-puts.Thestepresponsecurves,sij(t), obtainedusingSPICEsimulationsareshown in Figure5(b) andthe IR functionsobtained after the differentiation operation on sij(t) areshown in Figure 5(c).

To verify the convolution basedprocedure,the PGCwasstimulatedwith a trianglecurrentsourceshown in Fig-ure6(a).TheresultsobtainedusingtheSPICEsimulationsaresuperimposedwith the responseobtainedby convolv-ing thetriangleinputwith theIR functioncorrespondingtothatcurrentsourcelocationin Figure6(b).As shown in the

δ t( )td

du t( ) h t( )

tdd

s t( )=⇒= P\QRSU]US

Figure 5. (a) IRs from a sample current sourcelocation, i, to all the C4s. (b) Step response. (c)

Impulse Response.

VDD1

VDD0

VDD3

VDD2

hi1(t)

hi0(t) hi2(t)

hi3(t)

(a)

(c)

(b)Tue Sep 16 22:40:04 2003

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249.95

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789.65

857.11

924.58

992.04

1059.50

1126.96

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1396.81

1464.28

1531.74

1599.20

1666.66

1734.13

1801.59

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1282.71

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0

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Res

pons

eS

tep

si0(t)

si1(t)si2(t)si3(t)

(mill

i)

Figure6. a) Triangle input curr ent to the PGC (b)Superimposed SPICE and Convolution responses.

Thu Sep 18 01:49:40 2003

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Cur

rent

Thu Sep 18 01:57:29 2003

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11.05

12.84

14.64

16.43

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20.02

21.81

23.61

25.40

27.20

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)

Triangle Input

Cur

rent

(a) (b)

to the PGC

figure the two curves are almost identical.

7.1 Iso-IR ContoursEq. 3 givestheexpressionfor convolution sumof dis-

cretesignalswhereg[i] , h[i] andf[i] representstheoutput,IR andinput of thelinearsystemrespectively. If f[i] is a N

point signal,h[i] is a M point signaltheng[i] is a N+M-1point signal as given by the above equation.Eq. 3 showsthat theconvolution basedmethodrequiresN*M additionsand multiplications.Thus, the complexity involved in thecomputationof grid responseis significantly reducedascomparedto a SPICE simulation based approachthatinvolves solving several partial differential equations.

Comparisonof IR functioncurvesfrom adjacentinputlocationssuggeststhattheiramplitudeandshapecharacter-istics vary slowly asa function of distance.ThusIR func-tions from adjacentinput locations,within a userdefinedthreshold, can be grouped into regions or bands. Thethresholdis chosenbasedontolerabledifferencein theout-put waveformsobtainedusingEq.3. However, selectionofa suitablethresholdrequiresa meansof quantifying thesimilarity betweentwo waveformsin termsof their shapecharacteristics.This similarity analysisis performedusingcross-correlation and auto-correlation operations.

Cross-correlationof two waveformsresultsinto a thirdwaveform, the amplitudeof which indicatesthe degreeofsimilarity betweenthe two waveforms.Also, the locationof its peakindicatesthe time-shift requiredin the secondsignal to obtain the maximummatchwith the first wave-form. This is mathematicallyexpressedby Eq. 4, whererxy[i] representscross-correlationof two waveforms x[i]

andy[i] . Whenx[i] andy[i] areidentical,the operationis

termed as auto-correlation,ax(t). The peak value of anauto-correlation function provides us the maximumexpectedvaluefor the degreeof similarity in the IR func-tions.

First, the input locationsare sortedin an ascendingorderof their euclidiandistancewith respectto a referencelocation.Thecreationof anew iso-IR bandbeginswith theselectionof an representative location,referredto asfocusof the iso-IR band,which is the first input location in thedistance-sortedlist andis not a partof any previously iden-

g i[ ] h i[ ] f i[ ]⊗ hj 0=

M 1–∑ j[ ] f i j–[ ]= =

fj 0=

N 1–∑ j[ ]h i j–[ ]=

PRQRSU^US

r xy i[ ] x i[ ] y i[ ]⊕ xj 0=

M 1–∑ j[ ]y j i–[ ]= =

ax i[ ] x i[ ] x i[ ]⊕ xj 0=

M 1–∑ j[ ]x j i–[ ]= =

PRQRSU_US

tified iso-IR band.TheIR functionof thefocusis auto-cor-related to obtain the maximum expected degree ofsimilarity, max(afi(t)). The algorithm then searchestheentiregrid spaceto find all input locationsthathave a peakcross-correlationvaluenot exceeding5% (selecteddiffer-encetolerance)of the peakauto-correlationvalue of thefocus. This condition is given by Eq. 5.

Figure 7 shows the Quadwith the iso-IR band limitcontours.A bandis enclosedwithin two iso-IR limit con-tours.For thepurposeof clarity only every othercontourisshown in the figure.Using the differencetoleranceof 5%,28 iso-IR contourswereobtained.This shows a factorof100reductionin thenumberof IR functions(~3000to ~30)requiredto generatethe responseof the PGC within thegiven difference tolerance.

The categorizationof IR functions into iso-IR bandsreducesthemaximumnumberof convolution operationstothe total numberof identifiediso-IR bands.This is duetothe superpositionproperty of a linear systemexplainedusingEq.6. WhereB representsthetotal numberof iso-IR

bandsonthegrid andSrepresentsthetotalnumberof inputlocationsinsidea given iso-IR band.As the equationsug-gests the output yC40[n] is a linear superpositionofresponsesdueto eachiso-IR band,yj[n] . Ideally, computa-

PRQRSU`USmax r f ih jt( )

0.05 max a f it( )

⋅≤

Where the quantity on the left represents the cross-correlation of the

The quantity on the right represents the auto-correlation of focus’sIR function.

IR function of focus with the IR function of any other location hj(t).

Figure 7. Iso-IR contours depicting the regionswith similar impulse response at C4 VDD0.

VDD1

VDD0

VDD3

VDD2

PRQRSUaUSyC40 n[ ] yj n[ ]j 0=

B

∑=

yj n[ ] hi n[ ] f i n[ ]⊗i 0=

S

∑ h n[ ] f i n[ ]i 0=

S

∑⊗= =

Where yC40[n] is the overall response (iDDT) measured at C40,yj[n] is response due the inputs in an iso-IR band (j) at C40,hi[n] is the IR function from each input in an iso-IR band to C40,fi[n] is the input signal inside an iso-IR band and h[n] represents theIR function of the focus.

tion of eachyj[n] requiresSconvolutions,however, duetocreationof iso-IR bandsthe complexity involved in thecomputationof eachyj[n] reducesto a singleconvolutionoperation.This helpsto reducethe total numberof convo-lutions toB.b � ��W"X?YZ&�,��'[&������2dcE&?#%���-�

Theaccuracy of theiso-IRbandbasedfault simulationprocedureis verified using a full-custom designed16-bitlogarithmicadderasa representative of thesensitizedpor-tion in the CLC. Figure8(a) shows the approximateloca-tion of the adderin the lower left cornerof the PGC.Thelayout for the 16-bit logarithmic adderis shown in Figure8(b).Thegatesin thelayoutconsistof transistorswith W/L

ratiosrangingfrom 2 to 5 for NMOS and3 to 7 for PMOS(however, mostareminimum size).The power rails of theadderare connectedto SPICEvoltagesourcesat the sixlabeledpoints, Va0 through Va5. Thesepoints are deter-minedby locating the intersectionof eachlabel placedinthe PGCwith the local VDD andGND rails of the adder.Therefore,it maybeconsideredacaseof partitioningusingthe FP-schemeasthe local rails areconsideredpart of theCLC. TheGND connectionpoints(notshown) areadjacentto the VDD connection points.

The six VDD input locationsin the PGC(Va0 throughVa5) werefoundto traverse4 differentiso-IRbands.There-fore, the computationof power grid responsefor a giveninput sequenceentails six convolution operationsusingfour IR functions.Figure9(a) shows the currenttransientsmeasuredat the six input locationsusing SPICEsimula-tions.The responseof the PGCat VDD0 obtainedby con-volving each of the current waveforms with theircorrespondingIR functions is shown in Figure 9(b). Theoverall responseof PGCto thesensitizedadderlogic mea-suredat VDD0 is obtainedby linear superpositionof itsresponseto individual currentsources.Figure10(a)showsthe overall responseof the PGC to the sensitizedadderlogic at VDD0 obtainedusing convolution basedmethodoverlaid with the responseobtainedusing SPICEsimula-

A a

nd B

inpu

ts

Va0 Va1 Va2

Va3 Va4 Va5

Sum

outputs

Adder Layout

(b)

VDD1

VDD0 VDD2

VDD3

(a)

Figure 8. (a) A 16-bit logarithmic adderconnected to the PGC. (b) Layout of the adder.

Adder

tions.

Thecomplexity involved in thecomputationof powergrid responsebasedon convolution operationscanbe fur-ther reducedby creatingpiece-wise-linear(PWL) abstrac-tions of the input currentwaveforms.An algorithmbasedon detectionof the changein polarity of slopein a wave-form is usedto derive it’s PWL abstraction.This signifi-cantly reducesthe numberof points in eachinput signalandthusthe numberof multiplication andadditionopera-tions. Figure10(b) shows the overall responseof the gridobtained using convolution based on PWL abstractedinputs. Overlaid with this curve is the SPICE generatedresponseobtained using original SPICE waveforms asinputs. The peak amplitude and width values obtainedusing SPICEand the percentagedifferenceerror as com-pared to the convolution results on original SPICE andPWL inputsarelistedin Table1. Thewidth of iDDT is mea-suredasthe time-interval betweenthe pointsat which thewaveform attains 5% of its peak value.

e � ���B#���2�����&?�5A����MfJ�HhgHNL3 "��'4�2����������The SPICEsimulationsof isolatedpathscanbe used

asa meansof enablingthesimulationof theCLC pathsto

Original i DDTs PWL fitted i DDTs

5% width (spice) = 3.26ns 5% width (spice) = 3.26ns

peak (spice) = 0.594 mA peak (spice) = 0.594 mA

% width error = 0.4% % width error = 3%

% peak error = 1.8% % peak error = 10%

Table 1: Amplitude and Peak Error.

Figure 9. (a) Adder iDDT waveforms that forminputs the PGC. (b) Response of the PGC to the

individual iDDTs in figure 9 (a).

Fri Sep 19 19:47:13 2003i

-38.7 -34.2 -29.7 -25.2 -20.7 -16.2 -11.7 -7.2 -2.7 1.8 6.2 10.7 15.2 19.7 24.2 28.7 33.2 37.7 42.2 46.7

-139.57

-105.15

-70.73

-36.31

-1.89

32.53

66.95

101.37

135.79

170.21

204.63

239.05

273.47

307.89

342.31

376.73

411.15

445.57

479.99

514.41

548.83

583.25

617.67

652.09

686.51

720.93

755.35

789.77

824.19

858.61

893.03

927.45

961.87

996.29

1030.71

1065.12

1099.54

1133.96

1168.38

1202.80

1237.22

Va0 Va1 Va2

Va3 Va4 Va5

Fri Sep 19 19:13:33 2003

-24.7 -21.9 -19.0 -16.2 -13.3 -10.5 -7.6 -4.8 -1.9 0.9 3.8 6.6 9.5 12.3 15.2 18.0 20.9 23.7 26.6 29.4-197.40

-44.30

108.80

261.90

415.00

568.10

721.20

874.30

1027.40

1180.50

1333.59

1486.69

1639.79

1792.89

1945.99

2099.09

2252.19

2405.29

2558.39

2711.48

2864.58

3017.68

3170.78

3323.88

3476.98

3630.08

3783.18

3936.28

4089.38

4242.47

4395.57

4548.67

4701.77

4854.87

5007.97

5161.07

5314.17

5467.27

5620.37

5773.46

5926.56

Va0 Va1 Va2

Va3 Va4 Va5

(b)(a)5

0.7

00

mA

ns

mA

0.7

0

0 1005 5

PGC response to iDDTs

5

0.5

00

mA

ns

mA

0.5

0

0 1005 5

Adder iDDTs

(b)(a)2

0

0 ns 1064 8

Convolution vs. SPICE

0.5

0.25

mA

2

0

0 ns 1064 8

Convolution using PWL Fits vs. SPICE

0.6

0.3

mA

SPICE

Convolution PWL

Figure 10. a) Overall response using SPICEsuperimposedwith convolution derivedresults.(b)Overall response using SPICE superimposed withconvolution derived results of PWL fits to iDDTs.

Convolution

SPICE

derive the currentinput waveformsthat feedthe PGC.Wecananalyzethe complexity involved in sucha schemebyassumingthe averagenumberof gatessensitizedunderagiven test sequence.If we assumethe maximum fanout(FO) of 4, logic depth(D) of 5 andmaximumfanin (FI) of3, the maximumnumberof sensitizedgatescan be com-putedusinggeometricprogressiongivenby Eq. 7. Assum-

ing that the minimum numberof gatessensitizedunderatest sequenceis 5 (30 transistors),the averagenumberoftransistorsper testsequenceis 1038.This shows a signifi-cantreductionin the numberof transistorsthat needto besimulatedunder a given test sequencecomparedto theentireCLC of the CUT. It mustbe realizedthat underanygiven testsequenceseveral pathsmay get sensitizedinde-pendently. All suchindependentlysensitizedpathscanbeisolatedandsimulatedin parallel and their resultscanbecombinedduring the PGCconvolution process.Insteadofusing SPICEto simulatethe isolatedpathswe may alsomake useof tools that performTransientCurrentSimula-tions at the switch level verilog netlist. We are currentlyinvestigating the accuracy and complexity of TransientCurrentSimulations.Also resultsfor pathsalreadysimu-latedwhenprocessinga previous input test vectorcanbereused for other test sequences.�?��� ��Hh�C����2���#%������#

This paperinvestigatesthepracticalissuesconcerningthe implementationof fault simulation methodologyforiDDT testing. A new model basedon convolution basedapproachis proposedthat can be used to compute thepower grid responseusing the precomputedimpulseresponse(IR) functions.Thiscircumventstheneedfor run-ning time and memory intensive transientsimulationsontheentireCUT. Thecategorizationof IR functionsinto iso-IR bandsis shown to furtherreducethenumberof convolu-tionsrequiredto computethetransientresponseof thegridto the maximum number of iso-IR bands.An approachbasedon isolation of sensitizedpathsfrom the layout isproposedas a meansof enablingthe simulation of corelogic circuit. The accuracy andcomplexity of thesemeth-odsareevaluatedon partof acommercialpower grid usinga 16-bit logarithmic adder as the core-logic.

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Max Numer of gatesFO

D1–

FO 1–---------------------- 341= =

Max Numer of transistors 2FI

FOD

1–

FO 1–----------------------⋅ 2046= =

PRQRSUjUS

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