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FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP User Group International, Inc. 1

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Page 1: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

FCBGA Package Warpage Definition Stage Project

Raiyo Aspandiar - IntelHDP User Group Member

MeetingHost: Oracle

Santa Clara, CA.

Feb. 26. 2013© HDP User Group International, Inc. 1

Page 2: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

© HDP User Group International, Inc. 2

Purpose

Page 3: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

© HDP User Group International, Inc. 3

Background

Package/board Warpage increasing trends •Driven by thinner package substrates and thinner die

 Package/Board contacts getting smaller and closer

thereby reducing ability to overcome increased Warpage. Solder Joint Quality Impact of increasing Package

and Warpage.

With advent of lead free soldering, the assembly temperatures have increased and the warpage impact has been exacerbated.

Page 4: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

© HDP User Group International, Inc. 4

Examples of Warpage Induced Defects for Area Array Solder Joints

Stretched joint

Head on pillow

Head-on-Pillow Open

Die

Board

Non –Wet Open

Various Solder Joint Defects can occur during SMT Reflow Soldering due to Excessive BGA component and/or Board Warpage

Page 5: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

• Real Time Videos will be shown for two cases– `Bad` Solder Paste causing Non-Wet Open Defects– `Good` Solder Paste resulting in acceptable solder joints

5

Real Time Videos of Solder Joint Formation

• Video Camera Set up

Malcolm TechVideo camera

Reflow Oven Belt or Rail

FCBGA Package

Solder BallsSolder Paste

Camera fixture

Page 6: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

6

© HDP User Group International, Inc. 6

1 2 3 4 5 6 7 8 9 10 Cooling

Real Time Videos of Solder Joint Formation

Time

Tem

pera

ture

Page 7: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

© HDP User Group International, Inc. 7

Two Real Time Videos of Solder Joint Formation of a FCBGA package with high dynamic warpage

will now be shown

Page 8: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

© HDP User Group International, Inc. 8

Project Scope

- What is IN the Scope

Die

Package Substrate

Printed Circuit Board

Project Focus Area

FC BGA Package Substrate

Solder Paste Rheology Wetting Metallurgy Activator chemistry Volume printed on land

Package Termination Geometry (ball, pillar, column, etc) Metallurgy (SAC, low Ag SAC, BiSnAg, other)

FCBGA Package just as its entering the SMT Reflow Oven

Reflow Process Temperature –Time Profile Oven Atmosphere

Surface Finish OSP/ENIG/

ImAg/ENEPIG/ etc

Page 9: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

© HDP User Group International, Inc. 9

Project Scope

Die

Package Substrate

Printed Circuit Board

FC BGA Package Substrate

Package Warpage Mitigation Laminate Type Stack-up Die Thickness Die Size

- What is OUT of the Scope

Package Warpage Measurement Metrologies Specifications

Board Warpage Mitigation Laminate Type Stack-up

Board Warpage Measurement Metrologies Specifications

Page 10: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Goal

10© HDP User Group International, Inc.

Establish a limit for dynamic package warpage

that can be mitigated during board assembly

without impacting solder joint quality

Page 11: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

11

Project Objectives

1. Identify mitigation paths for solder joint yield loss caused during the SMT reflow soldering process specifically due to the excessive warpage of package and/or boards

2. Evaluate these mitigation paths for their effectiveness in increasing solder joint yield despite high levels of package and/or board warpage

© HDP User Group International, Inc.

Page 12: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Technical Discussion

Potential Mitigation Paths

• Alternate solder paste and package solder ball metallurgies,

i.e., low temperature solders

• Alternate solder temp profiles (steep ramp, soak, spike reflow

profile, for instance)

• Alternate package termination geometries (instead of balls)

• Optimized solder paste printing geometries 

• New solder paste formulations

• Tacky Fluxes, applied by dipping  

Each mitigation path can comprise a separate project proposal or all can be combined into one project

12© HDP User Group International, Inc.

Page 13: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

What has been Done to Date

• Project Scope, Objectives, and Flow defined• Key Variables Identified to Control and Monitor during SMT Reflow

Solderingo Gap between Ball and Paste

• Selected the Metrologies to vary and monitor the gap between Ball and paste during the reflow soldering process Modified Plexus’ Method of Adhesive and Solder Pre-form under Package Cisco’s Rework Equipment Use Method Real Time observation of Solder Joint Formation using Malcom Tech Camera’s

and overs

Drafted Experimental Plans and Resources Needed for initial Objectives

Defined Test Substrate /Board Requirements© HDP User Group International, Inc. 13

19-21

22-29

34

30-33

Page 14: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

What is Planned For the Near Future

Develop Modified Cisco Rework Method Metrology: o Run the designed experiments to confirm the feasibility of using Hot Air Rework machine

to control the gap between solder ball and solder paste with temperature with a full array package instead of a single solder ball at a time

Develop Modified Plexus Cisco Rework Method Metrology: o Confirm proof of concept for using the expansion of a high CTE adhesive to vary ball-to-

paste gap in the pre-reflow zone of an in-line reflow soldering oveno Confirm proof of concept of solder preform wetting into multiple PTHs in the board for

sharply decreasing ball-to-molten paste gap in the reflow zone of an in-line reflow soldering oven

Develop Real Time Monitoring: o Confirm the capability for real time monitoring of ball-to-paste gap and solder joint

formation mechanisms of high dynamic warpage area array packages during the reflow process and of

1. the Malcom RCA-1 Observation Monitor Video Camera in an in-line reflow oven

2. the VDS-1 Video Monitoring System in a Reflow Simulator Batch Oven© HDP User Group International, Inc. 14

Page 15: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

What is Planned Beyond the Near Future

• Brainstorm Mitigation paths: for excessive warpage of package and/or boards induced SMT solder joint yield loss and select potential candidates for assessment

• Select Mitigation Path: Obtain Components and Design and Procure Boards for Evaluation of Mitigation Paths

• Assess Effectiveness of Mitigation Path: Design and Run Experiments to evaluate present capability of materials and processes and feasibility of the Warpage-induced Defects’ Mitigation Paths

© HDP User Group International, Inc. 15

Page 16: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

© HDP User Group International, Inc. 16

Proposed Project Flow

Page 17: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

© HDP User Group International, Inc. 17

Team Members –to date

•Akrometrix

•Alcatel-Lucent

•Arlon

•ASE

•Celestica

•Ciena

•Cisco

•Curtiss-Wright

•Emerson

•Ericsson

•Fiberhome

•Flextronics

•Fujitsu

•H3C

•Huawei

•Hitachi

•Hitachi-Chemical

•IBM

•Indium

•Intel

•IST Group

•Juniper

•Medtronic

•Multek

•Nihon-Superior

•Panasonic

•Phillips

•Plexus

•Rockwell

•Sytech

•TTM Tech

•Ventec

•Zestron

•ZTE

Page 18: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Back-up

© HDP User Group International, Inc. 18

Page 19: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Temp

Effect of Typical Dynamic Warpage Characteristics of FCBGA packages on Solder Joint Formation

© HDP User Group International, Inc.19

Head-on-Pillow Open

Room Temperature

`Flat Package` Point

Start of Significant Pull Way of Ball from Board

Maximum Ball-Board Separation Point

Post Solder Ball Collapse Point

Post Solidification Point

Time

Ramp

up

soak

reflowCool down

The typical Dynamic Warpage of a FCBGA package entails For a corner solder joint…….contact first, then separation between the solder ball and the solder paste For a center solder joint……separation first, then contact between the solder ball and the solder paste

This contact + separation or vice versa sequence creates solder joint defects

Page 20: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Variation of Gap between Bottom of Solder Ball and Top of Solder Paste (when solid or molten)

© HDP User Group International, Inc. 20

Time

`Flat Package` Point

Start of Significant Pull Away of Ball from Board

Temp Maximum Ball-Board Separation Point Post Solder Ball

Collapse Point

Post Solidification PointGap in Center

joint of Package

Gap in Corner Joint of Package

Gap

Room Temperature

Sharp Decrease in Gap due to collapse of central

solder joints

Besides first contact , then separation for the corner ball, there is a sharp decrease in the gap as the solder balls melt and collapse in the reflow zone within the reflow soldering oven

This sharp drop and gap can facilitate coalescence of the molten solder ball and molten solder paste if paste flux is still active

Page 21: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Key Points

Any method of simulating BGA package warpage during reflow soldering needs to address the following to simulate the conditions for corner solder joints

Initial Contact of the BGA solder ball with the solder paste and subsequent separation before or during the soak zone or ramp regionSharp drop in the gap between the molten solder ball and molten paste when the solder balls melt and collapse in the reflow zone region

Any method of simulating BGA package warpage during reflow soldering needs to address the following to simulate the conditions for central solder joints

No contact between the BGA solder ball and solder paste before or during the ramp zone or soak zone until the flat package point is reachedContact developed between the solder ball and solder paste later in the soak zone

© HDP User Group International, Inc. 21

Page 22: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Simulation for the Corner and Outer Row Solder Joints of the BGA

© HDP User Group International, Inc. 22

Requirements• Initial Contact of the BGA solder ball with the solder paste and subsequent separation before

or during the soak zone or ramp region• Sharp drop in the gap between the molten solder ball and molten paste when the solder balls

melt and collapse in the reflow zone region

Gap < 0

Package

Adhesive

Board

Gap > 0

Room Temp ~20C

Soak Zone Temp ~160C

Board

Board

Reflow Zone Temp ~240C Gap < 0

Initial set up entails amount (thickness) of adhesive adjusted to ensure negative

gap between the solder balls and the paste;

SAC Solder Pre-form and Solder Paste or Flux

Expansion of the adhesive in its thickness direction raised the balls from

the paste and creates a positive gap

Melting of solder preforms in the reflow zone and the subsequent flow of the

molten solder into PTH will dramatically drop the stand-off height of

the package and eliminate the gap

The amount of gap and rate at which it is created in the ramp zone of the profile is controlled by the expansion coefficient of the adhesive in its thickness direction

Page 23: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

One Proposal to Simulate Gap Variation between the BGA Solder Ball and the Solder Paste on the PCB Land

© HDP User Group International, Inc. 23

Gap > 0

Board

Adhesive

Solder Preform

BGA PackageBGA Solder Balls

Solder Paste

Function of Adhesive: To simulate the increase in the gap by changing its length with increasing temperature due to its coefficient of thermal expansion

Function of Solder Preform: To melt at reflow temperature and flow into the PTH it is placed over and simulate the sudden decrease in the gap that occurs when the balls collapse after becoming molten

Page 24: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Simulation for the Central Solder Joints of the BGA

Gap < 0

When the low temp solder pre-form melts balls lowered and touch SAC

solder paste

Balls and solder paste melt while in contact

Gap at RT > 0

Gap < 0

Package

Adhesive

Room Temp ~20C

Soak Zone Temp ~160C

Reflow Zone Temp ~240C

Low Temp Solder Pre-form and Solder Paste or Flux Initial set up entails a gap between the

solder balls and the paste; gap amount controlled by amount (thickness) of

adhesive

Requirements• No contact between the BGA solder ball and solder paste before or during the

ramp zone or soak zone until the flat package point is reached• Contact developed between the solder ball and solder paste later in the soak zone

The temperature at which the solder ball and paste make contact can be varied by using different solders with different melting points in the SAC profile soak zone

Page 25: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Requirements for Adhesive Under Component to Simulate the Gap between the Ball and the Paste during SMT Reflow

Soldering

© HDP User Group International, Inc. 25

Gap > 0

Board Expansion of the adhesive in its thickness direction raises the balls from

the paste and creates a positive gapMinimum Gap to simulate problematic

warpage is 150 microns

Adhesive

1) High Coefficient of Linear Expansion after Cure; 2) Sufficient Hardness/Modulus/Rigidity to push the package up

as the adhesive expands3) Survive temperatures up to 250C after cure4) Dispensable or screen printable

Key question: What is the range of Linear Expansion that is needed for the adhesive?

Page 26: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Cisco’s SRT Rework Equipment Method for Head-on-Pillow Testing

© HDP User Group International, Inc. 26

BGA rework equipment was also used to reflow the solder ball and the solder paste, while controlling the movement of the solder ball with respect to the solder paste on the pad.

The purpose of controlling the movement is to mimic the movement of the corner balls of a BGA as they warp during the reflow process.

Page 27: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Conditions for Cisco’s Method

© HDP User Group International, Inc. 27

C1

C2

C1: Initially there is no initial contact between the solder ball and the paste. Then at 200 ° C during the cooling down phase, the solder ball is pulled down slowly (1 mil/second) so that it makes contact with the solder paste.

C2: Initially there is no initial contact between the solder ball and paste. Then at 190 °C during the cooling down phase, the solder ball is pulled down slowly so that it makes contact with the solder paste. This condition is similar to C1 but there is less contact timebefore solidification.

Note: When initial contact is made between ball and paste, no H-o-P defects were formed

Page 28: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Photo’s of Cisco’s Method for Evaluating H-o-P defects

© HDP User Group International, Inc. 28

Before Solder Paste Reflow After Solder Paste Reflow

Aspects of Actual Reflow Soldering of high warpage BGAs NOT Simulated in this Test Lifting up of the solder ball from the solder paste during initial temperature

ramp (though this can be done with the equipment) Un-constrained Ball Collapse when the solder melts Temperature Profile simulated with hot air rework machine instead of a

reflow oven

Page 29: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Malcom RCA-1 Observation Monitor

© HDP User Group International, Inc. 29

Observes and Records the components on a PCB as it goes through the Reflow Oven

Page 30: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Summary of Obj # 3 Experimental Plans

© HDP User Group International, Inc. 30

Experiment Name Phase Description of Experiment

High CTE Adhesive Development

AFeasibility of ME-280+ silicone fillers adhesive Sample Preparation and its expansion effect on gap variation between BGA ball and PCB land through the reflow oven

B effect of adhesive volume on gap variation and package tilting during reflow soldering

C Explore other materials with higher CTE than that of ME-580+silicone fillers

Solder Preform Development

A Proof of Concept Validation using off-the-shelf preform

B Preform Design

C Plated Through Hole Design

D Preform Fabrication at Indium CorpE Board Fabrication at Member PCB Fabricator

Combined Adhesive and Solder Preform Validation A Using Developed Adhesive and solder preform with substrate

and boards, conduct test runs with printed solder paste

Page 31: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Summary of Obj # 3 Experimental Plans

© HDP User Group International, Inc. 31

Experiment Name Phase Description of Experiment

Development of Modified Cisco Hot Air Rework

Machine Method

A

Exploratory Experimental Runs to confirm the method worksComprehensive Factors DOE, using critical process variables from screening DOE results and including material Variables and ball pitch/ ball size to determine main effects and 2 factor interactions

B Screening DOE using Process Variables to determine main effects and 2 factor interactions

C Comprehensive Factors DOE, using critical process variables from screening DOE results and including material Variables and ball pitch/ ball size to determine main effects and 2 factor interactions

Page 32: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Resources Needed for Initial Objectives

© HDP User Group International, Inc. 32

Experiment Resources Potential Source

Modified Cisco Hot Air Rework Method

Test Substrate Laminate Panasonic

Fabrication of Test Substrate and Boards

Member PCB Fabricator, to be identified

Solder Balls Senju

Solder Paste Senju/Indium/Alpha/Shenmao

Stencils for solder printing Non-member Supplier

Running Experiments with Hot Air Rework Machine

Intel/Celestica/A.P.E

Failure Analysis including Dye and Pry

Intel / other members to be identified

High CTE material Lord Corp / Panasonic / Other yet to be identified

Solder Preforms Indium Corp

SMT Reflow Oven Flextronics / Intel

Designers for Solder Preform and Boards

Members, to be identified

Page 33: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Resources Needed for Initial Objectives

© HDP User Group International, Inc. 33

Experiment Resources Potential Source

Modified Plexus Method usign

High CTE Material and Solder

Preform

High CTE material Lord Corp / Panasonic / Other yet to be identified

Solder Preforms Indium Corp

SMT Reflow Oven Flextronics / Intel

Designers for Solder Preform and Boards

Members, to be identified

SMT Reflow Oven Flextronics / Intel / Other

Real Time Monitoring of Ball-to-Paste Gap

Camera for In-line Reflow Oven and In-line SMT Oven

Intel / Other Member(s) to be identified

Batch Reflow Oven with Video Camera

Nihon Superior / Other Member(s) to be identified

Page 34: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Test Substrates Proposal

• Thickness: 400 microns w/two copper layers, on each side of the core• Panasonic labs to build the substrate using low warpage materials• Substrate / Board Fabrication to be done at a PCB supplier member• Ball Attach to be done at Outside sub-contractor

Ball Pitch Ball Size Body SizeQuantity of Substrates

(Approx)

Quantity of Balls per Substrate

(Approx)

0.5 mm 0.3 mm 7 mm 150 600

0.8 mm 0.5 mm 15 mm 150 800

1.0 mm 0.6 mm 35 mm 300 1000

Page 35: FCBGA Package Warpage Definition Stage Project Raiyo Aspandiar - Intel HDP User Group Member Meeting Host: Oracle Santa Clara, CA. Feb. 26. 2013 © HDP

Proposed Schedule