FeinProbe® Solution for WLCSP Applications

Krzysztof Dabrowiecki

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Overview• Motivation• WLCSP Market Drivers• WLCSP Application Requirements• Stages of FeinProbe® Internal Qualification and Testing• Summary and Conclusion

K. Dabrowiecki

Motivation• Diversification of semiconductor products:

– Smartphones/Tablets– Internet of Things/Wearables– Virtual Reality– Artificial Intelligence– 5G Connectivity– Automotive and much more others like Medical, Industrial, Military…

• Increasing WLP (Fan-in and Fan-out) without substrates or interposer for IC chips

• Increasing final tests at wafer level

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WLCSP Market Drivers• Good electrical performance • Good thermal performance• Smaller and lower profile• High power• High system integration• High I/O density• Low cost

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General WLCSP Requirements

Low resistance for DC measurements High bandwidth for functional tests or AC

tests Low path inductance to reduce the noise

on the DUT power and ground at its switching frequency

High current capacity for power delivery and DC parametric tests

Kelvin probes for analog and mixed signal

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Electrical Mechanical High contact force Short probe length for electrical

parameters Large plunger compliance for

reliable contacts Longer lifetime Effective cleaning method

Die Size< 100 sq mm

Low I/O Count < 500 Pin Count

Bump Pitch> = 300 µm

No IC Underfill and no IC Substrate or Interposer

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Fan-out WLP Connection to PCB

IC Package Mold

Board

RDL Thin Film

Probe Card Technology for WLCSP Testing

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Contact Force Direction

Electrical Contact

Contact Force Direction

Contact Force Direction

Electrical Contacts

Electrical Contact

Cantilever Technology Buckling Beam/Hybrid BB Technology

Spring Probe Technology

FeinProbe® Spring Contact Advantage

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Stable and consistent contact resistance Self-aligning plunger tip High bandwidth High Current Carrying Capability (CCC) Large spring range force Large plunger tip compliant Low bump damage No probe coating required

Crown Plungers of FeinProbe® Head

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Stages of FeinProbe® Qualification and Testing

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Finite Element of Solder Bump-Crown Tip Plunger Model

Contact Force Test of Probe Head

Path Resistance on Bumped Wafer

Vector Network Analyzer Probe Test

Probe Current Carrying Capability Method

Why Finite Element Bump-Probe Contact Study?

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CSP with RDL:- 4 mask- 9 um UBM Cu/Ti

Low cost solution: - No RDL- 2 mask- 5 um UBM Au/Ni/Cu/Ti

Current WLCSP Technology Options

Source: C.Lee Amkor

Finite Element Probe-Bump Models

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FE model – Quarter

Lead-free bump diameter 142um

Crown plunger diameter 160um

Plunger force F=20gf

FE Model w/ 2 maskFE Model w/ 4 mask Boundary Conditions

Model Material Properties Table

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Model part MaterialYoung's

Modulus E (GPa)

Poisson's Ratio (-)

Yield Point (MPa)

CTE (ppm/C)

Crown plunger Pd alloy 110 0.35 930 11.7

Solder ball Sn/Ag 50 0.36 34.2 25Cu Cu 117 0.34 62 16.8PBO 1 PI 2.3 0.3 69 35PBO 2 PI 2.3 0.3 69 35Custom Passivation PI 3.5 0.35 69 35Silicon Si 131 0.26 UTS 7000 2.54Gold Au 79 0.4 205 14.2Nickel Ni 207 0.31 138 13.3Titanium Ti 116 0.32 379 8.5

Source: Amkor, NIST, STATS ChipPAC, Japan Institute of Metals

Model Stress Simulation

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FE Model w/ 2 maskFE Model w/ 4 mask

Stress Calculation in the UBM

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FE Model w/ 2 maskFE Model w/ 4 mask

High stresses at the bottom of UBM and on the edge

High stresses underneath of solder bump

Potential Bump Failures

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Crack from UBM edge UBM and RDL detachment

Source: Journal of Electronic Packaging, 2015

Silicon die

The failure causes are related to high range of temperature and possible high stress concentrations in the UBM

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Cont

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orce

[gf]

Over Drive [um]

Contact Force Test - Full Probe Head

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The contact force of test probe head measured by EAP500 system at RT

Individual pre-loaded spring probe

Average probe contact force installed in probe head

Plunger friction in the probe head

Path Resistance Test

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The bumped wafer SAC305: pitch 250um, bump size 142umThe test over drive 175um

Path Resistance Illustration

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Shorted Wafer

Probe Head

J750 Wired Connector

Signal PathReturn Path

Prober Head

The path contact resistance contains material resistivity of wafer, solder bump, probe, connector wire, PCB solder, PCB trace and prober head pogo, and contact resistances of probe to bump, probe to wired connector, pogo to PCB and pogo to probe head

Path Resistance and Life Test Charts

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At Varied Temperature and OD Life Test at 175um OD

Path resistance at 125C is slightly higher (0.2 Ohm) than at RT and -40C

Path resistance at 175um OD shows a quite uniform and consistent profile up to 500k TD’s

Wafer Bump Image at RT

50µmOver Drive 100µm 150µm 175µm

Wafer Bump Image at 125C

Wafer Bump Image at -40C

Wafer Bump Scrub Marks

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Vector Network Analyzer Test

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Test fixture with VNA cables

Configuration: G-S-GProbe pitch: 400um

ENA 5071C

SMA JACK, 50 Ohm, 27GHz

SMA JACK, 50 Ohm, 27GHz

Test FixtureGG S

Impedance and s-Parameters Measurements

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The impedance characteristic was obtained by applying a signal with rise time 50ps (20-80%)

S21- Insertion Loss: 9.3GHz @ -1dBS11 – Return Loss: 9.5 GHz @-10dB

Probe Current Carrying Capability - Method

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The standard procedure of International Sematech Manufacturing Initiative (ISMI 2009) describing the probe current carrying capability test methods has not mentioned anything about a method how to define the CCC for spring probe.

Therefore based on our internal empirical researches and tests, the maximum continuous current has been defined as a maximum tolerable probe warming temperature during the current lab test.In case of FeinProbe®, the temperature change of probes under the current has been defined for 20 degree (K) measured by thermocouples

Tp = K + TeTp – probe surface temperatureK – probe temperature change measured by thermocouples Te – environment temperature (RT)

Probe Current Measurement Cases

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1 - power supply 2 – digital voltmeter3 – thermocouple meter

Thermocouples touching the test probe

Thermocouples with distance to the test probe

4 - thermocouples 5 - spring probe6 - probe station

Schematic Diagram Description

Case 1 Case 2

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Tem

pera

ture

Cha

nge

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Current [A]

TC with Distance TC Touch

Probe Temperature Change Chart

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+20%

Probe Image in the Eye of Infrared Camera

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Probe current I=1.7A

Probe Surface Temp Measured by IC

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3.7A

3.4A

3.2A

2.6-2.8 A

2.2A

0.4 – 1.9ANo color change

No color change

Slightly color change

Color changes along entire barrel

Black color

Red color

Note: Probe surface observation during the current test with TC. Test time for each current cycle t=2 minutes

0102030405060708090

100110120130140150160170180

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Prob

e Su

rfac

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ratu

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Current [A]

FeinProbe® Current CC and Resistance Graphs

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Current [A]

Temperature change Resistance

Probe length L= 8.6mmContinuous CCC= 2.1 APath resistance = 70 mOhm

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Current [A]

Temperature change Resistance

Probe length L=3.2mmContinuous CCC= 2.8 APath resistance = 65 mOhm

Lowest Probe Resistance Area Lowest Probe Resistance Area

Summary and Conclusions

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- The advanced package technology exploring the 3D, complex and

high pin count of FOCSP requires a reliable test solution and the

presented five stages of qualification methodology can be a good

approach to guarantee an appropriate contact solution

- The thinner and smaller UBM may cause a cracking or

delamination issues of the under bump metallization during the

wafer test

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Summary and Conclusions

- The update of ISMI procedure is needed to standardize the CCC

measurement method for the spring probes. The presented

approach is a suggestion for an alternative method

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Follow-on Work

- Study of the low spring force probe

- Study of the spring probe at high temperature

Acknowledgments

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Thank You

I would like to thank colleagues at Feinmetall for their help in

preparation of this presentation. Many thanks to Jörg Behr,

Gunnar Volkmann and Jörg Burgold.