Feng-Xiang Huang

2011.03.02

Test Symposium(ETS),2010 15th IEEE EuropeanKo, Ho Fai; Nicolici, Nicola; Department of Electrical and Computer Engineering, McMaster University, Hamilton, ON L8S 4K1, Canada 

Combining Scan and Trace Buffers for Enhancing Real-time

Observability in Post-Silicon Debugging

Combining Scan and Trace Buffers for Enhancing Real-time

Observability in Post-Silicon Debugging

A Scan Cell Design for Scan-Based Debugging of

an SoC With Multiple Clock Domains

A Scan Cell Design for Scan-Based Debugging of

an SoC With Multiple Clock Domains

On-Chip SOC Test Platform Design Basedon IEEE 1500 Standard

On-Chip SOC Test Platform Design Basedon IEEE 1500 Standard

Scan is a known design-for-test technique in manufacturing test that has been successfully applied also to aid post-silicon debugging on testers. However, to achieve real-time observability in-field, embedded trace buffers are needed. In this paper, we discuss how in the presence of enhanced scan chains, trace buffers can be utilized efficiently for real-time debug data acquisition in-field.

Reusing scan chains

[4.8.10.20]

Reusing scan chains

[4.8.10.20]

Capacity of the on-chip trace

buffers[1.13.15.17.19]

Capacity of the on-chip trace

buffers[1.13.15.17.19]

Compressing the trace data

[2.3.6]

Compressing the trace data

[2.3.6]

Trace signal election

algorithm[16.21]

Trace signal election

algorithm[16.21]

Automated Data Analysis

Solutions[22]

Automated Data Analysis

Solutions[22]

Debug Approach Based on Suspect

Window[9]

Debug Approach Based on Suspect

Window[9]

Algorithms for state

Restoration[12]

Algorithms for state

Restoration[12]

Too Much Delay Fault Coverage Is a Bad Thing

[18]

Too Much Delay Fault Coverage Is a Bad Thing

[18]

Combining Scan and Trace….Combining Scan and Trace….

Post-silicon debugging The first phase

。Learn how to control the failure The second phase

。Space(identify the erroneous logic block) & Time(find the exact clock cycle)

。repeatable In controlled environments where patterns that are known to trigger

the failure will be applied under different operating conditions. The experiments are deterministic(repeatable)- Scan chains

。Non-repeatable There are still many sources of non-determinism in- field:

asynchronous interfaces, interrupts from peripherals.-embedded logic analysis0

A typical embedded logic analyzer Trigger unit-

。determine when data acquisition should be initiated

Sample unit –Trace buffer。As embedded memories。Issue

Capacity

Offload unit。Unload the data for further processing

Enhanced scan chains Additional state element- shadow flip-flop

。During real-time debugging, the state snapshot is offloaded into the shadow scan chain, without interrupting the execution.

Combination enhance scan chain & trace buffer. Such that the storage space for the trace buffer is

divided to sample data(trace signal) and scan data(scan chain)

Limited by the width of the trace buffer

Division of storage space for trace and scan. Insert multiplexers that be reconfigured at runtime to

collect different combinations of trace and scan data.

To address tradeoff Using the multiplexers which are controlled by a programmable

configuration register. How many signals should be traced? Vs. How much scan data

should be stored?

Computing the capacity of trace buffer(16*1024bits)

Scan dump frequency When the expiration time is programmed to be shorter

than the length of the shadow scan chains, some of the scan data will be lost.

Area investment Enhanced scan cells Multiplexers

The table contains data for when a 32 Kbits trace buffer.

When one performs more scan dumps with less number of scan cells, the amount of data available after state restoration actually decreased. This is because the scan cells that are discarded are chosen based on the restorability metric proposed in [12] Research or develop new metrics and algorithms.

。Which shadow scan cells should be the best candidates to be discarded?。For automated trace signal selection/

They proposed the flexibility architecture. Unlike the existing approaches that consider either scan

dumps or tracing a subset of internal signals in real-time in post-silicon debugging.

You can choose what type of data is acquired that ultimately make more efficient usage of the limited storage .

The Formula is not easily to understand. Need an example for demonstrate ?

Need a table of area investment. Scan data and trace data are dependent or not?