ff'scounter'sregistersequential2

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Introduction

Flip-fops are synchronous bistable devices. The term synchronous means the output changes stateonly when the clock input is triggered. That is, changes in the output occur in synchronization withthe clock.

Flip-fop is a kind o multivibrator. There are three types o multivibrators:

1. Monostable multivibrator (also called one-shot) has only one stable state. It produces a single pulse in response to atriggering input.

2. Bistable multivibrator exhibits two stable states. It is able to retain the two SE and !ESE states inde"initely. It iscommonly used as a basic building bloc# "or counters$ registers and memories.

3. %stable multivibrator has no stable state at all. It is used primarily as an oscillator to generate periodic pulse wave"orms"or timing purposes.

n this tutorial, the three basic categories o bistable elements are emphasized: edge-triggeredfip-fop, pulse-triggered !master-slave" fip-fop, and data lock-out fip-fop. Their operatingcharacteristics and basic applications will also be discussed.

Edge-Triggered Flip-fops

%n edge-triggered "lip-"lop changes states either at the positive edge (rising edge) or at the negative edge ("alling edge) o" the cloc#pulse on the control input. he three basic types are introduced here& S-!$ '- and .

Click on one the following types of flip-flop. Thenits logic symbol will be shown on the left. Notice thesmall triangle, called the dynamic input indicator , isused to identify an edge-triggered flip-flop.

#ositive edge-triggered !without bubble at $lockinput":%-&, '-( , and ) .

*egative edge-triggered !with bubble at $lockinput":%-&, '-( , and ) .

he S-!$ '- and inputs are called synchronous inputs because data on these inputs are trans"erred to the "lip-"lop*s output onlyon the triggering edge o" the cloc# pulse.+n the other hand$ the direct set (SE ) and clear (, !) inputs are called asynchronousinputs$ as they are inputs that a""ect the state o" the "lip-"lop independent o" the cloc#. or the synchronous operations to wor#properly$ these asynchronous inputs must both be #ept +/.

+dge-triggered %-& fip-fop

The basic operation is illustrated below, along with the truth table or this type o fip-fop. Theoperation and truth table or a negative edge-triggered fip-fop are the same as those or apositive e cept that the alling edge o the clock pulse is the triggering edge.

%s S 0 1$ ! 0 2. lip-"lop SE S on the rising cloc# edge.

3ote that the S and ! inputs can be changed at any time when the cloc# input is +/ or 4I54 (except "or a very short intervalaround the triggering transition o" the cloc#) without a""ecting the output. his is illustrated in the timing diagram below&

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+dge-triggered '-( fip-fop

he '- "lip-"lop wor#s very similar to S-! "lip-"lop. he only di""erence is that this "lip-"lop has 3+ invalid state. he outputstoggle (change to the opposite state) when both ' and inputs are 4I54. he truth table is shown below.

+dge-triggered ) fip-fop

he operations o" a "lip-"lop is much more simpler. It has only one input addition to the cloc#. It is very use"ul when a single databit (2 or 1) is to be stored. I" there is a 4I54 on the input when a cloc# pulse is applied$ the "lip-"lop SE s and stores a 1. I" thereis a +/ on the input when a cloc# pulse is applied$ the "lip-"lop !ESE s and stores a 2. he truth table below summari6e theoperations o" the positive edge-triggered "lip-"lop. %s be"ore$ the negative edge-triggered "lip-"lop wor#s the same except that the"alling edge o" the cloc# pulse is the triggering edge.

Pulse-Triggered (Master-Slave) Flip-fops

he term pulse-triggered means that data are entered into the "lip-"lop on the rising edge o" the cloc# pulse$ but the output does notre"lect the input state until the "alling edge o" the cloc# pulse. %s this #ind o" "lip-"lops are sensitive to any change o" the input levelsduring the cloc# pulse is still 4I54$ the inputs must be set up prior to the cloc# pulse*s rising edge and must not be changed be"orethe "alling edge. +therwise$ ambiguous results will happen.

he three basic types o" pulse-triggered "lip-"lops are S-!$ '- and . heir logic symbols are shown below. 3otice that they do not

have the dynamic input indicator at the cloc# input but have postponed output symbols at the outputs.


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Fre uency )ivision

/hen a pulse wave"orm is applied to the cloc# input o" a '- "lip-"lop that is connected to toggle$ the 9 output is a s7uare wave withhal" the "re7uency o" the cloc# input. I" more "lip-"lops are connected together as shown in the "igure below$ "urther division o" thecloc# "re7uency can be achieved.

he 9 output o" the second "lip-"lop is one-"ourth the "re7uency o" the original cloc# input. his is because the "re7uency o" thecloc# is divided by : by the "irst "lip-"lop$ then divided by : again by the second "lip-"lop. I" more "lip-"lops are connected this way$the "re7uency division would be : to the power n$ where n is the number o" " lip-"lops.

#arallel )ata %torage

In digital systems$ data are normally stored in groups o" bits that represent numbers$ codes$ or other in"ormation. So$ it is commonto ta#e several bits o" data on parallel lines and store them simultaneously in a group o" "lip-"lops. his operation is illustrated in the"igure below.

Each o" the three parallel data lines is connected to the input o" a "lip-"lop. Since all the cloc# inputs areconnected to the same cloc#$ the data on the inputs are stored simultaneously by the "lip-"lops on thepositive edge o" the cloc#. !egisters$ a group o" "lip-"lops use "or data storage$ will be explained in moredetail in a later chapter.

$ounting


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%nother very important application o" "lip-"lops is in digital counters$ which arecovered in detail in the next chapter.

4 counter that counts rom 5 to 6 is illustrated in the timingdiagram on the right. The two-bit binary se uence repeatsevery our clock pulses. 1hen it counts to 6, it recycles back

to 5 to begin the se uence again.

Ta#le o$ ontents

ntroduction

4synchronous !&ipple" $ounters

4synchronous )ecade $ounters

4synchronous p-)own $ounters

%ynchronous $ounters

%ynchronous )ecade $ounters

%ynchronous p-)own $ounters

4pplications

Introduction

$ircuits or counting events are re uently used in computers and other digital systems. %ince acounter circuit must remember its past states, it has to possess memory. The chapter about fip-fops introduced how fip-fops are connected to make a counter. The number o fip-fops used andhow they are connected determine the number o states and the se uence o the states that thecounter goes through in each complete cycle.

ounters can be classi2ed into two broad categories according to the way they are clocked:

1. 4synchronous !&ipple" $ounters - the 2rst fip-fop is clocked by the e ternal clock pulse,and then each successive fip-fop is clocked by the 7 or 78 output o the previous fip-fop.

2. %ynchronous $ounters - all memory elements are simultaneously triggered by the sameclock.

n this tutorial, pure binary, decade and up-down counters within the two categories will beintroduced.

"s%nc!ronous(&ipple) ounters

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% two-bit asynchronous counter is shown on the le"t. he external cloc# isconnected to the cloc# input o" the "irst "lip-"lop ( 2) only. So$ 2 changes stateat the "alling edge o" each cloc# pulse$ but 1 changes only when triggered by

the "alling edge o" the 9 output o" 2. Because o" the inherent propagationdelay through a "lip-"lop$ the transition o" the input cloc# pulse and a transition o" the 9 output o" 2 can never occur at exactly the same time. here"ore$ the "lip-"lops cannot be triggered simultaneously$ producing an asynchronous operation.

3ote that "or simplicity$ the transitions o" 92$ 91 and , in the timing diagram above are shown as simultaneous even though this

is an asynchronous counter. %ctually$ there is some small delay between the , $ 92 and 91 transitions.

sually, all the $3+4& inputs are connected together, so that a single pulse can clear all the fip-fops be ore counting starts. The clock pulse ed into FF5 is rippled through the other countersa ter propagation delays, like a ripple on water, hence the name &ipple $ounter.

The 9-bit ripple counter circuit above has our di erent states, each one corresponding to a countvalue. %imilarly, a counter with n fip-fops can have ' to t!e po er n states. The number o statesin a counter is known as its mod !modulo" number. Thus a 9-bit counter is a mod-; counter.

4 mod-n counter may also described as a divide-by- n counter. This is because the most signi2cantfip-fop !the urthest fip-fop rom the original clock pulse" produces one pulse or every n pulsesat the clock input o the least signi2cant fip-fop !the one triggers by the clock pulse". Thus, theabove counter is an e ample o a divide-by-; counter.

The ollowing is a three-bit asynchronous binary counter and its timing diagram or one cycle. tworks e actly the same way as a two-bit asynchronous binary counter mentioned above, e cept ithas eight states due to the third fip-fop.


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"s%nc!ronousDecade ounters

he binary counters previously introduced have two to the power n states. But counters with states less than this number are alsopossible. hey are designed to have the number o" states in their se7uences$ which are called truncated se7uences. hese se7uencesare achieved by "orcing the counter to recycle be"ore going through all o" its normal states.

4 common modulus or counters with truncated se uences is ten. 4 counter with ten states in itsse uence is called a decade counter . The circuit below is an implementation o a decade counter.

+nce the counter counts to ten (1212)$ all the "lip-"lops are being cleared. 3otice that only 91 and 9; are used to decode the count o" ten. his is called partial decoding$ as none o" the other states (6ero to nine) have both 91 and 9; 4I54 at the same time.

The se uence o the decade counter is shown in the table below:

"s%nc!ronousp-Do n ounters

In certain applications a counter must be able to count both up and down. he circuit below is a ;-bit up-down counter. It countsup or down depending on the status o" the control signals


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3otice that an asynchronous up-down counter is slower than an up counter or a down counter because o"the additional propagation delay introduced by the 3%3 networ#s.

S%nc!ronous ounters

In synchronous counters $ the cloc# inputs o" all the "lip-"lops are connected together and are triggered by the input pulses. hus$ allthe "lip-"lops change state simultaneously (in parallel). he circuit below is a ;-bit synchronous counter. he ' and inputs o" 2are connected to 4I54. 1 has its ' and inputs connected to the output o" 2$ and the ' and inputs o" : are connected tothe output o" an %3 gate that is "ed by the outputs o" 2 and 1.

#ay attention to what happens a ter the 6rd clock pulse. >oth outputs o FF5 and FF= are / ?/. The positive edge o the ;th clock pulse will cause FF9 to change its state due to the 4*) gate.

he count se7uence "or the ;-bit counter is shown on the right.

The most important advantage o synchronous counters is that there is no cumulative

time delay because all fip-fops are triggered in parallel. Thus, the ma imum operatingre uency or this counter will be signi2cantly higher than or the corresponding ripplecounter.

S%nc!ronousDecade ounters

Similar to an asynchronous decade counter$ a synchronous decade counter counts "rom 2 to = and then recycles to 2 again. his isdone by "orcing the 1212 state bac# to the 2222 state. his so called truncated se7uence can be constructed by the "ollowing circuit.


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rom the se7uence on the le"t$ we notice that& • 92 toggles on each cloc# pulse .

• 91 changes on the next cloc# pulse each time 9201 and 9;02 .

• 9: changes on the next cloc# pulse each time 9209101 .

• 9; changes on the next cloc# pulse each time 9201$ 9101 and 9:01 (count >)$or when 9201 and 9;01 (count =) .

hese characteristics are implemented with the %3 ?+! logic connected as shown in the logic diagram above.

S%nc!ronousp-Do n ounters

% circuit o" a ;-bit synchronous up-down counter and a table o" its se7uence are shown below. Similar to an asynchronous up-downcounter$ a synchronous up-down counter also has an up-down control input. It is used to control the direction o" the counter througha certain se7uence.

%n examination o" the se7uence table shows& • "or both the


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igital counters are very use"ul in many applications. hey can be easily "ound in digital cloc#s and parallel-to-serial dataconversion (multiplexing). In this section$ we will use the later as an example on how counters are being used.

4 group o bits appearing simultaneously on parallel lines is called parallel data. 4 group o bitsappearing on a single line in a time se uence is called serial data. #arallel-to-serial conversion isnormally accomplished by the use o a counter to provide a binary se uence or the data-selectinputs o a multiple er, as illustrated in the circuit below.

he 9 outputs o" the modulus-A counter are connected to the data-select inputs o"an eight-bit multiplexer. he "irst byte (eight-bit group) o" parallel data is appliedto the multiplexer inputs. %s the counter goes through a binary se7uence "rom 2 to>$ each bit beginning with 2$ is se7uentially selected and passed through themultiplexer to the output line.

%"ter eight cloc# pulses$ the data byte has been converted to a serial "ormat andsent out on the transmission line. hen$ the counter recycles bac# to 2 and convertsanother parallel byte se7uentially again by the same process.

Ta#le o$ ontents

ntroduction

%erial n - %erial


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"lip-"lop on the le"t ( 2). uring each cloc# pulse$ one bit is transmitted "rom le"t to right. %ssume a data word to be 1221. heleast signi"icant bit o" the data has to be shi"ted through the register "rom 2 to ;.

n order to get the data out o the register, they must be shi ted out serially. This can be donedestructively or non-destructively. For destructive readout, the original data is lost and at the endo the read cycle, all fip-fops are reset to zero.

o avoid the loss o" data$ an arrangement "or a non-destructive reading can be done by adding two %3 gates$ an +! gate and aninverter to the system. he construction o" this circuit is shown below.

he data is loaded to the register when the control line is 4I54 (ie /!I E). he data can be shi"ted out o" the register when thecontrol line is +/ (ie !E% ). his is shown in the animation below.

Serial In - Parallel Out S!i$t &egisters

or this #ind o" register$ data bits are entered serially in the same manner as discussed in the last section. he di""erence is the wayin which the data bits are ta#en out o" the register. +nce the data are stored$ each bit appears on its respective output line$ and allbits are available simultaneously. % construction o" a "our-bit serial in - parallel out register is shown below.

In the animation below$ we can see how the "our-bit binary number 1221 is shi"ted to the 9 outputs o" the register.


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Parallel In - Serial Out S!i$t &egisters

% "our-bit parallel in - serial out shi"t register is shown below. he circuit uses "lip-"lops and 3%3 gates "or entering data (iewriting) to the register.

2$ 1$ : and ; are the parallel inputs$ where 2 is the most signi"icant bit and ; is the least signi"icant bit. o write data in$the mode control line is ta#en to +/ and the data is cloc#ed in. he data can be shi"ted when the mode control line is 4I54 asS4I is active high. he register per"orms right shi"t operation on the application o" a cloc# pulse$ as shown in the animationbelow.

Parallel In - Parallel Out S!i$t &egisters

or parallel in - parallel out shi"t registers$ all data bits appear on the parallel outputs immediately "ollowing the simultaneous entryo" the data bits. he "ollowing circuit is a "our-bit parallel in - parallel out shi"t register constructed by "lip-"lops.

The )8s are the parallel inputs and the 78s are the parallel outputs.


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he registers discussed so "ar involved only right shi"t operations. Each right shi"t operation has the e""ect o" successively dividingthe binary number by two. I" the operation is reversed (le"t shi"t)$ this has the e""ect o" multiplying the number by two. /ithsuitable gating arrangement a serial shi"t register can per"orm both operations.

4 #idirectional , or reversi#le , shi t register is one in which the data can be shi t either le t or right. 4 our-bit bidirectional shi t register using ) fip-fops is shown below.

/ere a set o *4*) gates are con2gured as


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'ohnson $ounters

'ohnson counters are a variation o" standard ring counters$ with the invertedoutput o" the last stage "ed bac# to the input o" the "irst stage. hey are also#nown as twisted ring counters. %n n-stage 'ohnson counter yields a count

se7uence o" length 2n $ so it may be considered to be a mod- 2n counter. hecircuit above shows a -bit 'ohnson counter. he state se7uence "or the counteris given in the table as well as the animation on the le"t.

4gain, the apparent disadvantage o this counter is that the ma imum available states are not ullyutilized. eware that or both the &ing and the 'ohnson counter must initially be orced into a valid state inthe count se uence because they operate on a subset o the available number o states.


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'ohnson $ounters

'ohnson counters are a variation o" standard ring counters$ with the invertedoutput o" the last stage "ed bac# to the input o" the "irst stage. hey are also#nown as twisted ring counters. %n n-stage 'ohnson counter yields a count

se7uence o" length 2n $ so it may be considered to be a mod- 2n counter. hecircuit above shows a -bit 'ohnson counter. he state se7uence "or the counteris given in the table as well as the animation on the le"t.

4gain, the apparent disadvantage o this counter is that the ma imum available states are not ullyutilized. eware that or both the &ing and the 'ohnson counter must initially be orced into a valid state inthe count se uence because they operate on a subset o the available number o states.


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Figure 1. Block Diagram of Sequential Circuit.

The diagram consists of combinational circuit to which memory elements are connected to form a feedback path. The memory elements are devicescapable of storing binary information within them. The combinational part of the circuit receives two sets of input signals! one is primary "coming from

the circuit environment# and secondary "coming from memory elements#. The particular combination of secondary input variables at a given time iscalled the present state of the circuit. The secondary input variables are also know as the state variables .

The block diagram shows that the e$ternal outputs in a sequential circuit are a function not only of e$ternal inputs but also of the present state of thememory elements. The ne$t state of the memory elements is also a function of e$ternal inputs and the present state. Thus a sequential circuit isspecified by a time sequence of inputs, outputs, and internal states.

%ynchronous and 4synchronous


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logic gates. Thus, asynchronous sequential circuits may be regarded as combinational circuits with feedback. )ecause of the feedback among logicgates, asynchronous sequential circuits may, at times, become unstable due to transient conditions. The instability problem imposes many difficultieson the designer. -ence, they are not as commonly used as synchronous systems.

%ummary o the Types o Flip-fop >ehaviour

%ince memory elements in sequential circuits are usually flip&flops, it is worth summarising the behaviour of various flip&flop types before proceedingfurther.

All flip&flops can be divided into four basic types! SR , JK , D and T. They differ in the number of inputs and in the response invoked by different value ofinput signals. The four types of flip&flops are defined in Table .

Table =. Flip-fop Types

!"#- !$# N%&' !"# - !$# ()&*$! C+% %CT' "(T"C T%*!'

C+% %CT' "(T"C' %T"$N '/C"T%T"$N T%*!'

S!

S ! 9(next)

0 0

0 1 0

1 0 1

1 1

9(next) 0 S !*9

%& C 5

9 9(next) S !

0 0 0 /

0 1 1 0

1 0 0 1

1 1 / 0

'

' 9(next)

0 0

0 1 0

1 0 1

1 1

9(next) 0 '9* *9

9 9(next) '

0 0 0 /

0 1 1 /

1 0 / 1

1 1 / 0

9(next)

0 0

1 1

9(next) 0

9 9(next)

0 0 0

0 1 1

1 0 0

1 1 1

9(next)

0

1

9(next) 0 9* *9

9 9(next)

0 0 0

0 1 1

1 0 1

1 1 0

ach of these flip&flops can be uniquely described by its graphical symbol, its characteristic table, its characteristic equation or e$citation table. All flip&flops have output signals / and /*.

The characteristic table in the third column of Table defines the state of each flip&flop as a function of its inputs and previous state. Q refers to thepresent state and Q ne!t" refers to the ne$t state after the occurrence of the clock pulse. The characteristic table for the 0% flip&flop shows that thene$t state is equal to the present state when both inputs % and 0 are equal to (. 1hen 02 , the ne$t clock pulse clears the flip&flop. 1hen %2 , the flip&flop output / is set to . The equation mark "3# for the ne$t state when % and 0 are both equal to designates an indeterminate ne$t state.

The characteristic table for the 45 flip&flop is the same as that of the 0% when 4 and 5 are replaced by % and 0 respectively, e$cept for theindeterminate case. 1hen both 4 and 5 are equal to , the ne$t state is equal to the complement of the present state, that is, /"ne$t# 2 /*.

The ne$t state of the 6 flip&flop is completely dependent on the input 6 and independent of the present state.

The ne$t state for the T flip&flop is the same as the present state / if T2( and complemented if T2 .

The characteristic table is useful during the analysis of sequential circuits when the value of flip&flop inputs are known and we want to find the value ofthe flip&flop output / after the rising edge of the clock signal. As with any other truth table, we can use the map method to derive the characteristicequation for each flip&flop, which are shown in the third column of Table .

6uring the design process we usually know the transition from present state to the ne$t state and wish to find the flip&flop input conditions that willcause the required transition. For this reason we will need a table that lists the required inputs for a given change of state. %uch a list is called theexcitation table , which is shown in the fourth column of Table . There are four possible transitions from present state to the ne$t state. The required


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input conditions are derived from the information available in the characteristic table. The symbol 7 in the table represents a 8don*t care8 condition, thatis, it does not matter whether the input is or (.

%tate Tables and %tate )iagrams

1e have e$amined a general model for sequential circuits. In this model the effect of all previous inputs on the outputs is represented by a state of thecircuit. Thus, the output of the circuit at any time depends upon its current state and the input. These also determine the ne$t state of the circuit. Therelationship that e$ists among the inputs, outputs, present states and ne$t states can be specified by either the state table or the state diagram .

%tate Table

The state table representation of a sequential circuit consists of three sections labelled present state , next state and output . The present statedesignates the state of flip&flops before the occurrence of a clock pulse. The ne$t state shows the states of flip&flops after the clock pulse, and theoutput section lists the value of the output variables during the present state.

%tate )iagram

In addition to graphical symbols, tables or equations, flip&flops can also be represented graphically by a state diagram. In this diagram, a state isrepresented by a circle, and the transition between states is indicated by directed lines "or arcs# connecting the circles. An e$ample of a state diagramis shown in Figure 9 below.

Figure3. StateDiagra

m

The binary number inside each circle identifies the state the circle represents. The directed lines are labelled with two binary numbers separated by aslash ":#. The input value that causes the state transition is labelled first. The number after the slash symbol : gives the value of the output. Fore$ample, the directed line from state (( to ( is labelled :(, meaning that, if the sequential circuit is in a present state and the input is , then the ne$tstate is ( and the output is (. If it is in a present state (( and the input is (, it will remain in that state. A directed line connecting a circle with itselfindicates that no change of state occurs. The state diagram provides e$actly the same information as the state table and is obtained directly from thestate table.

+ ample : This example is taken from . !. "ala# Practical Digital Logic Design and Testing # rentice $all# 1%% p.1''.

Consider a sequential circuit shown in Figure ;. It has one input $, one output < and two state variables / /' "thus having four possible present states((, ( , (, #.


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Figure (. )Sequential

Circuit

The behaviour of the circuit is determined by the following )oolean e$pressions!

F 0 xG91 1 0 x* 91 : 0 xG9:* x*G91*

These equations can be used to form the state table. %uppose the present state "i.e. / /'# 2 (( and input $ 2 (. =nder these conditions, we get < 2 (,6 2 , and 6' 2 . Thus the ne$t state of the circuit 6 6' 2 , and this will be the present state after the clock pulse has been applied. The output ofthe circuit corresponding to the present state / /' 2 (( and $ 2 is < 2 (. This data is entered into the state table as shown in Table '.

#resent (tate

*1*2

Ne t (tate 4 0 4 1

$utput 4 0 4 1

0 00 11 01 1

1 1 0 11 1 0 01 0 1 11 0 1 0

0 00 00 10 1

Ta+le 2. State ta+le for the sequential circuit in Figure (.

The state diagram for the sequential circuit in Figure ; is shown in Figure >.

Figure '.StateDiagramof circuitin Figure(.


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%tate )iagrams o Darious Flip-fops

Table 9 shows the state diagrams of the four types of f lip&flops.

,)- ST)T D/)0 )-

%&

'(

)

T

Ta+le 3. State iagrams of the four t pes of 4ip54ops.

?ou can see from the table that all f our flip&flops have the same number of states and transitions. ach flip&flop is in the set state when /2 and in thereset state when /2(. Also, each flip&flop can move from one state to another, or it can re&enter the same state. The only difference between the fourtypes lies in the values of input signals that cause these transitions.

A state diagram is a very convenient way to visualise the operation of a flip&flop or even of large sequential components.

4nalysis o %e uential $ircuits

The behaviour of a sequential circuit is determined from the inputs, the outputs and the states of its flip&flops. )oth the output and the ne$t state are afunction of the inputs and the present state.

The suggested analysis procedure of a sequential circuit is set out in Figure @ below.


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1e start with the logic schematic fromwhich we can derive e$citation equationsfor each flip&flop input. Then, to obtain

ne$t&state equations, we insert thee$citation equations into the characteristicequations. The output equations can bederived from the schematic, and once wehave our output and ne$t&state equations,we can generate the ne$t&state and outputtables as well as state diagrams. 1hen wereach this stage, we use either the table orthe state diagram to develop a timingdiagram which can be verified throughsimulation.

Figure &. )nal sis proce ure of sequential circuits.

ow let*s look at some e$amples, using these procedures to analyse a sequential circuit.

)esign o %e uential $ircuits

The design of a synchronous sequential circuit starts from a set of specifications and culminates in a logic diagram or a list of )oolean functions fromwhich a logic diagram can be obtained. In contrast to a combinational logic, which is fully specified by a truth table, a sequential circuit requires a statetable for its specification. The first step in the design of sequential circuits is to obtain a state table or an equivalence representation, such as a statediagram.

A synchronous sequential circuit is made up of flip&flops and combinational gates. The design of the circuit consists of choosing the flip&flops and thenfinding the combinational structure which, together with the flip&flops, produces a circuit that fulfils the required specifications. The number of flip&flops isdetermined from the number of states needed in the circuit.

The recommended steps for the design of sequential circuits are set out below.


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For information on state reduction .


This example is taken from -. -. -ano# Digital Design # rentice $all# 1%6(# p.23'.

+ ample =.6 1e wish to design a synchronous sequential circuit whose state diagram is shown in Figure 9. The type of flip&flop to be use is 4&5.

http://loadsession%28%27st-red.htm%27%29/http://loadsession%28%27st-red.htm%27%29/http://loadsession%28%27st-red.htm%27%29/


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igure 13. (tatediagram

From the state diagram, we can generate the state table shown in Table B. ote that there is no output section for this circuit. Two flip&flops are neededto represent the four states and are designated /(/ . The input variable is labelled $.

#resent (tate

*7 *1

Ne t (tate 4 0 4 1

0 00 11 0

1 1

0 0 0 11 0 0 11 0 1 1

1 1 0 0

Ta+le %. State ta+le.

1e shall now derive the e$citation table and the combinational structure. The table is now arranged in a different form shown in Table , where thepresent state and input variables are arranged in the form of a truth table. 0emember, the e$citable for the 45 flip&flop was derive in Table .

Ta+le 17. xcitation ta+le for 8! 4ip54op

$utput Transitions

* *9next

lip-flop inputs

8 !

0 00 11 0

1 1

0 /1 // 1/ 0

Ta+le 11. xcitation ta+le of the circuit

#resent (tate

*7 *1

Ne t (tate

*7 *1

"nput

x

lip-flop "nputs5060 5161

0 00 00 10 11 01 01 11 1

0 00 11 00 11 01 11 10 0

01010101

0 / 0 /0 / 1 /1 / / 10 / / 0/ 0 0 // 0 1 // 0 / 0/ 1 / 1

In the first row of Table , we have a transition for flip&flop /( from ( in the present state to ( in the ne$t state. In Table ( we find that a transition ofstates from ( to ( requires that input 4 2 ( and input 5 2 7. %o ( and 7 are copied in the first row under 4( and 5( respectively. %ince the first row alsoshows a transition for the flip&flop / from ( in the present state to ( in the ne$t state, ( and 7 are copied in the first row under 4 and 5 . This processis continued for each row of the table and for each flip&flop, with the input conditions as specified in Table (.

The simplified )oolean functions for the combinational circuit can now be derived. The input variables are /(, / , and $ the output are the variables4(, 5(, 4 and 5 . The information from the truth table is plotted on the 5arnaugh maps shown in Figure ;.

http://www.eelab.su.oz.au/digital_tutorial/part3/fl-type.htmhttp://www.eelab.su.oz.au/digital_tutorial/part3/fl-type.htm


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Figure 1(. !arnaugh -aps

The flip&flop input functions are derived!

'2 0 91Gx* 2 0 91Gx'1 0 x 1 0 92*Gx* 92Gx 0 92 x

,ote: the s m+ol is exclusi;e5,< .

The logic diagram is drawn in Figure >.

Figure 1'. "ogiciagram of the

sequential circuit


This example is taken from . !. "ala# Practical Digital Logic Design and Testing # rentice $all# 1%% p.1=&.

+ ample =.; 6esign a sequential circuit whose state tables are specified in Table ', using 6 f lip&flops.

Ta+le 12. State ta+le of a sequential circuit.

#resent (tate

*7 *1

Ne t (tate

x > 7 x > 1

$utput

x > 7 x > 1

0 00 11 01 1

0 0 0 10 0 1 01 1 1 00 0 0 1

0 00 00 00 1

Ta+le 13. xcitation ta+le for a D 4ip54op.

$utput Transitions

* *9next

lip-flop inputs

D


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0 00 11 01 1

0

1

0

1

e$t step is to derive the e$citation table for the design circuit, which is shown in Table ;. The output of the circuit is labelled


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Figure 1=. "ogic iagram of the sequential circuit.


This example is taken from . !. "ala# Practical Digital Logic Design and Testing # rentice $all# 1%% p.1=&.

+ ample =.; 6esign a sequential circuit whose state tables are specified in Table ', using 6 f lip&flops.

Ta+le 12. State ta+le of a sequential circuit.

#resent (tate

*7 *1

Ne t (tate

x > 7 x > 1

$utput

x > 7 x > 1

0 00 11 01 1

0 0 0 10 0 1 01 1 1 00 0 0 1

0 00 00 00 1

Ta+le 13. xcitation ta+le for a D 4ip54op.

$utput Transitions

* *9next

lip-flop inputs

D

0 00 11 01 1

0

1

0

1

e$t step is to derive the e$citation table for the design circuit, which is shown in Table ;. The output of the circuit is labelled


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igure 17. (tate diagram of a3-bit binary counter.

The circuit has no inputs other than the clock pulse and no outputs other than its internal state "outputs are taken off each flip&flop in the counter#. Thene$t state of the counter depends entirely on its present state, and the state transition occurs every time the clock pulse occurs. Figure B shows thesequences of count after each clock pulse.

+nce the sequential circuit is defined by the state diagram, the ne$t step is to obtain the ne$t&state table, which is derived from the state diagram inFigure and is shown in Table >.

Ta+le 1'. State ta+le

#resent (tate

*2 *1 *7

Ne t (tate

*2 *1 *7

0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1

0 0 10 1 00 1 11 0 01 0 11 1 01 1 10 0 0

%ince there are eight states, the number of f lip&flops required would be three. ow we want to implement the counter design using 45 flip&flops.


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e$t step is to develop an e$citation table from the state table, which is shown in Table @.

Ta+le 1&. xcitation ta+le


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igure 21. !ogicdiagram of a 3-

bit binarycounter.

)esign o $ounters

This example is taken from -. -. -ano# Digital Design # rentice $all# 1%6(# p.2(3.

+ ample =. 6esign a counter specified by the state diagram in $ample .> using T flip&flops. The state diagram is shown here again in Figure''.

igure 22. (tate diagram of a3-bit binary counter.

The state table will be the same as in $ample .>.

ow derive the e$citation table from the state table, which is shown in Table D.

Ta+le 1=. xcitation ta+le.


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igure 23.6arnaughmaps

The following e$pressions are obtained!

T5 C =G T= C 75G T9 C 7=H75

Finally, draw the logic diagram of the circuit from the e$pressions obtained. The complete logic diagram of the counter is shown in Figure ';.

igure 28. !ogic diagram of 3-bit binary counter.

To see the timing and state transitions of the counter, click on this image.
http://loadsession%28%27cnt-animate.htm%27%29/

ff'scounter'sregistersequential2

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