field programmable gate array - university of the...
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![Page 1: Field Programmable Gate Array - University of the Ryukyusie.u-ryukyu.ac.jp/~wada/system06/SYSARC2006-8(FPGA).pdf · Field Programmable Gate Array. ... Multiplier (18b x 18b) ... Altera’s](https://reader034.vdocument.in/reader034/viewer/2022042111/5e8bdef050b49b64b0055592/html5/thumbnails/1.jpg)
System Arch 2006 (Fire Tom Wada) 1HO#8 2006/June/16
Field Programmable Gate Array
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System Arch 2006 (Fire Tom Wada) 2HO#8 2006/June/16
What is FPGA?
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System Arch 2006 (Fire Tom Wada) 3HO#8 2006/June/16
FPGAProgrammable (= reconfigurable) Digital SystemComponent
Basic componentsCombinational logicsFlip Flops
Macro componentsMultiplier ( large combinational logic)Random Access Memory (Large Density)Read Only memory (Large Density)CPU
Programmable InterconnectionProgrammable Input/Output circuitProgrammable Clock Generator
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System Arch 2006 (Fire Tom Wada) 4HO#8 2006/June/16
What is Combinational Logic?
CLABCD
f
g
A, B, C, D, f, g are all binary signal.
If output f, g are function of only inputs (A, B, C, D) then the circuit is combinational circuit.In another word, output signal is determined by only the combination of input signals.
f = func1(A, B, C, D)g = func2(A, B, C, D)
Combinational logic does NOT include memories such as Flip-Flops.Combinational logic can be constructed by just primitive gates such as NOT, NAND, NOR, etc. (But no feedback loop)
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System Arch 2006 (Fire Tom Wada) 5HO#8 2006/June/16
Combinational Logic realization - gates -
There is no signal loop in the circuit.In combinational logic, signal loop is prohibited since the loop makes states (Memory).Function is not configurable.
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System Arch 2006 (Fire Tom Wada) 6HO#8 2006/June/16
Combinational Logic realization - Table -
TRUTH TABLE
1111
1011
0101
0001
0110
0010
0100
0000
fCBA
A
B
C
0
0
0
0
0
0
1
1
f
Decoder
• Function is configurable by storing the TABLE values.
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System Arch 2006 (Fire Tom Wada) 7HO#8 2006/June/16
Clocked D LATCH
D
CLK
Q
QWhen CLK=‘1’
D Q
Q1 bit memory by NOR cross-loopWhen CLK=1, Q = D, /Q=not(D)When CLK=0, Q holds previous data.
When CLK=‘0’
Q
QD Q
CLKCIRCUIT SYMBOL:
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System Arch 2006 (Fire Tom Wada) 8HO#8 2006/June/16
Master-Slave D Flip-Flop
2 LATCHES in seriesStill work as 1 bit memoryCLK edge Trigger OperationMost commonly used memory element in the state-of-the-art synchronous Digital Design.Q only changes CLK edge (once in one cycle).
D Q
CLK
D Q
CLK
CLK
D Q CLK
D
1 1 0 1 0Q
D QCIRCUIT SYMBOL:
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System Arch 2006 (Fire Tom Wada) 9HO#8 2006/June/16
Digital System is just FF + CLs
CLD Q
D Q
D Q
D Q
CL
CLD Q
FPGA supports such digital circuit with configurability.FPGA’s basic element
D QCL
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System Arch 2006 (Fire Tom Wada) 10HO#8 2006/June/16
Example of Circuit Synthesis
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System Arch 2006 (Fire Tom Wada) 11HO#8 2006/June/16
XILINX FPGA
Field Programmable Gate Array
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System Arch 2006 (Fire Tom Wada) 12HO#8 2006/June/16
XILINX XC3000 Family I/OElectronic Static Discharge ProtectionCMOS, TTL inputRegistered /Non Registered I/O
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System Arch 2006 (Fire Tom Wada) 13HO#8 2006/June/16
XILINX XC3000 Family CLBCLB: Configurable Logic BlockLook-up table for combinational logicD-Flip-FlopsLook-up Table = RAM
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System Arch 2006 (Fire Tom Wada) 14HO#8 2006/June/16
XILINX XC4000 Family CLBTwo Stage Look-up Table
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System Arch 2006 (Fire Tom Wada) 15HO#8 2006/June/16
XILINX VIRTEX FAMILY ARCHITECTURE
CLB: Configurable Logic BlockMany 4Kbit RAM BLOCK RAMDLL (Delay-Locked Loops) to provide controlled-delay clock networksMultiplier (18b x 18b) Macro also supported (not in figure)
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System Arch 2006 (Fire Tom Wada) 16HO#8 2006/June/16
XILINX VIRTEX FAMILY CLBCLB: Configurable Logic BlockMany 4Kbit RAM BLOCK RAMDLL (Delay-Locked Loops) to provide controlled-delay clock networks
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System Arch 2006 (Fire Tom Wada) 17HO#8 2006/June/16
XILINX VIRTEX FAMILY I/OElectronic Static Discharge ProtectionCMOS, TTL inputRegistered /Non Registered I/O
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System Arch 2006 (Fire Tom Wada) 18HO#8 2006/June/16
ALTERA CPLD
Complex Programmable Logic Devices
Altera uses less routing resource than XilinxAltera’s Logic Array Block (LAB) is more complex than Xilinx’s CLBs. Then fewer LABs in on chip than Xilinx’s CLBs.
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System Arch 2006 (Fire Tom Wada) 19HO#8 2006/June/16
ALTERA FLEX8000 ARCHITECUREEach LAB has eight LEs (Logic Elements) .
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System Arch 2006 (Fire Tom Wada) 20HO#8 2006/June/16
ALTERA FLEX8000 Logic Element (LE)
CARRY, CASCADE signals
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System Arch 2006 (Fire Tom Wada) 21HO#8 2006/June/16
ALTERA APEX 20K ARCHITECTURE
MANY RAMsLarge Number Input combinational logic such as MultiplierPhase Locked Loop for Advanced Clock generation
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System Arch 2006 (Fire Tom Wada) 22HO#8 2006/June/16
How to Design your Digital Systemusing Hard-Macro Blocks
White Blocks might be available (Hardware pre-designed Blocks)
Your Circuit
RAM
I/O circuit
ROM
Multiplier
CPU
RAM
ROM
SoftWarefor
CPU
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System Arch 2006 (Fire Tom Wada) 23HO#8 2006/June/16
Hardware Description Languages (HDLs)
HDL is a software programming language used to model the intended operation of a piece of hardware.Two level of modeling
Abstract behavior modelingHardware structure modeling: Input to Circuit Synthesis
Two kinds of LanguageVHDL: Very High Speed Integrated Circuit hardware description language
Similar to Pascal Programming languageVerilog HDL:
Similar to C Programming language
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System Arch 2006 (Fire Tom Wada) 24HO#8 2006/June/16
HALF_ADDER exampleVHDL Verilog HDL
module HALF_ADDER (A, B,S, C
);
input A, B;output S, C;
assign S = A ^ B;assign C = A & B;
endmodule
library IEEE;use IEEE.std_logic_1164.all;
entity HALF_ADDER isport ( A, B : in std_logic;
S, C : out std_logic );end HALF_ADDER;
architecture STRUCTURE of HALF_ADDER isbegin
S <= A xor B;C <= A and B;
end STRUCTURE;
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System Arch 2006 (Fire Tom Wada) 25HO#8 2006/June/16
Moving Average Filter by VHDLlibrary IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_ARITH.all;
entity AVG4 isport(CLK : in std_logic;
FMINPUT : in std_logic_vector(7 downto 0);AVGOUT : out std_logic_vector(7 downto 0));
end AVG4;
architecture RTL of AVG4 is
signal FF1, FF2, FF3, FF4 : std_logic_vector(7 downto 0);signal SUM : std_logic_vector(9 downto 0);
begin
-- SHIFT REGISTERprocess(CLK) begin
if (CLK'event and CLK = '1') thenFF1 <= FMINPUT;FF2 <= FF1;FF3 <= FF2;FF4 <= FF3;
end if;end process;
-- SUMSUM <=signed(FF1(7)&FF1(7)&FF1)+signed(FF2(7)&FF2(7)&FF2)
+signed(FF3(7)&FF3(7)&FF3)+signed(FF4(7)&FF4(7)&FF4);
-- DIVIDE BY 4 (SHIFT 2 bit), OUTPUT REGISTERprocess(CLK) begin
if (CLK'event and CLK='1') thenAVGOUT <= SUM(9 downto 2);
end if;end process;
end RTL;
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System Arch 2006 (Fire Tom Wada) 26HO#8 2006/June/16
Simulated Waveform
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System Arch 2006 (Fire Tom Wada) 27HO#8 2006/June/16
Synthesized Circuit
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System Arch 2006 (Fire Tom Wada) 28HO#8 2006/June/16
XILINX VP70 FLOORPLAN