Fig. 10.1 The 741 op-amp circuit. Q11, Q12, and R5 generate a reference bias current, IREF, Q10, Q9, and Q8 bias the input stage, which is composed of Q1 to Q7. The second gain stage is composed f Q16 and Q17 with Q13 acting as active load. The class AB output stage is formed by Q14 and Q20 with biasing devices Q18 and Q19 and an input buffer Q23. Transistors Q15, Q21, Q24, and Q22 serve to protect the amplifier against output short circuit and are normally off.

Fig. 10.3 The dc analysis of the 741 input stage.

Fig. 10.4 The dc analysis of the 741 input stage, continued

Fig. 10.6 Small-signal analysis of the 741 input stage

Fig. 10.7 The load circuit of the input stage fed by the two complementary current signals generated by Q1 through Q4 in Fig. 10.6. The order of the analysis steps is indicated by the circled numbers.

Fig. 10.15 The 741 output stage.

Fig. 10.16 Model for the 741 output stage.

Fig. 10.23 Two-stage CMOS op-amp configuration.

Fig. 10.25 Bias circuit for the CMOS op amp.

Fig. 10.26 Employing the cascode configuration in the first stage of a CMOS op amp: Transistors Q1C and Q2C are the cascode transistors for the differential amplifier Q1, Q2, and raise the output resistance of Q2 by the factor gm2Cro2C. Transistors Q3, Q3C, Q4, and Q4C form a Wilson current mirror that provides a high load resistance, Ro4C. The total output resistance of the first stage is about two orders of magnitude higher than that of the first stage of the circuit in Fig. 10.23.

Fig. 10.27 A folded-cascode CMOS op amp. Here the n-channel devices Q1C and Q2C form the common-gate stage of the cascoded input stage. Transistors Q3, Q3C, Q4, and Q4C form a modified Wilson current mirror that acts as the load for the gain stage.

Fig. 10.28 A BiCMOS folded-cascode op amp. BJTs are employed to implement the common-base stage Q1C, Q2C . The high value of gm1C = gm2C raises the frequency of the nondominant pole that results at the input of the common-base stage. Thus for a given value of CL, wt = gm1/CL can be increased by operating the first stage at a higher gm.

Fig. 10.29 Process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit. The switch closes seconds every period. (b) Input signal waveform. (c) sampling signal (control signal for the switch). (d) Output signal (to be fed to the A/D converter.

Fig. 10.32 An N-bit D/A converter using a binary-weighted resistive ladder network.

Fig. 10.33 Basic circuit configurations of a DAC utilizing an R-2R ladder network.

Fig. 10.34 A practical circuit implementation of a DAC utilizing an R-2R ladder network.

Fig. 10.37 The dual-slope A/D conversion method. Note that vA is assumed to be negative.

Fig. 10.39 Charge-distribution A/D converter suitable for CMOS implementation. (a) Sample phase; (b) hold phase; and (c) charge-redistribution phase.