fig. 7.1 fixed-bias...

Fig. 7.1 Fixed-bias configuration.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Fig. 7.2 Network for dc analysis.

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Fig. 7.3 Plotting Shockley’s equation.

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Fig. 7.4 Finding the solution for the fixed-bias configuration.

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Fig. 7.5 Measuring the quiescent values of ID and VGS.

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Fig. 7.6 Example 7.1.

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Fig. 7.7 Graphical solution for the network of Fig. 7.6.

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Fig. 7.8 JFET self-bias configuration.

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Fig. 7.9 DC analysis of the self-bias configuration.

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Fig. 7.10 Defining a point on the self-bias line.

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Fig. 7.11 Sketching the self-bias line.

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Fig. 7.13 Sketching the self-bias line for the network of Fig. 7.12.

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Fig. 7.14 Sketching the device characteristics for the JFET of Fig. 7.12.

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Fig. 7.15 Determining the Q-point for the network of Fig. 7.12.

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Fig. 7.16 Determining the quiescient point of operation for the network of Example 7.2.

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Fig. 7.19 Sketching the dc equivalent of the network of Fig. 7.18.

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Fig. 7.21 Voltage-divider bias arrangement.

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Fig. 7.22 Redrawn network of Fig. 7.21 for dc analysis.

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Fig. 7.23 Sketching the network equation for the voltage-divider configuration.

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Fig. 7.24 Effect of RS on the resulting Q-point.

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Fig. 7.28 Determining the network equation for the configuration of Fig. 7.27.

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Fig. 7.36 Transfer characteristics of an n-channel enhancement-type MOSFET.

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Fig. 7.37 Feedback biasing arrangement.

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Fig. 7.38 DC equivalent of the network of Fig. 7.37.

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Fig. 7.41 Plotting the transfer curve for the MOSFET of Fig. 7.40.

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Fig. 7.43 Voltage-divider biasing arrangement for an n-channel enhancement MOSFET.

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Fig. 7.45 Determining the Q-point for the network of Example 7.12.

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Fig. 7.50 Self-bias configuration to be designed.

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Fig. 7.52 Determining VGSQ for the network of Fig. 7.51.

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Fig. 7.55 Checking the dc operation of the JFET self-bias configuration.

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Fig. 7.56 p-Channel configurations. (a) JFET; (b) Depletion-type MOSFET; (c) Enhancement-type MOSFET.

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Fig. 7.58 Determining the Q-point for the JFET configuration of Fig. 7.57.

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Fig. 7.59 Universal JFET bias curve.

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Fig. 7.61 Universal curve for Examples 7.19 and 7.20.

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Fig. 7.63 JFET characteristics: (a) defining the linear region; (b) expanding the linear region.

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Fig. 7.64 JFET voltage-controlled drain resistance: (a) general equivalence; (b) with VGS = 0 V; (c) with VGS = -1.5

V.

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Fig. 7.65 (a) Noninverting op-amp configuration; (b) using the voltage-controlled drain-to-source resistance of a

JFET in the noninverting amplifier.

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Fig. 7.66 Demonstrating the benefits of dc control: system with (a) ac control; (b) dc control; (c) RF noise pickup.

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Fig. 7.67 JFET voltmeter: (a) network; (b) reduced equivalent with an 8-V measurement. (Redrawn from

International Rectifier Corporation.)

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Fig. 7.68 JFET timer network.

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Fig. 7.69 Basic elements of a fiber optic cable.

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Fig. 7.70 Basic components of an optical communication system.

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Fig. 7.71 TTL fiber optic communication channel: (a) JFET design; (b) passing on the signal generated across the

photodiode.

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Fig. 7.72 MOSFET relay driver.

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Fig. 7.73 JFET voltage-divider configuration with PSpice Windows results for current and voltage levels.

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Fig. 7.74 Verifying the hand-calculated solution of Example 7.13 using PSpice Windows.

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Fig. 7.75 Network used to obtain the characteristics of the IRF150 enhancement-type n-channel MOSFET.

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Fig. 7.76 Characteristics of the IRF500 MOSFET of Figure 7.75 with a load line defined by the network of Figure

7.77.

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Fig. 7.77 Feedback-biasing arrangement using an IRF150 enhancement-type MOSFET.

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Fig. 7.78 Verifying the results of Example 7.2 using Multisim.

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Fig. 7.79 Problems 1 and 35.

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Fig. 7.80 Problem 2.

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Fig. 7.84 Problems 6, 7, and 36.

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Robert L. Boylestad





fig. 7.1 fixed-bias...

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