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Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost

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Page 1: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost

Page 2: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Figure DESN2 The V-Cycle for Design System Architecture

Page 3: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Figure DESN3 Hardware and Software Design Gaps versus Time

Page 4: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Figure DESN5 Evolving Role of Design Phases in Overall System Power Minimization

Page 5: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Figure DESN8 Variability-Induced Failure Rates for Three Canonical Circuit Types

Page 6: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Figure DESN9 Power Supply-Dependent Failure Rates for Three Canonical Circuit Types

Page 7: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

0%10%20%30%40%50%60%70%80%90%

100%geo scaling

equivalent scaling

functional diversification

Figure DESN11 Moore and Non-Moore Design Technology Improvements

Page 8: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Figure DESN12 Possible Variability Abstraction Levels

PhysicalPhysical

DeviceDevice

GateGate

ChipChip

Bit CellBit Cell

CircuitCircuit ArrayArray

Page 9: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Product cost

Development R&D

Manufacturing

Marketing, sales

General, administrative

Maintenance, service

Financial

Labor

Infrastructure

Chip/circuit/physical design

Chip integration

Verification, test

SW development

EDA licenses

EDA integration & support

Test chips

Depreciation/amortization

Product cost

Development R&D

Manufacturing

Marketing, sales

General, administrative

Maintenance, service

Financial

Labor

Infrastructure

Chip/circuit/physical design

Chip integration

Verification, test

SW development

EDA licenses

EDA integration & support

Test chips

Depreciation/amortization

Figure DESN13 Simplified Electronic Product Development Cost Model

Page 10: Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform

Figure DESN14 Impact of Low-Power Design Technology on SOC Consumer Portable Power Consumption


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