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Single, 12-/14-/16-Bit nanoDAC with 5 ppm/°C On-Chip Reference in SOT-23

Data Sheet AD5620/AD5640/AD5660

Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES Low power, single nanoDACs

AD5660: 16 bits AD5640: 14 bits AD5620: 12 bits

12-bit accuracy guaranteed On-chip, 1.25 V/2.5 V, 5 ppm/°C reference Tiny 8-lead SOT-23, MSOP, and LFCSP packages Power-down to 480 nA @ 5 V, 200 nA @ 3 V 3 V/5 V single power supply Guaranteed 16-bit monotonic by design Power-on reset to zero/midscale 3 power-down functions Serial interface with Schmitt-triggered inputs Rail-to-rail operation SYNC interrupt facility

APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators

PRODUCT HIGHLIGHTS

1. 12-/14-/16-bit nanoDAC—12-bit accuracy guaranteed. 2. On-chip, 1.25 V/2.5 V, 5 ppm/°C reference. 3. Available in 8-lead SOT-23, MSOP, and LFCSP packages. 4. Power-on reset to 0 V or midscale. 5. 10 µs settling time.

Table 1. Related Device Part No. Description AD5662 2.7 V to 5.5 V, 16-bit DAC in SOT-23, LFCSP, and

MSOP, external reference

FUNCTIONAL BLOCK DIAGRAM

AD5620/AD5640/AD5660

VREFOUT GND

REF(+)

VDD

RESISTORNETWORK

POWER-DOWNCONTROL LOGIC

DACREGISTER

POWER-ONRESET

1.25/2.5VREF

OUTPUTBUFFER16-BIT

DAC

INPUTCONTROL

LOGIC

VOUT

VFB

SYNC SCLK DIN

0453

9-00

1

Figure 1.

GENERAL DESCRIPTION

The AD5620/AD5640/AD5660, members of the nanoDAC™ family of devices, are low power, single, 12-/14-/16-bit, buffered voltage-out DACs and are guaranteed monotonic by design.

The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/°C reference, giving a full-scale output voltage range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output voltage range of 5 V. The reference associated with each part is available at the VREFOUT pin.

The parts incorporate a power-on reset circuit to ensure that the DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2) or midscale (AD5620-3 and AD5660-3) and remains there until a valid write takes place. The parts contain a power-down feature that reduces the current consumption of the device to 480 nA at 5 V and provides software-selectable output loads while in power-down mode. The power consumption is 2.5 mW at 5 V, reducing to 1 µW in power-down mode.

The AD5620/AD5640/AD5660 on-chip precision output amplifier allows rail-to-rail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. The AD5620/AD5640/AD5660 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI®, QSPI™, MICROWIRE™, and DSP interface standards.

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AD5620/AD5640/AD5660 Data Sheet

Rev. G | of 28

TABLE OF CONTENTS Features .............................................................................................. 1

Applications ....................................................................................... 1

Product Highlights ........................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AD5620/AD5640/AD5660-2-3 .................................................. 3

AD5620/AD5640/AD5660-1 ...................................................... 5

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 16

Theory of Operation ...................................................................... 17

D/A Section ................................................................................. 17

Resistor String ............................................................................. 17

Internal Reference ...................................................................... 17

Output Amplifier ........................................................................ 17

Serial Interface ............................................................................ 17

Input Shift Register .................................................................... 18

SYNC Interrupt .......................................................................... 18

Power-On Reset .......................................................................... 19

Power-Down Modes .................................................................. 19

Microprocessor Interfacing ....................................................... 19

Applications Information .............................................................. 21

Using a REF19x as a Power Supply for the AD5620/AD5640/AD5660 ....................................................... 21

Bipolar Operation Using the AD5660 ..................................... 21

Using the AD5660 as an Isolated, Programmable, 4 mA to 20 mA Process Controller ......................................................... 22

Using the AD5620/AD5640/AD5660 with a Galvanically Isolated Interface ........................................................................ 22

Power Supply Bypassing and Grounding ................................ 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 26

REVISION HISTORY

8/13—Rev. F to Rev. G

Added LFCSP (Throughout)........................................................... 1 Added Thermal Impedance for LFCSP; Table 5 ........................... 8 Added Figure 5; Renumbered Sequentially .................................. 9 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 26

12/10—Rev. E to Rev. F

Changes to Ordering Guide .......................................................... 25

7/10—Rev. D to Rev. E

Moved Using the AD5660 as an Isolated, Programmable, 4 mA to 20 mA Process Controller Section ........................................... 22 Moved Power Supply Bypassing and Grounding Section ......... 23 Changes to Ordering Guide .......................................................... 25

3/10—Rev. C to Rev. D

Changes to Ordering Guide .......................................................... 24

10/09—Rev. B to Rev. C Changes to Ordering Guide .......................................................... 23

5/06—Rev. A to Rev. B

Updated Formatted ............................................................ Universal Updated Temperature Range ............................................ Universal Changes to Table 2 ............................................................................. 3 Changes to Table 5 ............................................................................. 8 Replaced Figure 17, Figure 18, and Figure 19 ............................. 12 Changes to Ordering Guides .................................................. 23, 24

9/05—Rev. 0 to Rev. A

Changes to Specifications ................................................................. 5 Changes to Outline Dimensions .................................................. 23

7/05—Revision 0: Initial Version


Rev. G | of 28

SPECIFICATIONS AD5620/AD5640/AD5660-2-3 VDD = 4.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted.

Table 2. Parameter A Grade1 B Grade1 C Grade1 Unit Conditions/Comments STATIC PERFORMANCE2

AD5660 Resolution 16 16 16 Bits min Relative Accuracy ±32 ±16 ±16 LSB max Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design

AD5640 Resolution 14 14 14 Bits min Relative Accuracy ±8 ±4 ±4 LSB max Differential Nonlinearity ±0.5 ±0.5 ±0.5 LSB max Guaranteed monotonic by design


Zero-Code Error 2 2 2 mV typ All 0s loaded to DAC register 10 10 10 mV max Offset Error ±10 ±10 ±10 mV max Full-Scale Error −0.15 −0.15 −0.15 % FSR typ All 1s loaded to DAC register ±1 ±1 ±1 % FSR max Gain Error ±1.5 ±1.5 ±1.5 % FSR max Zero-Code Error Drift ±2 ±2 ±2 µV/°C typ Gain Temperature Coefficient ±2.5 ±2.5 ±2.5 ppm typ Of FSR/°C DC Power Supply Rejection Ratio −75 −75 −75 dB typ DAC code = midscale; VDD = 5 V ± 10%

OUTPUT CHARACTERISTICS3 Output Voltage Range 0 0 0 V min VDD VDD VDD V max Output Voltage Settling Time 8 8 8 µs typ ¼ to ¾ scale change settling to ±2 LSB 10 10 10 µs max RL = 2 kΩ; 0 pF < CL < 200 pF Slew Rate 1.5 1.5 1.5 V/µs typ ¼ to ¾ scale Capacitive Load Stability 2 2 2 nF typ RL = ∞ 10 10 10 nF typ RL = 2 kΩ Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10 kHz Output Noise (0.1 Hz to 10 Hz) 45 45 45 µV p-p typ DAC code = midscale Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry Digital Feedthrough 0.1 0.1 0.1 nV-s typ DC Output Impedance 0.5 0.5 0.5 Ω typ Short-Circuit Current 30 30 30 mA typ VDD = 5 V Power-Up Time 5 5 5 µs typ Coming out of power-down mode; VDD = 5 V

REFERENCE OUTPUT Output Voltage 2.495 2.495 2.495 V min At ambient 2.505 2.505 2.505 V max Reference TC3 ±10 ±10 ±5 ppm/°C typ ±10 ppm/°C max Output Impedance 7.5 7.5 7.5 kΩ typ


Rev. G | of 28

Parameter A Grade1 B Grade1 C Grade1 Unit Conditions/Comments LOGIC INPUTS3

Input Current ±2 ±2 ±2 µA max All digital inputs VINL, Input Low Voltage 0.8 0.8 0.8 V max VDD = 5 V VINH, Input High Voltage 2 2 2 V min VDD = 5 V Pin Capacitance 3 3 3 pF typ

POWER REQUIREMENTS VDD 4.5 4.5 4.5 V min All digital inputs at 0 V or VDD 5.5 5.5 5.5 V max DAC active and excluding load current IDD (Normal Mode)

VDD = 4.5 V to 5.5 V 0.55 0.55 0.55 mA typ VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 1 1 1 mA max VIH = VDD and VIL = GND

IDD (All Power-Down Modes) VDD = 4.5 V to 5.5 V 0.48 0.48 0.48 µA typ VIH = VDD and VIL = GND VDD = 4.5 V to 5.5 V 1 1 1 µA max VIH = VDD and VIL = GND

1 Temperature range is −40°C to +105°C, typical at +25°C. 2 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output

unloaded. Linearity tested with VDD = 5.5 V. If part is operated with a VDD < 5 V, the output is clamped to VDD. 3 Guaranteed by design and characterization; not production tested.


Rev. G | of 28

AD5620/AD5640/AD5660-1 VDD

1 = 2.7 V to 3.3 V, RL = 2 kΩ to GND, CL = 200 pF to GND, CREFOUT = 100 nF; all specifications TMIN to TMAX, unless otherwise noted.

Table 3. Parameter A Grade2 B Grade2 C Grade2 Unit Conditions/Comments STATIC PERFORMANCE3

AD5660 Resolution 16 16 16 Bits min Relative Accuracy ±32 ±16 ±16 LSB max Differential Nonlinearity ±1 ±1 ±1 LSB max Guaranteed monotonic by design



Zero-Code Error 2 2 2 mV typ All 0s loaded to DAC register 8 8 8 mV max Offset Error ±9 ±9 ±9 mV max Full-Scale Error ±0.15 ±0.15 ±0.15 % FSR typ All 1s loaded to DAC register ±0.85 ±0.85 ±0.85 % FSR max Gain Error ±0.85 ±0.85 ±0.85 % FSR max Zero-Code Error Drift ±2 ±2 ±2 µV/°C typ Gain Temperature Coefficient ±2.5 ±2.5 ±2.5 ppm typ Of FSR/°C DC Power Supply Rejection Ratio −60 −60 −60 dB typ DAC code = midscale; VDD = 3 V ± 10%

OUTPUT CHARACTERISTICS4 Output Voltage Range 0 0 V min VDD VDD VDD V max Output Voltage Settling Time 8 8 8 µs typ ¼ to ¾ scale change settling to ±2 LSB 10 10 10 µs max RL = 2 kΩ; 0 pF < CL < 200 pF Slew Rate 1.5 1.5 1.5 V/µs typ ¼ to ¾ scale Capacitive Load Stability 2 2 2 nF typ RL = ∞ 10 10 10 nF typ RL = 2 kΩ Output Noise Spectral Density 80 80 80 nV/√Hz typ DAC code = midscale, 10 kHz Output Noise (0.1 Hz to 10 Hz) 20 20 20 µV p-p typ DAC code = midscale Digital-to-Analog Glitch Impulse 5 5 5 nV-s typ 1 LSB change around major carry Digital Feedthrough 0.1 0.1 0.1 nV-s typ DC Output Impedance 0.5 0.5 0.5 Ω typ Short-Circuit Current 30 30 30 mA typ VDD = 3 V Power-Up Time 6 6 6 µs typ Coming out of power-down mode; VDD = 3 V

REFERENCE OUTPUT Output Voltage 1.247 1.247 1.247 V min At ambient 1.253 1.253 1.253 V max Reference TC4 ±10 ±10 ±5 ppm/°C typ ±15 ppm/°C max Output Impedance 7.5 7.5 7.5 kΩ typ


Rev. G | of 28

Parameter A Grade2 B Grade2 C Grade2 Unit Conditions/Comments LOGIC INPUTS4

Input Current ±1 ±1 ±1 µA max All digital inputs VINL, Input Low Voltage 0.8 0.8 0.8 V max VDD = 3 V VINH, Input High Voltage 2 2 2 V min VDD = 3 V Pin Capacitance 3 3 3 pF max

POWER REQUIREMENTS VDD 2.7 2.7 2.7 V min All digital inputs at 0 V or VDD 3.3 3.3 3.3 V max DAC active and excluding load current IDD (Normal Mode)

VDD = 2.7 V to 3.3 V 0.55 0.55 0.55 mA typ VIH = VDD and VIL = GND VDD = 2.7 V to 3.3 V 0.65 0.65 0.65 mA max VIH = VDD and VIL = GND

IDD (All Power-Down Modes) VDD = 2.7 V to 3.3 V 0.2 0.2 0.2 µA typ VIH = VDD and VIL = GND VDD = 2.7 V to 3.3 V 0.25 0.25 0.25 µA max VIH = VDD and VIL = GND

1 Part is functional with VDD up to 5.5 V. 2 Temperature range is −40°C to +105°C, typical at +25°C. 3 Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output

unloaded. 4 Guaranteed by design and characterization; not production tested.


Rev. G | of 28

TIMING CHARACTERISTICS All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2. VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 4. Limit at TMIN, TMAX Parameter VDD = 2.7 V to 3.6 V VDD = 3.6 V to 5.5 V Unit Conditions/Comments t1

1 50 33 ns min SCLK cycle time t2 13 13 ns min SCLK high time t3 13 13 ns min SCLK low time t4 13 13 ns min SYNC to SCLK falling edge setup time

t5 5 5 ns min Data setup time t6 4.5 4.5 ns min Data hold time t7 0 0 ns min SCLK falling edge to SYNC rising edge

t8 50 33 ns min Minimum SYNC high time

t9 13 13 ns min SYNC rising edge to SCLK fall ignore

t10 0 0 ns min SCLK falling edge to SYNC fall ignore 1 Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V.

DIN

LSB = DB0MSB = DB23 FOR AD5660MSB = DB15 FOR AD5620/AD5640

SYNC

SCLK

MSB LSB

t9t10

t4t3

t2 t7

t6t5

t1

t8

0453

9-00

2

Figure 2. Serial Write Operation


Rev. G | of 28

ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted.

Table 5. Parameter Rating VDD to GND −0.3 V to +7 V VOUT to GND −0.3 V to VDD + 0.3 V VFB to GND −0.3 V to VDD + 0.3 V VREFOUT to GND −0.3 V to VDD + 0.3 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Operating Temperature Range

Industrial −40°C to +105°C Storage Temperature Range −65°C to +150°C Junction Temperature (TJ max) 150°C

Power Dissipation (TJ max − TA)/θJA SOT-23 Package (4-Layer Board)

θJA Thermal Impedance 119°C/W MSOP Package (4-Layer Board)

θJA Thermal Impedance 141°C/W θJC Thermal Impedance 44°C/W

LFCSP Package(4-Layer Board) θJA Thermal Impedance 103°C/W θJC Thermal Impedance 44.4°C/W

Reflow Soldering Peak Temperature SnPb 240°C Pb-Free 260°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION


Rev. G | of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SYNC

0453

9-00

3

VDD 1

VREFOUT 2

VFB 3

VOUT 4

GND8

DIN7

SCLK6

5

AD5620/AD5640/AD5660TOP VIEW

(Not to Scale)

Figure 3. SOT-23 Pin Configuration

SYNC

0453

9-00

4VDD 1

VREFOUT 2

VFB 3

VOUT 4

GND8

DIN7

SCLK6

5

AD5620/AD5640/AD5660TOP VIEW

(Not to Scale)

Figure 4. MSOP Pin Configuration

3

4

1

2

6

5

8

7AD5620/AD5640/AD5660TOP VIEW

VDD

VREFOUT

VFB

VOUT

GND

DIN

SCLK

SYNC

0453

9-10

5

Figure 5. LFCSP Pin Configuration

Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Power Supply Input. These parts can operate from 2.7 V to 5.5 V. VDD should be decoupled to GND. 2 VREFOUT Reference Voltage Output. 3 VFB Feedback Connection for the Output Amplifier. VFB should be connected to VOUT for normal operation. 4 VOUT Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation. 5 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When

SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle for the AD5660 and the 16th clock cycle for AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.

6 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz.

7 DIN Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input.

8 GND Ground Reference Point for all Circuitry on the Part.


Rev. G | of 28

TYPICAL PERFORMANCE CHARACTERISTICS

CODE

INL

ERR

OR

(LSB

)

10

8

0

–10

–6

–8

–4

6

–2

4

2

6500

0

6000

0

5500

0

5000

0

4500

0

4000

0

3500

0

3000

0

2500

0

2000

0

1500

0

1000

0

50000

VDD = 5VVREFOUT = 2.5VTA = 25°C

0453

9-00

5

Figure 6. INL—AD5660-2/AD5660-3

CODE

INL

ERR

OR

(LSB

)

4

3

–4

–3

–2

2

–1

1

0

1625

0

1500

0

1375

0

1250

0

1125

0

1000

0

8750

7500

6250

5000

3750

2500

12500


0453

9-00

6


CODE

INL

ERR

OR

(LSB

)

1.0

0.8

0

–1.0

–0.8

–0.6

0.6

–0.4

–0.2

0.4

0.2

0 1000500 20001500 350030002500 4000


0453

9-00

7


CODE

DN

L ER

RO

R (L

SB)

1.0

0.8

0

–1.0

–0.6

–0.8

–0.4

0.6

–0.2

0.4

0.2

6500

0

6000

0

5500

0

5000

0

4500

0

4000

0

3500

0

3000

0

2500

0

2000

0

1500

0

1000

0

50000


0453

9-00

8

Figure 9. DNL—AD5660-2/AD5660-3

CODE

DN

L ER

RO

R (L

SB)

0.5

0.4

0

–0.5

–0.3

–0.4

–0.2

0.3

–0.1

0.2

0.1

1625

0

1500

0

1375

0

1250

0

1125

0

1000

0

8750

7500

6250

5000

3750

2500

12500


0453

9-00

9


CODE

DN

L ER

RO

R (L

SB)

0.20

0.15

0

–0.20

–0.15

–0.10

0.10

–0.05

0.05

0 1000500 20001500 350030002500 4000


0453

9-01

0



Rev. G | of 28

CODE

INL

ERR

OR

(LSB

)

10

8

4

6

2

0

–4

–2

–6

–8

–10

6500

0

6000

0

5500

0

5000

0

4500

0

4000

0

3500

0

3000

0

2500

0

2000

0

1500

0

1000

0

50000

0453

9-01

7


Figure 12. INL—AD5660-1

CODE

INL

ERR

OR

(LSB

)

4

–4

1625

0

1500

0

1375

0

1250

0

1125

0

1000

0

8750

7500

6250

5000

3750

2500

12500

0453

9-01

8

3

2

1

0

–1

–2

–3



CODE

INL

ERR

OR

(LSB

)

1.0

–1.00 500 1000 1500 2000 2500 3000 3500 4000

0453

9-01

9

0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8



CODE

DN

L ER

RO

R (L

SB)

1.0

0.8

0.4

0.6

0.2

0

–0.4

–0.2

–0.6

–0.8

–1.0

6500

0

6000

0

5500

0

5000

0

4500

0

4000

0

3500

0

3000

0

2500

0

2000

0

1500

0

1000

0

50000

0453

9-02

0


Figure 15. DNL—AD5660-1

CODE

DN

L ER

RO

R (L

SB)

0.5

–0.5

1625

0

1500

0

1375

0

1250

0

1125

0

1000

0

8750

7500

6250

5000

3750

2500

12500

0453

9-02

1

0

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4



CODE

DN

L ER

RO

R (L

SB)

0.20

–0.200 500 1000 1500 2000 2500 3000 3500 4000

0453

9-02

5

0

0.15

0.10

0.05

–0.05

–0.10

–0.15




Rev. G | of 28

0453

9-01

1

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

ERR

OR

(LSB

)

12

–12

–10

–8

–6

–4

–2

0

2

4

6

8

10

MAX DNL

MAX INL

MIN DNL

MIN INL

VDD = 5V

Figure 18. INL Error and DNL Error vs. Temperature

0453

9-01

2

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

0.4

–0.4

–0.2

0

0.2

ERR

OR

(%FS

R)

VDD = 5V

FULL SCALE ERROR

GAIN ERROR

Figure 19. Gain Error and Full-Scale Error vs. Temperature

0453

9-01

3

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

1.6

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

ERR

OR

(mV)

VDD = 5V

ZERO CODE ERROR

OFFSET ERROR

Figure 20. Zero-Code and Offset Error vs. Temperature

IDD (mA)

NU

MB

ER O

F D

EVIC

ES

200

180

160

140

100

120

80

20

40

60

0

0.45

0.46

0.47

0.48

0.49

0.50

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

0.60

0.61

0.62

0.63

0.65

0.64

0.66

0.67

0453

9-01

4

VDD = 5VTA = 25°C

VDD = 3.3V

Figure 21. IDD Histogram

CURRENT (mA)

ERR

OR

VO

LTA

GE

(V)

0.50

0.40

–0.50

–0.40

–0.30

–0.20

–0.10

0

0.10

0.20

0.30

–10 –8 –6 –4 –2 0 2 4 86 10

0453

9-02

2

VDD = 3VVREFOUT = 1.25V


DAC LOADED WITHZERO-SCALESINKING CURRENT

DAC LOADED WITHFULL-SCALESOURCING CURRENT

Figure 22. Headroom at Rails vs. Source and Sink

CURRENT (mA)

V OU

T (V

)

6.00

5.00

4.00

3.00

2.00

1.00

–1.00

0

–30 –20 –10 0 10 20 30

0453

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3


ZERO SCALE

FULL SCALE

MIDSCALE

1/4 SCALE

3/4 SCALE

Figure 23. Source and Sink Capability—AD5660-2/AD5660-3


Rev. G | of 28

CURRENT (mA)

V OU

T (V

)

4.00

–1.00

0

1.00

2.00

3.00

–30 –20 –10 0 10 20 30

0453

9-02

4


ZERO SCALE

FULL SCALE

MIDSCALE

1/4 SCALE

3/4 SCALE

Figure 24. Source and Sink Capability—AD5660-1

CODE

I DD

(mA

)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0512 2051210512 30512 40512 50512 60512

0453

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5

TA = 25°C

VDD = 3V

VDD = 5V

Figure 25. Supply Current vs. Code

VLOGIC (V)

I DD

(µA

)

1400

1200

1000

800

600

400

200

00 21 3 4 5

0453

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6

TA = 25°C

VDD = 5V

VDD = 3V

Figure 26. Supply Current vs. Logic Input Voltage

0453

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8

TIME BASE = 4µs/DIV

VDD = 5VTA = 25°CFULL-SCALE CODE CHANGE0x0000 TO 0xFFFFOUTPUT LOADED WITH 2kΩAND 200pF TO GND

VOUT = 909mV/DIV

1

Figure 27. Full-Scale Settling Time, 5 V

0453

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9

CH1 2.00VCH3 100mV

CH2 2.00V M40.0ms CH1

VOUT

VDD

VREF

3

1

2

Figure 28. Power-On Reset to 0 V—AD5660-2

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9-03

0

CH1 2.00VCH3 200mV

CH2 2.00V M20.0µs CH1 1.88V

VOUT

VDD

VREF

3

1

2

Figure 29. Power-On Reset to Midscale—AD5660-3


Rev. G | of 28

0453

9-03

1

CH1 1.20VCH3 100mV

CH2 1.00V M100µs CH1 1.87V

VOUT

VDD

VREF

3

1

2

Figure 30. Power-On Reset to 0 V—AD5660-1

0453

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5

CH1 2.00VCH3 50.0mV

M1.00µs CH2 520mV

VOUT

VDD = 3VSCLK

3

1

Figure 31. Exiting Power-Down to Midscale

SAMPLE NUMBER

AM

PLIT

UD

E

2.501250

2.501000

2.500750

2.500500

2.500250

2.500000

2.499750

2.499500

2.499250

2.498750

2.499000

2.4985002.4982502.498000

0 150 200 25050 100 300 350 400 450 500 550

0453

9-03

2

VDD = 5VVREFOUT = 2.5VTA = 25°C13nS/SAMPLE NUMBER1LSB CHANGE AROUND MIDSCALE (0x7FFF TO 0x8000)GLITCH IMPULSE = 0.497nV-s

Figure 32. Digital-to-Analog Glitch Impulse—AD5660-2/AD5660-3

SAMPLE NUMBER

AM

PLIT

UD

E

1.250800

1.250600

1.250400

1.250200

1.250000

1.249800

1.249600

1.249400

1.249200

1.249000

1.248800

1.2486001.248400

0 150 200 25050 100 300 350 400 450 500 550

0453

9-03

3

VDD = 3VVREFOUT = 1.25VTA = 25°C13nS/SAMPLE NUMBER1LSB CHANGE AROUND MIDSCALE (0x7FFF TO 0x8000)GLITCH IMPULSE = 0.284nV-s

Figure 33. Digital-to-Analog Glitch Impulse—AD5660-1

SAMPLE NUMBER

AM

PLIT

UD

E

2.500250

2.500200

2.500150

2.500100

2.5000502.500000

2.499950

2.4999002.499850

2.499800

2.499750

2.499700

2.4996502.499600

0 150 200 25050 100 300 350 400 450 500 550

0453

9-03

4

VDD = 5VTA = 25°C20nS/SAMPLE NUMBERDAC LOADED WITH MIDSCALEDIGITAL FEEDTHROUGH = 0.06nV-s

Figure 34. Digital Feedthrough

CAPACITANCE (nF)

TIM

E (µ

s)

16

14

12

10

8

6

40 1 2 3 4 5 6 7 98 10

0453

9-03

6TA = 25°C

VDD = 5V

VDD = 3V

Figure 35. Settling Time vs. Capacitive Load


Rev. G | of 28

5s/DIV

10µV

/DIV

1

0453

9-03

7

VDD = 5VVREFOUT = 2.5VTA = 25°CDAC LOADED WITH MIDSCALE

Figure 36. 0.1 Hz to 10 Hz Output Noise—AD5660-2/AD5660-3

4s/DIV

5µV/

DIV

1

0453

9-05

4

VDD = 3VVREFOUT = 1.25VTA = 25°CDAC LOADED WITH MIDSCALE

Figure 37. 0.1 Hz to 10 Hz Output Noise—AD5660-1

FREQUENCY (Hz)

OU

TPU

T N

OIS

E (n

V√H

z)

800

0

100

200

300

400

500

600

700

100 100001000 100000 1000000

0453

9-03

8VDD = 3VVREFOUT = 1.25V


TA = 25°CMIDSCALE LOADED

Figure 38. Noise Spectral Density


Rev. G | of 28

TERMINOLOGY Relative Accuracy For the DAC, relative accuracy, or integral nonlinearity (INL), is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Figure 6 through Figure 8 show typical INL vs. code.

Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Figure 9 through Figure 11 show typical DNL vs. code.

Zero-Code Error Zero-code error is a measurement of the output error when zero code (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5620/AD5640/AD5660, because the output of the DAC cannot go below 0 V. It is due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in mV. Figure 20 shows a plot of zero-code error vs. temperature.

Full-Scale Error Full-scale error is a measurement of the output error when full-scale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD − 1 LSB. Full-scale error is expressed as a percentage of the full-scale range. Figure 19 shows a plot of full-scale error vs. temperature.

Gain Error This is a measurement of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal, expressed as a percentage of the full-scale range.

Zero-Code Error Drift This is a measurement of the change in zero-code error with a change in temperature. It is expressed in µV/°C.

Gain Temperature Coefficient This is a measurement of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5660 with Code 512 loaded into the DAC register. It can be negative or positive.

DC Power Supply Rejection Ratio (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for the full-scale output of the DAC. It is measured in dB. VREF is held at 2.5 V, and VDD is varied by ±10%.

Output Voltage Settling Time This indicates the amount of time for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change. It is measured from the 24th falling edge of SCLK.

Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000). See Figure 32 and Figure 33.

Digital Feedthrough Digital feedthrough is a measurement of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s or vice versa.

Noise Spectral Density This is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. Figure 38 shows a plot of noise spectral density.


Rev. G | of 28

THEORY OF OPERATION D/A SECTION The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS process. The architecture consists of a string DAC followed by an output buffer amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C reference that is internally gained up by 2. Figure 39 shows a block diagram of the DAC architecture.

VDD R

R

VOUT

GND

RESISTORSTRING

REF (+)

REF (–) OUTPUTAMPLIFIER

DAC REGISTER

0477

7-02

2

VFB

Figure 39. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal output voltage is given by

××= NREFOUTOUT

DVV2

2

where: D is the decimal equivalent of the binary code that is loaded to the DAC register. 0 to 4095 for AD5620 (12 bit) 0 to 16383 for AD5640 (14 bit) 0 to 65535 for AD5660 (16 bit) N is the DAC resolution.

R

R

R

R

R TO OUTPUTAMPLIFIER

0453

9-04

0

Figure 40. Resistor String

RESISTOR STRING The resistor string section is shown in Figure 40. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

INTERNAL REFERENCE The AD5620/AD5640/AD5660-1 parts include an internal, 1.25 V, 5 ppm/°C reference, giving a full-scale output voltage of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an internal, 2.5 V, 5 ppm/°C reference, giving a full-scale output voltage of 5 V. The reference associated with each part is available at the VREFOUT pin. A buffer is required if the reference output is used to drive external loads. It is recommended that a 100 nF capacitor is placed between the reference output and GND for reference stability.

OUTPUT AMPLIFIER The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. This output buffer amplifier has a gain of 2 derived from a 50 kΩ resistor divider network in the feedback path. The inverting input of the output amplifier is available to the user, allowing for remote sensing. This VFB pin must be connected to VOUT for normal operation. It can drive a load of 2 kΩ in parallel with 1000 pF to GND. Figure 22 shows the source and sink capabilities of the output amplifier. The slew rate is 1.5 V/µs with a ¼ to ¾ full-scale settling time of 10 µs.

SERIAL INTERFACE The AD5620/AD5640/AD5660 have a 3-wire serial interface (SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and MICROWIRE interface standards as well as most DSPs. See Figure 2 for a timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data from the DIN line is clocked into the 16-bit shift register (AD5620/AD5640) or the 24-bit shift register (AD5660) on the falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the AD5620/AD5640/AD5660 compatible with high speed DSPs. On the 16th falling clock edge (AD5620/ AD5640) or the 24th falling clock edge (AD5660), the last data bit is clocked in and the programmed function is executed, that is, a change in the DAC register contents and/or a change in the mode of operation is executed. At this stage, the SYNC line can be kept low or be brought high. In either case, it must be brought high for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. Because the SYNC buffer draws more current when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be idled low between write sequences for even lower power operation of the parts. As is mentioned previously, however, SYNC must be brought high again just before the next write sequence.


Rev. G | of 28

INPUT SHIFT REGISTER AD5620/AD5640

The input shift register is 16 bits wide for the AD5620/AD5640 (see Figure 41 and Figure 42). The first two bits are control bits that control which mode of operation the part is in (normal mode or any of the three power-down modes). The next 14/12 bits, respectively, are the data bits. These are transferred to the DAC register on the 16th falling edge of SCLK.

AD5660

The input shift register is 24 bits wide for the AD5660 (see Figure 43). The first six bits are don’t care bits. The next two are control bits that control which mode of operation the part is in (normal mode or any of the three power-down modes). For a more complete description of the various modes, see the Power-Down Modes section. The next 16 bits are the data bits. These are transferred to the DAC register on the 24th falling edge of SCLK.

SYNC INTERRUPT

In a normal write sequence for the AD5660, the SYNC line is kept low for at least 24 falling edges of SCLK, and the DAC is updated on the 24th falling edge. However, if SYNC is brought high before the 24th falling edge, this acts as an interrupt to the write sequence. The shift register is reset, and the write sequence is seen as invalid. Neither an update of the DAC register contents nor a change in the operating mode occurs (see Figure 44). Similarly, in a normal write sequence for the AD5620/AD5640, the SYNC line is kept low for at least 16 falling edges of SCLK, and the DAC is updated on the 16th falling edge. However, if SYNC is brought high before the 16th falling edge, this acts as an interrupt to the write sequence.

DATA BITS

DB15 (MSB) DB0 (LSB)

PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

0453

9-04

1

Figure 41. AD5620 Input Register Contents

DATA BITS


PD1 PD0 D11 D10D13 D12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0453

9-04

2


DATA BITS


PD1 PD0 D15 D14 D13 D12X X X X X X D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0453

9-04

3


0453

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4

DIN MSB MSB LSBLSB

INVALID WRITE SEQUENCE:SYNC HIGH BEFORE 16TH/24TH FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATESON THE 16TH/24TH FALLING EDGE

SYNC

SCLK

Figure 44. SYNC Interrupt Facility


Rev. G | of 28

POWER-ON RESET The AD5620/AD5640/AD5660 family contains a power-on reset circuit that controls the output voltage during power-up. The AD5620/AD5640/AD5660-1-2 DAC output powers up to 0 V, and the AD5620/AD5660-3 DAC output powers up to midscale. The output remains at this level until a valid write sequence is made to the DAC, which is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up.

POWER-DOWN MODES The AD5620/AD5640/AD5660 have four separate modes of operation. These modes are software-programmable by setting two bits in the control register. Table 7 and Table 8 show how the state of the bits corresponds to the operating mode of the device.

Table 7. Modes of Operation for the AD5660 DB17 DB16 AD5660 Operating Mode 0 0 Normal operation Power-down modes: 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state

Table 8. Modes of Operation for the AD5620/AD5640 DB15 DB14 AD5620/AD5640 Operating Mode 0 0 Normal operation Power-down modes: 0 1 1 kΩ to GND 1 0 100 kΩ to GND 1 1 Three-state

When both bits are set to 0, the part works normally with its normal power consumption of 550 µA at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V (200 nA at 3 V). Not only does the supply current fall, but the output stage is internally switched from the output of the amplifier to a resistor network of known values. The advan-tage is that the output impedance of the part is known while the part is in power-down mode. There are three options: the out-put is connected internally to GND through a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited (three-stated). The output stage is shown in Figure 45.

RESISTORNETWORK

VOUTRESISTOR

STRING DAC

0453

9-04

5

POWER-DOWNCIRCUITRY

AMPLIFIER

Figure 45. Output Stage During Power-Down

The bias generator, output amplifier, reference, resistor string, and other associated linear circuitry are all shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power-down is typically 5 µs for VDD = 5 V and VDD = 3 V (see Figure 31).

MICROPROCESSOR INTERFACING AD5660-to-Blackfin® ADSP-BF53x Interface

Figure 46 shows a serial interface between the AD5660 and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multi-processor communications. Using SPORT0 to connect to the AD5660, the setup for the interface is as follows: DT0PRI drives the DIN pin of the AD5660, while TSCLK0 drives the SCLK of the part and SYNC is driven from TFS0.

AD56601

1ADDITIONAL PINS OMITTED FOR CLARITY

TFS0

DTOPRI

TSCLK0

SYNC

DIN

SCLK

0453

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6

ADSP-BF53x1

Figure 46. AD5660-to-Blackfin ADSP-BF53x Interface


Rev. G | of 28

AD5660-to-68HC11/68L11 Interface

Figure 47 shows a serial interface between the AD5660 and the 68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives the SCLK of AD5660, and the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: The 68HC11/68L11 should be con-figured so that its CPOL bit is 0, and its CPHA bit is 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured in this way, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5660, PC7 is left low after the first eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at the end of this procedure.

AD56601


PC7

SCK

MOSI

SYNC

SCLK

DIN

0453

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7

68HC11/68L111

Figure 47. AD5660-to-68HC11/68L11 Interface

AD5660-to-80C51/80L51 Interface

Figure 48 shows a serial interface between the AD5660 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5660, and RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case, Port Line P3.3 is used. When data is to be transmitted to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit

data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 output the serial data LSB first; however, the AD5660 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.

80C51/80L511 AD56601

P3.3

TxD

RxD

SYNC

SCLK

DIN

0453

9-04

8


Figure 48. AD5660-to-80C51/80L51 Interface

AD5660-to-MICROWIRE Interface

Figure 49 shows an interface between the AD5660 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the AD5660 on the rising edge of the SK.

MICROWIRE1 AD56601

CS

SK

SO

SYNC

SCLK

DIN

0453

9-04

9


Figure 49. AD5660-to-MICROWIRE Interface


Rev. G | of 28

APPLICATIONS INFORMATION USING A REF19x AS A POWER SUPPLY FOR THE AD5620/AD5640/AD5660 Because the supply current required by the AD5620/AD5640/ AD5660 is extremely low, an alternative option is to use a REF19x voltage reference (REF195 for 5 V or REF193 for 3 V) to supply the required voltage to the part (see Figure 50). This is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The REF19x outputs a steady supply voltage for the AD5620/ AD5640/AD5660. If the low dropout REF195 is used, the current it needs to supply to the AD5660 is 500 µA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF195 also must supply the current to the load. The total current required (with a 5 kΩ load on the DAC output) is

500 µA + (5 V/5 kΩ) = 1.5 mA

The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 3 ppm (15 µV) for the 1.5 mA current drawn from it. This corresponds to a 0.197 LSB error for the AD5660.

AD56603-WIRESERIAL

INTERFACE

SYNCSCLK

DIN

15V

5V

VOUT = 0V TO 5V

REF195

0453

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0

Figure 50. REF195 as the Power Supply to the AD5660

BIPOLAR OPERATION USING THE AD5660 The AD5660 is designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 51. Figure 51 gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier.

The output voltage for any input code can be calculated as

×−

+

×

×=

R1R2

VR1

R2R1DVV DDDDO 65536

where D represents the input code in decimal (0 to 65535).

When VDD = 5 V, R1 = R2 = 10 kΩ,

V56553610

−

×

=D

VO

This results in an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output and 0xFFFF corresponding to a +5 V output.

R210kΩ

0453

9-05

1

+5V

–5V

AD820/OP295

3-WIRESERIAL

INTERFACE

+5V

AD5660VDD

VFBVOUT

R110kΩ

±5V

0.1µF10µF

Figure 51. Bipolar Operation with the AD5660


Rev. G | of 28

0453

9-05

2

SERIALLOAD AD5660

VLOOP12V TO 36V

4–20mA

AD8627R14.7kΩ

R218.5kΩ

P120mA

ADJUST

P24mA

ADJUST

R63.3kΩ

R31.5kΩ

D1

Q12N3904

R7100Ω

RL

ADR02

Figure 52. Programmable 4 mA to 20 mA Process Controller

USING THE AD5660 AS AN ISOLATED, PROGRAMMABLE, 4 mA TO 20 mA PROCESS CONTROLLER In many process-control system applications, 2-wire current transmitters are used to transmit analog signals through noisy environments. These current transmitters use a zero-scale signal current of 4 mA to power the signal conditioning circuitry of the transmitter. The full-scale output signal in these transmitters is 20 mA. The converse approach to process control can also be used, in which a low-power, programmable current source is used to control remotely located sensors or devices in the loop.

A circuit that performs this function is shown in Figure 52. Using the AD5660 as the controller, the circuit provides a programmable output current of 4 to 20 mA, proportional to the digital code of the DAC. Biasing for the controller is provided by the ADR02 and requires no external trim for two reasons: first, the ADR02’s tight initial output voltage tolerance, and second, the low supply current consumption of both the AD8627 and the AD5660. The entire circuit, including optocouplers, consumes less than 3 mA from the total budget of 4 mA. The AD8627 regulates the output current to satisfy the current summation at the noninverting node of the AD8627.

IOUT = 1/R7 (VDAC × R3/R1 + VREF × R3/R2)

For the values shown in Figure 52,

IOUT = 0.2435 µA × D + 4 mA

where D = 0 ≤ D ≤ 65,535, giving a full-scale output current of 20 mA when the AD5660’s digital code equals 0xFFFF. Offset trim at 4 mA is provided by P2, and P1 provides the circuit gain trim at 20 mA. These two trims do not interact because the noninverting input of the AD8627 is at virtual ground. The Schottky diode, D1, is required in this circuit to prevent loop supply power-on transients from pulling the noninverting input of the AD8627 more than 300 mV below its inverting input.

Without this diode, such transients could cause phase reversal of the AD8627 and possible latch-up of the controller. The loop supply voltage compliance of the circuit is limited by the maximum applied input voltage to the ADR02 and is from 12 V to 40 V.

USING THE AD5620/AD5640/AD5660 WITH A GALVANICALLY ISOLATED INTERFACE For process-control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from hazardous common-mode voltages that might occur in the area where the DAC is functioning. The iCoupler® provides isolation in excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire serial logic interface; therefore, the ADuM1300 3-channel digital isolator provides the required isolation (see Figure 53). The power supply to the part also must be isolated, which is done by using a transformer. On the DAC side of the trans-former, a 5 V regulator provides the 5 V supply required for the AD5620/AD5640/AD5660.

0.1µF

5VREGULATOR

GND

0453

9-05

3

DIN

SYNC

SCLK

POWER 10µF

SDI

SCLK

DATA

AD56x0

VOUTVOB

VOA

VOC

VDD

V1C

V1B

V1A

ADuM1300

Figure 53. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface


Rev. G | of 28

POWER SUPPLY BYPASSING AND GROUNDING When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD5620/ AD5640/AD5660 should have separate analog and digital sections, each having its own area of the board. If the AD5620/ AD5640/AD5660 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD5620/AD5640/AD5660.

The power supply to the AD5620/AD5640/AD5660 should be bypassed with 10 µF and 0.1 µF capacitors. The capacitors should be as close as physically possible to the device, with the 0.1 µF capacitor ideally right up against the device. The 10 µF capacitors are the tantalum bead type. It is important that the 0.1 µF capacitor has a low effective series resistance (ESR) and low effective series inductance (ESI), such as is typical of common ceramic types of capacitors. This 0.1 µF capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching.

The power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. Clocks and other components with fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. The best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board.


Rev. G | of 28

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-178-BA

8°4°0°

SEATINGPLANE

1.95BSC

0.65 BSC

0.60BSC

7 6

1 2 3 4

5

3.002.902.80

3.002.802.60

1.701.601.50

1.301.150.90

0.15 MAX0.05 MIN

1.45 MAX0.95 MIN

0.22 MAX0.08 MIN

0.38 MAX0.22 MIN

0.600.450.30

PIN 1INDICATOR

8

12-1

6-20

08-A

Figure 54. 8-Lead Small Outline Transistor Package [SOT-23]

(RJ-8) Dimensions shown in millimeters

COMPLIANT TO JEDEC STANDARDS MO-187-AA

6°0°

0.800.550.40

4

8

1

5

0.65 BSC

0.400.25

1.10 MAX

3.203.002.80

COPLANARITY0.10

0.230.09

3.203.002.80

5.154.904.65

PIN 1IDENTIFIER

15° MAX0.950.850.75

0.150.05

10-0

7-20

09-B

Figure 55. 8-Lead Mini Small Outline Package [MSOP]

(RM-8) Dimensions shown in millimeters


Rev. G | of 28

TOP VIEW

8

1

5

4

0.350.300.25

BOTTOM VIEW

PIN 1 INDEXAREA

SEATINGPLANE

0.800.750.70

0.203 REF

0.05 MAX0.00 MIN

0.65 BSC

1.95 REF3.103.00 SQ2.90

COPLANARITY0.08

0.500.400.30

COMPLIANT TOJEDEC STANDARDS MO-229-WEEC-2 02-2

3-20

11-A

PIN 1 CORNERC 0.130× 45°

Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-8-15)

Dimensions shown in millimeters


Rev. G | of 28

ORDERING GUIDE

Model1 Temperature Range

Package Description

Package Option Branding

Power-On Reset to Code Accuracy

Internal Reference

AD5620ARJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6V Zero ±6 LSB INL 1.25 V AD5620ARJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2L Zero ±6 LSB INL 2.5 V AD5620ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5D Zero ±6 LSB INL 2.5 V AD5620ARJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2L Zero ±6 LSB INL 2.5 V AD5620ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5D Zero ±6 LSB INL 2.5 V AD5620ARMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DGY Zero ±6 LSB INL 2.5 V AD5620ARMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGY Zero ±6 LSB INL 2.5 V AD5620BCPZ-1500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DL9 Zero ±6 LSB INL 1.5 V AD5620BCPZ-1RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DL9 Zero ±6 LSB INL 1.5 V AD5620BCPZ-2500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLC Zero ±6 LSB INL 2.5 V AD5620BCPZ-2RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLC Zero ±6 LSB INL 2.5 V AD5620BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2H Zero ±1 LSB INL 1.25 V AD5620BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D87 Zero ±1 LSB INL 1.25 V AD5620BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2H Zero ±1 LSB INL 1.25 V AD5620BRJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2J Zero ±1 LSB INL 2.5 V AD5620BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5C Zero ±1 LSB INL 2.5 V AD5620BRJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2J Zero ±1 LSB INL 2.5 V AD5620BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5C Zero ±1 LSB INL 2.5 V AD5620CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D2M Zero ±1 LSB INL 1.25 V AD5620CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DGM Zero ±1 LSB INL 1.25 V AD5620CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2M Zero ±1 LSB INL 1.25 V AD5620CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGM Zero ±1 LSB INL 1.25 V AD5620CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D2N Zero ±1 LSB INL 2.5 V AD5620CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2N Zero ±1 LSB INL 2.5 V AD5620CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 D59 Zero ±1 LSB INL 2.5 V AD5620CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D59 Zero ±1 LSB INL 2.5 V AD5620CRM-3 −40°C to +105°C 8-Lead MSOP RM-8 D2P Midscale ±1 LSB INL 2.5 V AD5620CRMZ-3 −40°C to +105°C 8-Lead MSOP RM-8 DGN Midscale ±1 LSB INL 2.5 V AD5620CRMZ-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DGN Midscale ±1 LSB INL 2.5 V EVAL-AD5620EBZ Evaluation Board

AD5640ARJ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2T Zero ±8 LSB INL 2.5 V AD5640ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC6 Zero ±8 LSB INL 2.5 V AD5640ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC6 Zero ±8 LSB INL 2.5 V AD5640BCPZ-1500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLV Zero ±4 LSB INL 1.25 V AD5640BCPZ-1RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLV Zero ±4 LSB INL 1.25 V AD5640BCPZ-2500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLW Zero ±4 LSB INL 2.5 V AD5640BCPZ-2RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLW Zero ±4 LSB INL 2.5 V AD5640BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Q Zero ±4 LSB INL 1.25 V AD5640BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC3 Zero ±4 LSB INL 1.25 V AD5640BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Q Zero ±4 LSB INL 1.25 V AD5640BRJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC3 Zero ±4 LSB INL 1.25 V AD5640BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC0 Zero ±4 LSB INL 2.5 V AD5640BRJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2R Zero ±4 LSB INL 2.5 V AD5640BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DC0 Zero ±4 LSB INL 2.5 V AD5640CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D2U Zero ±4 LSB INL 1.25 V AD5640CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2U Zero ±4 LSB INL 1.25 V AD5640CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DG1 Zero ±4 LSB INL 1.25 V AD5640CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DG1 Zero ±4 LSB INL 1.25 V AD5640CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D2V Zero ±4 LSB INL 2.5 V AD5640CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D2V Zero ±4 LSB INL 2.5 V AD5640CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DEW Zero ±4 LSB INL 2.5 V AD5640CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEW Zero ±4 LSB INL 2.5 V


Rev. G | of 28

Model1 Temperature Range

Package Description

Package Option Branding

Power-On Reset to Code Accuracy

Internal Reference

AD5660ACPZ-1500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLM Zero ±32 LSB INL 1.25 V AD5660ACPZ-1RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLM Zero ±32 LSB INL 1.25 V AD5660ACPZ-2500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLX Zero ±32 LSB INL 2.5 V AD5660ACPZ-2RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLX Zero ±32 LSB INL 2.5 V AD5660ACPZ-3500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLY Midscale ±32 LSB INL 2.5 V AD5660ACPZ-3RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLY Midscale ±32 LSB INL 2.5 V AD5660ARJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D30 Zero ±32 LSB INL 1.25 V AD5660ARJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5G Zero ±32 LSB INL 1.25 V AD5660ARJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D30 Zero ±32 LSB INL 1.25 V AD5660ARJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D5G Zero ±32 LSB INL 1.25 V AD5660ARJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6K Zero ±32 LSB INL 2.5 V AD5660ARJ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D31 Zero ±32 LSB INL 2.5 V AD5660ARJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6K Zero ±32 LSB INL 2.5 V AD5660ARJ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D32 Midscale ±32 LSB INL 2.5 V AD5660ARJZ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAV Midscale ±32 LSB INL 2.5 V AD5660ARJ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D32 Midscale ±32 LSB INL 2.5 V AD5660ARJZ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAV Midscale ±32 LSB INL 2.5 V AD5660BCPZ-1500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLZ Zero ±16 LSB INL 1.25 V AD5660BCPZ-1RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DLZ Zero ±16 LSB INL 1.25 V AD5660BCPZ-2500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DM0 Zero ±16 LSB INL 2.5 V AD5660BCPZ-2RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DM0 Zero ±16 LSB INL 2.5 V AD5660BCPZ-3500RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DM1 Midscale ±16 LSB INL 2.5 V AD5660BCPZ-3RL7 −40°C to +105°C 8-Lead LFCSP_WD CP-8-15 DM1 Midscale ±16 LSB INL 2.5 V AD5660BRJ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2X Zero ±16 LSB INL 1.25 V AD5660BRJZ-1500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6C Zero ±16 LSB INL 1.25 V AD5660BRJ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2X Zero ±16 LSB INL 1.25 V AD5660BRJZ-1REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6C Zero ±16 LSB INL 1.25 V AD5660BRJZ-2500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6L Zero ±16 LSB INL 2.5 V AD5660BRJZ-2REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D6L Zero ±16 LSB INL 2.5 V AD5660BRJ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Z Midscale ±16 LSB INL 2.5 V AD5660BRJZ-3500RL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAN Midscale ±16 LSB INL 2.5 V AD5660BRJ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 D2Z Midscale ±16 LSB INL 2.5 V AD5660BRJZ-3REEL7 −40°C to +105°C 8-Lead SOT-23 RJ-8 DAN Midscale ±16 LSB INL 2.5 V AD5660CRM-1 −40°C to +105°C 8-Lead MSOP RM-8 D33 Zero ±16 LSB INL 1.25 V AD5660CRM-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D33 Zero ±16 LSB INL 1.25 V AD5660CRMZ-1 −40°C to +105°C 8-Lead MSOP RM-8 DEX Zero ±16 LSB INL 1.25 V AD5660CRMZ-1REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEX Zero ±16 LSB INL 1.25 V AD5660CRM-2 −40°C to +105°C 8-Lead MSOP RM-8 D34 Zero ±16 LSB INL 2.5 V AD5660CRM-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D34 Zero ±16 LSB INL 2.5 V AD5660CRMZ-2 −40°C to +105°C 8-Lead MSOP RM-8 DEY Zero ±16 LSB INL 2.5 V AD5660CRMZ-2REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DEY Zero ±16 LSB INL 2.5 V AD5660CRM-3 −40°C to +105°C 8-Lead MSOP RM-8 D35 Midscale ±16 LSB INL 2.5 V AD5660CRM-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 D35 Midscale ±16 LSB INL 2.5 V AD5660CRMZ-3 −40°C to +105°C 8-Lead MSOP RM-8 DBY Midscale ±16 LSB INL 2.5 V AD5660CRMZ-3REEL7 −40°C to +105°C 8-Lead MSOP RM-8 DBY Midscale ±16 LSB INL 2.5 V EVAL-AD5660EBZ Evaluation Board 1 Z = RoHS Compliant Part.

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