final exam of coa

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UNIVERSITY OF GONDAR FACULTY OF TECHNOLOGY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING Date: 09/07/2007 Time allowed: 3:00 Computer Architecture and Organization Final Exam 1.A register transfer operation can be represneted uisng a control function. Control function is composed of two parts, control variables and register transfer operation. For example the statement P: R 2 R 1 denotes the transfer of contents of register R 1 inot R 2 while content of R 2 are replaced by contets of R 1 but R 1 remains intact. By the above statement we mean that the trnasfer of contents of register R 1 to R 2 happens only if only P=1. This implies that P is control signal that determines the transfer to happen. It is assumed that the control variable is synchronized with the same clock as one applied to the registers.The block digram of the above control function can be represneted as follows Fig: block diagram for Transfer from R 1 to R 2 when P = 1; Question: Show the block diagram of the hardware (similar to the figure above) that implements the following register transfer statement yT 2 : R2R 1 , R1R 2 (5 pts) 2. A digital computer has a common bus system for 8 registers of 8 bits each. The bus is constructed with multiplexers. (8 pts) a. How many selection inputs are there in each multiplexer? b. What size of multiplexers are needed? C. How many multiplexers are there in the bus? d. Draw your bus system

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  • UNIVERSITY OF GONDAR

    FACULTY OF TECHNOLOGY

    DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

    Date: 09/07/2007 Time allowed: 3:00

    Computer Architecture and Organization Final Exam

    1.A register transfer operation can be represneted uisng a control function. Control function is composed

    of two parts, control variables and register transfer operation. For example the statement

    P: R2 R1

    denotes the transfer of contents of register R1 inot R2 while content of R2 are replaced by contets of R1

    but R1 remains intact. By the above statement we mean that the trnasfer of contents of register R1 to R2

    happens only if only P=1. This implies that P is control signal that determines the transfer to happen.

    It is assumed that the control variable is synchronized with the same clock as one applied to the

    registers.The block digram of the above control function can be represneted as follows

    Fig: block diagram for Transfer from R1 to R2 when P = 1;

    Question: Show the block diagram of the hardware (similar to the figure above) that implements the

    following register transfer statement

    yT2: R2 R1, R1 R2 (5 pts)

    2. A digital computer has a common bus system for 8 registers of 8 bits each. The bus is constructed with

    multiplexers. (8 pts)

    a. How many selection inputs are there in each multiplexer?

    b. What size of multiplexers are needed?

    C. How many multiplexers are there in the bus?

    d. Draw your bus system

  • UNIVERSITY OF GONDAR

    FACULTY OF TECHNOLOGY

    DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 3. A computer uses a memory unit with 256k words of 32 bits each. A binary instruction code is stored in

    one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code

    part to specify one of 64 registers, and an address part. (8 pts)

    a. how many bits are there in the operation code, the register code part and the address part?

    b. Draw the instruction word format and indicate the number of bits in each part.

    c. How many bits are there in the data and address inputs of the memory?

    4. The following program is stored in the memory unit of the basic computer. Show the contents of the

    AC,PC, and IR (in hexa decimal), at the end , after each instruction is executed. All numbers listed

    below are in hexa decimal. (6 pts)

    5. a) Explain the difference between hardwired control and microprogrammed control. Is it possible to

    have hardwired control associated with a control memory.(3 pts)

    b) Define the following: (I) micropoperation; (II) microinstruction; (III) microprogram;

    (IV) microcode ( 4 pts )

    6. In certain scientific computations it is necessary to perform the arithmetic operation (Ai+Bi)(Ci+Di)

    with a stream of numbers. Specify a pipeline configuration (Block diagram) to carry out this task. List

    the contents of all registers in the pipeline for i= 1 through 6. (10 pts)

    7. a)How many 128 X 8 RAM chips are needed to provide a memory capacity of 2048 bytes?

    b) How many lines of the address bus must be used to access 2048 bytes of memory? How many of

    these lines will be common to all chips?

    c) How many lines must be decoded for chip select? Specify the size of the decoders.

    (Each 2 points)

  • UNIVERSITY OF GONDAR

    FACULTY OF TECHNOLOGY

    DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING