final presenation slide

8/13/2019 Final Presenation Slide

1/36

Guided by: Presented by:

Mr. Dheeraj Jain Arushi SomaniAsst. Prof. M.Tech VLSI

I.T.M., Bhilwara Enrol. No.: 10E2IMVLF4XT604


2/36

CONTENTS

Introduction Literature Survey

Objective

Multiplier Types

Hierarchical Array Multiplier (HAM)

Adders

Modified Booth Multiplier (MBM)

Vedic Mathematics (VM)

Results

Conclusion Future Work

References

Paper Published

Acknowledgement


3/36

INTRODUCTION

Multiplier is an arithmetic circuit that is extensively used in

DSP, microprocessors and communication applications.

Multiplication algorithms differ in the means of partial product

generation and addition to produce the final result.

Many multiplication algorithms are available like Array,

Modified Booth, Wallace Tree, Dadda etc.

The main objective of this dissertation is to design and

implement most efficient multiplier on various performance

factors like power, speed, and area.


4/36

LITERATURE SURVEY

Many researchers published various research papers based onthe comparative study of multipliers (Conventional and Vedic)on various performance factors like speed, power, delay andarea.

This survey highlights the pros and cons of various multiplier

techniques like array multiplier to Wallace tree, boothmultipliers, hierarchical array of array multiplier and Vedicmultiplier based on already published research papers.

There are two possible ways to speed up the multiplication

Reducing number of partial products.Accelerating the accumulation process.


5/36

OBJECTIVE

The core objective to find out most efficient multiplier is dividedinto 4 sub studies. All multipliers have been implemented on180nm CMOS technology using tanner tool.

Design and implementation of hierarchical array multiplier(HAM) using six different types of adders and modified booth

multiplier with different bit widths for analysis power, delayand area.

Design and implementation of U.T. type 1 and U.T. type 2multipliers based on Urdhva Tiryagbhyam algorithm of Vedicmathematics on different bit widths.

Comparative study of all implemented multipliers on variousperformance factors like power, speed, delay and size.

Design and implementation of most efficient multiplier usingNikhilam sutra.


6/36

MULTIPLIERS TYPES

Hierarchical Array Multiplier(HAM)

Modified Booth Multiplier(MBM)

Vedic Multiplier (VM)


7/36

EXAMPLE OF HIERARCHICAL ARRAY MULTIPLIER(HAM)

Binary multiplication of 1011 1011


8/36

HIERARCHICAL ARRAY MULTIPLIER

Hierarchical Array Multiplier (a) Block Diagram (b) Schematic Block Diagram


9/36

ADDERS

Ripple Carry Adder (RCA)

Carry Lookahead Adder(CLA)

Carry Select Adder(CSLA)

Carry Skip Adder(CSKA)


10/36

RIPPLE CARRY ADDER (RCA)

4 bit Ripple Carry Adder (a) Block Diagram (b) Schematic Block

Diagram

(b)(a)


11/36

FULL ADDER (FA)

Schematic Block Diagram of 1 bit FA using (a) Mirror Full Adder (b)

transmission gate type 1 (c) transmission gate type 2

(a) (b)

(c)


12/36

CARRY LOOKAHEAD ADDER (CLA)

4 bit carry lookahead adder (a) Block Diagram (b) Schematic Block

Diagram

(b)(a)


13/36

CARRY SELECT ADDER (CSLA)

(a)

Carry Select adder (a) Block Diagram (b) Schematic Block Diagram

(b)


14/36

CARRY SKIP ADDER (CSKA)

(a)

Carry Skip Adder (a) Block Diagram (b) Schematic Block Diagram

(b)


15/36

RESULTS OF 16 BIT HAM WITH DIFFERENT

ADDERS

S.

No.

Adder Power

(mW)

Delay

(ns)

PDP

(pJ)

EDP

(10-21Js)

Transistor Simulation

Time(Sec)

1 RCA 5.79 24.58 142.32 3498.18 15776 315.42

2 CLA 15.91 22.72 361.48 8212.72 35312 759.16

3 CSLA 12.92 23.28 300.78 7002.10 29144 644.58

4 CSKA 13.42 24.29 325.97 7917.86 18224 462.65

5 TG type 1 14.85 23.42 347.79 8145.17 16656 393.45

6 TG type 2 14.45 23.59 340.88 8041.25 18416 378.1


16/36

MODIFIED BOOTH MULTIPLIER (MBM)

Modified Booth Multiplier (a) Block Diagram (b) Schematic Block

Diagram

(a) (b)


17/36

VEDIC MATHEMATICS

The Vedic mathematics (VM) is part of four Vedas. VMprovides techniques to solve operations with large magnitude

of numbers easily.

It covers explanation of several modern mathematical terms

including arithmetic, trigonometry, plain, calculus, quadraticequations, factorization and spherical geometry.

Various methods of multiplication proposed in VM are

Urdhva Tiryagbhyam Vertically and crosswise.

Nikhilam sutra All from nine and last from ten.


18/36

URDHVA TRIYAGBHYAM (U.T.) MULTIPLIER

"Urdhva" and "Tiryagbhyam" words are derived from Sanskrit

literature. Urdhva means "Vertically" and Tiryagbhyam means

"crosswise".

It is based on a novel concept, where the generation of all

partial products can be done with the concurrent addition ofpartial products.


19/36

EXAMPLE OF URDHVA TIRYAGBHYAM MULTIPLIER

Multiplication of 232 323=74936 by Urdhva Tiryagbhyam multiplier

with line diagram

Line diagram Multiplication of 232323=74936


20/36

URDHVA TIRYAGBHYAM TYPE 1

(a)Urdhva Tiryagbhyam type 1 (a) Block Diagram (b) Schematic Block

Diagram

(b)


21/36

URDHVA TIRYAGBHYAM TYPE 2

(a)

Urdhva Tiryagbhyam type 2 (a) Block Diagram (b) Schematic Block

Diagram

(b)


22/36

COMPARISON OF 16 BIT MULTIPLIERS

16 16 bit Multipliers

S.

No.

Multiplier Power

(mW)

Delay

(ns)

PDP

(pJ)

EDP

(10-21Js)


time(Sec)

1 MBM 275.37 25.09 6909.03 173374.64 20780 697.38

2 HAM 5.79 24.58 142.32 3498.18 15776 315.42

3 U.T. type 1 4.6 22.58 103.87 2345.34 12864 249.91

4

U.T. type 2

4.12

18.52

76.30

1413.12

11674

217.96


23/36

0

20

40

60

80

100

120

140

160

8 bit 16 bit

Power(mw)

No. of Bits

Comparison of avg. power in different

multiplier

HAM

U.T Type 1

U.T Type 2

0

500

1000

1500

2000

2500

3000

3500

8 bit 16 bit

Delay(ns)

No. of Bits

Comparison of delay in different multiplier

HAM

U.T Type 1

U.T Type 2

SUMMARIZED RESULTS


24/36

0

20

40

60

80

100

120

140

160

8 bit 16 bit

PD

P

No. of Bits

Comparison of PDP in different multiplier

HAM

U.T Type 1

U.T Type 2

0

500

1000

1500

2000

2500

3000

3500

8 bit 16 bit

ED

P

No. of Bits

Comparison of EDP in different multiplier

HAM

U.T Type 1

U.T Type 2

SUMMARIZED RESULTS


25/36

(a)

(b)

(c)

(d)

Output of 16 bit Multiplier (a) Modified Booth (b) U.T. type 1 (c) U.T. type 2(d) HAM

OUTPUT OF MULTIPLIERS


26/36

NIKHILAM SUTRA (N.S.) MULTIPLIER

Urdhva Tiryagbhyam multiplier suffer from a high carrypropagation delay in case of large multiplication. This problem

can be solved by Nikhilam sutra which converts multiplication

of large numbers into small numbers.

Nikhilam sutra literally means all from 9 and last from 10.Although it is applicable to all cases of multiplication.


27/36

EXAMPLE OF NIKHILAM SUTRA MULTIPLIER

Multiplication Using Nikhilam Sutra


28/36

NIKHILAM SUTRA MULTIPLIER

(b)16 bit Nikhilam Sutra Multiplier (a) Block Diagram (b) Schematic

Block Diagram

(a)


29/36

16 16 bit Multiplier

S.

No.

Multiplier Power

(mW)

Delay

(ns)

PDP

(pJ)

EDP

(10-21Js)


time(Sec)

1 N.S. type1

( Both RCA)

1.12 15.44 17.29 267.00 13530 144.58

2 N.S. type 2

(RCA & CSLA)

1.16 15.00 17.40 261.00 13926 170.45

3 N.S. type 3

(Both CSLA)

1.24 14.93 18.51 276.40 14322 168.78

4 N.S. type 4

(CSLA & RCA)

1.19 15.30 18.21 278.57 13926 161.02

RESULTS OF 16 BIT N.S. MULTIPLIER WITH

DIFFERENT ADDERS


30/36

Output of 16 16 bit Nikhilam sutra multiplier (a) type 1 (b) type 2 (c)

type 3 (d) type 4

(a)

(b)

(c)

(d)

OUTPUT OF 16 BIT N.S. MULTIPLIER


31/36

CONCLUSION

It has been concluded that N.S. type 1 multiplier is best interms of power, power delay product (PDP) and energy delay

product (EDP) and N.S. type 3 is found to be most efficient in

terms of speed but required largest area compare to others.

After comparison of 16 bit U.T. type 2 with Nikhilam sutramultiplier. The power and PDP in N.S. type 1 multiplier is

reduced by 72.81% and 77.33% respectively and delay in N.S.

type 3 multiplier is reduced by 19.38%.


32/36

LIMITATIONS

Nikhilam sutra performs best among all multipliers. Butstill it has some limitations, which are

Both the multiplier and multiplicand should be less or

greater than the base. Multiplier and multiplicand should be near to the

base.


33/36

FUTURE WORK

One possible direction is to reduce the number of partial

products and other is optimisation of the various components

used in the design.

If all those methods effectively implemented on hardware then

it will reduce the computational speed drastically. It could be possible to implement a complete ALU and a math

coprocessor using Vedic mathematics.


34/36

REFERENCES

[1]Sumit Vaidya, Deepak Dandekar, Delay-Power performance

comparison of multipliers in VLSI circuit design,

International Journal of Computer Networks &

Communications (IJCNC), Vol.2, No.4, pp. 47-56, Jul. 2010.

[2]Abhijit Asati, Chandrashekhar, A High-Speed, Hierarchical

1616 Array of Array Multiplier Design, InternationalConference on Multimedia, Signal processing and

Communication Technologies (IMPACT), pp. 161-164, Mar.

2009.

[3]Shamim Akhter, VHDL implementation of fast NNmultiplier based on Vedic mathematic, 18th European

Conference on Circuit Theory and Design, Sevilla Spain, pp.

472-475, Aug. 2007.

[4] More references


35/36


36/36

ACKNOWLEDGEMENT

I would like to express my sincere gratitude to Mr. Dheeraj Jain

for his valuable guidance.

I Further extend my thanks to Ms. Kumkum Verma and Mr.

Sanjay Jaiswal for their support.

I also would thank Dr. N. K. Mathur for his motivation.

Last but not least I would like to thank my colleagues, friends

and my parents for their valuable support.

final presenation slide

Documents