final project - utep · final project prof. macdonald . project!! sram simulation schematic for...
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![Page 1: final project - UTEP · Final Project Prof. MacDonald . Project!! SRAM simulation schematic for undergrads ! DRAM for grads but with SRAM structure and DRAM bit cell ! No write circuitry](https://reader033.vdocument.in/reader033/viewer/2022042917/5f5b7586bce68129463c1ece/html5/thumbnails/1.jpg)
Final Project
Prof. MacDonald
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Project!l SRAM simulation schematic for undergrads
l DRAM for grads but with SRAM structure and DRAM bit cell
l No write circuitry or refresh circuitry – use Initial conditions to program.
l Must have worst and best case timing cases
l Upper right for worst case word and bit line distances
l Lower left for best case word and bit line distances
l Need dummy loads and 1 ohm resistors on bit and word lines
![Page 3: final project - UTEP · Final Project Prof. MacDonald . Project!! SRAM simulation schematic for undergrads ! DRAM for grads but with SRAM structure and DRAM bit cell ! No write circuitry](https://reader033.vdocument.in/reader033/viewer/2022042917/5f5b7586bce68129463c1ece/html5/thumbnails/3.jpg)
SRAM Interface !!l Dirt simple
– clk – only required if registered inputs and/or outputs
– Cen – usually negatively active chip select
– wen – usually negatively active write enable = NOT USED
– a – address bus – logarithmically related to number of locations
– d – data in bus – inputs used during writes – ONE BIT IN THIS CASE
– q – data out bus – outputs used during reads – NOT USED
l read – csn active / wen inactive – data in the byte located by A bus launches out Q bus
l write – csn active / wen active – D bus value is loaded into memory location determined by A
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Static Memory Cell!
T1!
True!Bit!Line!
Complement!Bit!Line!
Wordline!
T2!
T5!
T3!
T6!
T4!
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DRAM Cross Section
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Random Access Memory (RAM)
wordline
bitline bitlineN
6 Transistor SRAM cell
n+c
m
sram array of 6-t cells n to 2n decoder
2n
Address input
word lines
m rnw
data in data out
peripheral circuits – column mux, sense amps, write circuitry
n
c
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SRAM Array for sim schematic bl73 bl00
Fast Cell
bl73b
Slow Cell
bl00b
wl0
wl31
Same for DRAM except bit bar will come from a dummy cell on the other side of the sense amp. In this case bit bar is precharged to half vdd and held by a 32x dummy load.
![Page 8: final project - UTEP · Final Project Prof. MacDonald . Project!! SRAM simulation schematic for undergrads ! DRAM for grads but with SRAM structure and DRAM bit cell ! No write circuitry](https://reader033.vdocument.in/reader033/viewer/2022042917/5f5b7586bce68129463c1ece/html5/thumbnails/8.jpg)
DRAM organization and internal circuits
1/2 Vdd
1/2 Vdd
SAEN
SAE
1/2 Vdd
1/2 Vdd
LDWL LWL0 LWL1 RDWL RWL1 RWL0
PCH PCH
1/2 Vdd
1/2 Vdd
1/2 Vdd
1/2 Vdd 1/2
Vdd 1/2 Vdd
right dummy cell
left dummy cell
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SRAM Organization!!l Blocks with unity aspect ratio
l Rows
l Columns
l IO
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SRAM Read Cross-Section!TSA!
CSA!Set!Sense!Amp! Bit !
Line !Isolation!
Bit !Line!Precharge!
Isolation Circuit!
Precharge ! Circuit!
Cell!
T!TBL! CBL!
Wordline!
Isolation is not used for DRAM as you need to refresh the cell contents after the read.
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SRAM Isolation & Pre-charge Circuits!
Bit !Line !Isolation!
Bit Switch Circuit!
Pre-charge ! Circuit!Bit !Line !Pre-charge!
Cells!
Sense Amp! Isolation is not used for DRAM as you need to refresh the cell contents after the read.
Additionally the DRAM precharge should be to half Vdd.
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SRAM Sense Amplifier Circuit!
TSA!
CSA!
Set!Sense!Amp!
Bit Switch!
As DRAMs are precharged to half vdd, the SSA signal should choke not only ground but Vdd with a PFET.
SRAMs only need ground as the bit and bitbar are precharged to either Vdd or Vdd-Vt.
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SRAM Internal Memory Waveforms !Clock!
Word line!!!!Isolation!!Set Sense Amp!!!!Sense Amp Output!!!Data!
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SRAM Internal Memory Waveforms !
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SRAM Internal Memory Waveforms !
![Page 16: final project - UTEP · Final Project Prof. MacDonald . Project!! SRAM simulation schematic for undergrads ! DRAM for grads but with SRAM structure and DRAM bit cell ! No write circuitry](https://reader033.vdocument.in/reader033/viewer/2022042917/5f5b7586bce68129463c1ece/html5/thumbnails/16.jpg)
SRAM Internal Memory Waveforms !
![Page 17: final project - UTEP · Final Project Prof. MacDonald . Project!! SRAM simulation schematic for undergrads ! DRAM for grads but with SRAM structure and DRAM bit cell ! No write circuitry](https://reader033.vdocument.in/reader033/viewer/2022042917/5f5b7586bce68129463c1ece/html5/thumbnails/17.jpg)
DRAM Internal Memory Waveforms !