WARPAGE OF MICROELECTRONIC PACKAGES: FUNDAMENTALS AND CONTROL STRATEGIES

Neel Patel, Nithin Jacob, Seshadri Ramalingam School for Engineering of Matter, Transport and Energy

Arizona State University Tempe, USA

Nmpatel5@asu.edu, Nithin.Jacob@asu.edu, Seshadri.Ramalingam@asu.edu

Aditya Vaidya, Bharat Penmecha MCC, ATTD

Intel Corporation Chandler, USA

aditya.s.vaidya@intel.com, bharat.penmecha@intel.com

I. Abstract— As the trend in the microelectronics industry evolves towards reducing device and component thickness, warpage of electronic packages shall continue to be a pressing issue for chip makers and device manufacturers. In this report, the fundamental aspects of package warpage are examined through the Bimetallic strip theory (in 2D) and Finite Element simulations (in 3D). The key factors affecting the warpage are identified and are used to engineer warpage control solutions. The solutions are then employed to design a package with a certain warpage specification.

II. Index Terms—Glass Transition temperature, Warpage, Bimetallic Strip.

III. INTRODUCTION Advances in Silicon technology and organic substrate

technologies continues to drive the microelectronics industry. In accordance to the prediction of Moore’s law, density of 2D integrated circuits (IC) on silicon chips have doubled every 18-24 months in the past 30 to 40 years. However, as down-sizing silicon transistor size starts becoming economically challenging, new approaches to improving device performance are being explored. 3D packaging is one of the efforts along those lines. [1]

3D packaging technologies integrate memory die and application processor into a single package by stacking one on top of the other. This approach, known as Package-on-Package (PoP) technology, is gaining more acceptance and is now becoming mainstream. For a successful package on package assembly, the warpage of both top and bottom package are critical. A large warpage could lead to solder joint formation defects (opens and shorts), either between the processor package and the mother board or the memory and the processor package. For the successful assembly of a PoP package during the surface mounting process (SMT), studies have shown that warpage of the processor package at both the room (25 C) and the reflow temperatures (260 C) needs to meet a certain specification. So understanding warpage and engineering solutions to control it are of significant interest. This is the primary objective of this report.

First, factors influencing the warpage of a simple flip-chip package are studied. This is done first through the theory of bending of a bimetallic in two dimensions. Then a 3D finite

element (FE) model of a flip chip package on an organic susbtrate along with a DOE study is used to identify the key modulators of package warpage. The impact of temperature dependent properties of the materials which make up the package, especially the capillary underfill (CUF), and how they can be lead to reduced warpage in a package are analyzed. Then a design optimization is carried out for a package to meet the certain warpage and geometry specifications is carried out using constrained optimization techniques and FEM. Based on the findings, solutions to reduce warpage in a typical package are studied and two innovative solutions are proposed and analyzed to be possible solutions to reduce warpage in a PoP package [2].

IV. ORIGIN AND IMPACT OF WARPAGE Warpage is the out-of-plane (z-direction) deformation

exhibited by a package Different materials undergo dimensional changes at different rates when subject to a temperature change. This property is characterized by the coefficient of thermal expansion (CTE) of the material. An organic flip-chip package consists of materials of widely varying CTEs assembled together. For instance, in a flip chip ball grid array (FCBGA) package, the die is made of silicon is attached to a laminar organic substrate through solder joints and an epoxy underfill material is used for encapsulation. The mismatch in properties is huge with silicon having a CTE of 2.8 ppm/˚C and laminate substrate having CTE of approximately 18 ppm/˚C. During processing, assembly and service, when the package goes through temperature cycles, these materials expand or contract. But due to their inability to expand freely owing to the constraints they experience in the package, significant stresses are induced in a package. Warpage of the package is the resulting out-of plane displacement to relieve these stresses. Warpage at reflow conditions modulates the amount of collapse seen during the SMT process. High values of package warpage has a detrimental effect on the assembly yield at SMT due to the higher possibility of solder joint defects. The typical defects seen are bridging of adjacent joints resulting in leakage fails and no joint formation leading to resistance fails.

(a)

(b) Fig 1. SMT yield fails due to high warpage. (a) Non contacts, (b)

Solder bridging.

The high thermo mechanical stress due to the CTE

differences could lead to failures such as die. When it comes to Package-on-Package (POP) configuration, there are tight specifications on both the room and reflow temperature warpage numbers. It has been understood that the main challenge in assembly of POP packages is to control and match warpage of top and bottom packages. Interestingly, more than 90% of the defects in POP assemblies are due to warpage.

The following factors have been identified to contribute towards warpage of a FCBGA package

Die (i) Die size (ii) Die thickness (iii) Material property

Laminate substrate (i) Material Properties (ii) Thickness (iii) Average Copper (Cu) density (iv) Trace routing design

Warpage increases as the substrate becomes thinner. As mentioned earlier, mismatch in CTE of die, substrate play a major role in warpage issues. High Tg mold compounds are used to balance this mismatch between die and substrate.

Thinner and smaller die have been found to reduce warpage at room temperature when compared to larger, thicker die that tend to drive concave warpage at room temperature.

V. UNDERFILL STUDIES Underfill is an epoxy based material added between the die

and substrate in order to protect the solder joints connecting the Silicon chip to the substrate from the thermo mechanical stresses arising due to the CTE differences between the die and the substrate. Post cure, the underfill material establishes a strong coupling between the chip and the substrate. The underfill fills the gap between the chip and the substrate based on capillary action. The pre-cured underfill is expected to flow like water under the smallest gaps, well under 1 mil (<25 microns) for some of the flex-based packages. The cured underfill is expected to assume rock-hard, inorganic like properties, while bonding strongly to inorganic silicon and organic substrate.

The desired properties of an underfill are listed below Completely fill chip-board gap in seconds Absence of voids Conversion from easily flowable liquid to solid in few

minutes Excellent electrical insulation characteristic Low moisture absorption High thermal stability Low CTE

Fillers are generally used in polymers to reduce CTE and to increase its compatibility with silicon. However, the addition of excess filler particles increases the viscosity of the underfill which is not desirable for easy flow. The relation between the silica level and CTE, viscosity properties can be understood from figures 2 and 3 [3, 4].

Fig. 2. Silica level Vs CTE of the underfill

Fig. 3. Silica level Vs Viscosity of the underfill Glass transition temperature is another important character

of an underfill that needs to be considered. Most underfill’s display a Glass Transition Temperature (Tg) where a phase change occurs. Above the Tg. there is enough energy (increased molecular vibration energy) to allow the polymer chains to move slightly apart and gain additional degrees of freedom. The polymer cannot melt because the cross-links prevent the long polymer chains from slipping over one another thereby changing the bulk shape. As a result the polymer goes from a hard glassy state below Tg to a soft rubbery state above Tg. The added molecular motion also results in an increase in the CTE. The CTE above Tg, is 3 or 4 times higher than below it. This means that a well-designed underfill with a CTE of 20 – 25 ppm/C, displays an excessive expansion rate, up to 100

ppm/C above Tg. This higher CTE value would produce severe Z-axis strain on the joints leading to thermo mechanical failure. This is why the Tg value for most (but not all) underfills should be well above the intended use and test maximum temperature. A Tg of 150C or higher is considered adequate since use and testing is below that value for most systems. The cure temperature affects the Tg value. A general rule is that Tg will not be much higher than the maximum cure temperature. Since a higher cure temperature usually increases the Tg while reducing the cure time, the industry has attempted to push the maximum temperature [5]. The generally accepted maximum cure temperature for tin/lead eutectic solders is approximately 165C, a temperature that can be handled by the advanced substrate materials being used in Flip Chip applications. Hence in our Finite Element Studies, the initial temperature has been identified to be this 165C [5, 6].

VI. BIMETTALIC STRIP The bimetallic strip is a system of two metals with different

CTE (and usually Young’s modulus) bound together using a suitable bonding mechanism (riveting, brazing, welding etc.). The strip is flat at the bonding temperature. The thermo mechanical forces generated due to the different CTE results in the flat strip to bend one way if heated, and in the opposite direction if cooled below its initial temperature. [7].

Fig.4. A bimetallic strip

The curvature () of the strip bending in two dimensions can be calculated using the following formulae

(1) Where, Ex and hx are the Young’s Modulus and height of the Materials. is the misfit strain, calculated by: ϵ = (1 - 2) T (2) Where x is the Coefficient of Thermal Expansion of Materials. ΔT is the difference between the higher and lower temperatures.

It was found that warpage of the bimetallic strip obtained

was higher when the CTE mismatch between the materials is

higher. The higher the CTE mismatch, the higher the warpage obtained. This observation helped us in understanding the reasoning behind warpage seen in semiconductor packages and better comprehending some of the methods used to minimize the impact of this CTE mismatch between the die and substrate, in order to reduce package warpage.

VII. ANSYS ANALYSIS OF BIMETALLIC STRIP Finite element software, ANSYS is used to simulate the

bending of a 3D bimaterial coupon consisting of SS/Al, Al/Cu and Cu/SS couples. The thickness of the strip were 0.25 mm, 0.50mm and 1.00mm, with thickness ratio of the metals being a parity. The size of the strip was 5mm x 5mm. The strip was constrained at points A, B and C; such that all the rigid body modes of displacement are supressed. The mesh was refined to avoid mesh sensitivity and the element type was cubic, first order. The coupon is assumed to be flat initially, at 25C. The temperature of the coupon was ramped from 25 C to 200 C, the results are discussed below. A MATLAB code (Appendix) was used to compare the results with ANSYS solutions.

Fig.5. ANSYS setup of the strip The ANSYS and the MATLAB results show almost similar

nature of the plot when comparing the curvature generated due to the change in temperature of the system. In case of a Al/SS strip (Fig.6.) maximum out of plane displacement of 0.0375mm was observed.

This analysis laid the foundation for understanding the principle that dictates the warpage in a microelectronics package.

Fig.6. Al/SS bimetallic with thickness of 0.25mm at 200 C.

Fig.7. Comparing ANSYS results to the MATLAB results

The slopes of the plots were approximately similar, the change in deformation is due to the difference in the property assumptions and FEA errors

VIII. PACKAGE ANALYSIS SETUP With the knowledge gained through the bimetallic strip

warpage study, the next step in the project was to conduct a similar study on a semiconductor package. The two materials in the bimetallic strip would be replaced with silicon (Die) and BT Epoxy (Substrate). Epoxy underfill was used between the die and substrate simulating a real world package setup. The following image represents the schematic of the package set up used for our study.

Fig.8. Schematic of the package setup used for warpage

experimentation

All the required dimensions were treated as constants. The aim was to quantify warpage for a realtime package, so that the geometries could be optimized and methods for reducing warpage could be later be simulated. The following properties were assigned to the die, underfill and substrate.

Table I. Material Properties assigned for initial warpage

experimentation

Young’s Modulus (GPa)

CTE (ppm/ C)

Silicon (Die)

155.8

2.6

BT Epoxy (Substrate)

24.21

15

Epoxy (Underfill)

10

24

The ANSYS model was constrained using the same boundary condition as the bimetallic strip. The mesh was a hex dominant with element size as 0.125mm. Figure 9 shows the meshed ANSYS model used for the study.

Fig.9. Meshed package.

The intial temperature was assumed to be 165 C. This is the curing temperature for underfill which the package sees initially. The package is flat at this temperature. From this the package is assumed to be cooled down to room temperature (25 C). After this step, the temperature is raised to 260 C simulating an oven heating process, which is the most extreme temperature condition which the package is expected to see in the real world conditions. The warpage results obtained are listed in table 2.

Table 2. ANSYS results obtained for package warpage

Temperature © Package Out of Plane

Displacement (mm) 165 C 0 (Package is flat) 25 C 0.075051 mm

260 C 0.050928 mm The following figures show the package warpage at 25 C

and 260 C.

Fig.10. Package warpage at 25 C

.

Fig.11. Package warpage at 260 C

A similar study was later conducted using the Glass

transition temperature dependent material properties for the underfill. Results obtained before and after considering the glass transition temperature are discussed in the next section.

IX. EFFECT OF TEMPERATURE DEPENDENT PROPERTIES

The Glass transition temperature (Tg) can be defined as the temperature at which the transition in the amorphous regions between the glassy and rubbery state occurs [8]. At this stage of the project, an analysis was carried out on ANSYS to study the effect of Tg on the warpage of the microelectronics package. The ANSYS model used in section VIII was assigned properties as listed in table 3.

Table 3. Temperature Dependent Material Properties

Material Tg

(C)

Below Tg (C) Above Tg (C) Young’s Modulus (GPa)

CTE (ppm/ C)

Young’s Modulus (GPa)

CTE (ppm/ C)

Silicon (Die)

725

155.8

2.6

160.3

3.706

BT Epoxy (Substrate)

325

24.21

15

24.21

15

Epoxy (Underfill)

175

10

24

0.2

100

After assigning these temperature dependent properties, the

analysis was run once again with temperature steps as explained in section VIII.

There was a significant change observed in the warpage of the package at 260 C (Fig. 12). The warpage is reduced to 0.04035 mm. This is due to the fact that the softening of the epoxy at 175 C minimizes the coupling between the die and the substrate. This is shown in figure 12.

Fig.12.Package Warpage at 260C (Temp Dependent)

X. PARAMETRIC STUDIES The study of geometric parameters for the package

geometry considered is important in identifying the key contributors to warpage and can thus help in selecting the right package geometry to control package warpage. The geometric

parameters of importance are die thickness, die thickness and substrate size. Here a full factorial design is carried out to study the effect of each parameters. Each factor has two discrete levels, high and low. The values of high and low levels of the factors are as shown in Table 4.

Table 4. Factors and Levels

Factor High Level(+) Low Level(-) Die Thickness 0.3 mm 0.2 mm Die Size 8 X 8 mm2 6 X 6 mm2 Substrate Thickness

0.7 mm 0.6 mm

The design of experiment was set up in Minitab 17 and the various combinations of factors and their run orders are as shown in table 5.

Table 5. Design of Experiments set up in Minitab 17

A B C Warpage(microns)

-1 -1 -1 63.294 1 -1 -1 58.008 -1 1 -1 91.958 1 1 -1 83.70 -1 -1 1 54.732 1 -1 1 51.669 -1 1 1 80.031 1 1 1 75.106

Here A is die thickness, B is die size and C is substrate

thickness.

Fig.13. Normal Probability Plot

From the results of the design of experiments, it can be observed that an increase in die size tends to increase the warpage while a decrease in both substrate thickness and die thickness tends to increase warpage. This is because higher the die size, the higher expansion it would try to impose on the package. In order to counteract this, the package would warp more. At the same time, a reduction in substrate thickness would reduce the resistance offered to the thermal expansion caused by the die due to lesser stiffness of the substrate .This would again increase warpage. The result from this parametric study is crucial in modelling a package to keep warpage under required values.

XI. PACKAGE WARPAGE REDUCTION TECHNIQUES Using the studies made until this stage, an attempt was

made to optimize the package dimensions and implement control techniques to reduce the package warpage. Aim was to keep the package total height limited to 1mm, while trying to minimize package warpage to within 0.05mm.

Fig.14. Package schematic used for optimization

It can be seen that, in the optimization task, all the dimensions were fixed except the die and substrate thickness, which also have a dimensional constraint. The first approach was to try and reduce the warpage by optimizing the geometry based on the inference from the design of experiments on geometric parameters in section X. The values of parameters that yielded lowest warpage were die size 0.1mm, substrate thickness 0.86mm and under fill below die thickness of 0.04mm for a total package height of 1mm; hence meeting the geometric constraints. The result from optimizing the geometry gave a maximum warpage of 0.056mm at 25ºC which was above the maximum allowable warpage. The second approach was the use of an Epoxy Mold Compound (EMC) to reduce the package warpage. The EMC encapsulates the entire package and helps in reducing warpage

because of the lower thermal expansion mismatch with respect to both the substrate and the die. The geometry was chosen as follows, die size was set to 0.1mm, substrate thickness to 0.7mm, underfill between the die and substrate had a thickness of 0.04mm and the epoxy mold compound encapsulant had a height of 0.08mm above the package. The total package height was thus set to 1mm and all geometric constraints were met. The package geometry used for the FEM analysis is shown in figure 15.

Fig.15. Package Geometry

Three epoxy mold compounds namely EMC A, EMC B and EMC C with different temperature dependent properties were chosen to reduce warpage. The FEM results showed that the use of epoxy mold compounds helped to reduce warpage. This was majorly due to the high values of flexural modulus and lower thermal expansion mismatch between the epoxy mold compound and both die and substrate. The used of EMC C gave the least warpage of 50 microns at 25 C and 260 C, thus helping in attaining maximum warpage below 50 x10-3mm. The temperature dependent properties used for EMC C is shown in Table 6.

Table 6 EMC C Properties

Temperature

(C) Young’s

Modulus(GPa) Coeff. of Thermal Expansion(ppm/C)

25 27 18.8 165 3.4 42.5 260 0.6 42.2

Fig.16. Warpage at 25 C using EMC C

Fig. 17 Warpage at 250C using EMC C

Figure 16 and 17 show the FEM results for warpage at 25 C and 260 C respectively when using EMC C The warpage results at 25 C and 260 C from the FEM analysis for all the three EMC cases along with the geometric optimization are presented in Figure 18.

Fig. 18. Effect of EMC on Package Warpage

The results show that epoxy mold compounds help in reducing warpage both at 25 C and 260 C.

XII CONCLUSIONS Initially, from the experiments conducted, the principles of package warpage was thoroughly understood. It was also observed how an underfill contributes in reducing the package warpage. At later stages, from the parametric study it was understood that package warpage is very much dependent on the die size. An increase in die size leads to an increase in package warpage. An increase in package thickness would also result in decreased warpage. Hence it is essential to make the package design in order to counter warpage issues in packages with lower substrate thickness. One such method is analyzed here where Epoxy Mold Compounds may be used as encapsulates to control warpage both at room temperature and elevated temperatures.

XIII ACKNOWLEDGEMENTS We would like to thank Dr. Amaneh Tasooji, Mr.Bharat

Penmecha and Mr. Aditya Vaidya for their technical and intellectual support throughout the course of this project. A special thanks to Intel Corporation for providing a deep insight on the design and manufacturing of microelectronics packages.

XIV REFERENCES [1] K.N. Tu, “Reliability challenges in 3D IC Packaging Technology”, Microelectronics Reliability Vol 51, 2011, pp 517-523. [2] Wei Lin, Min Woo Lee, “PoP/CSP Warpage Evaluation and Viscoelastic Modeling,” , IEEE Transactions 2008 [3] Zhuqing Zhang and C. P. Wong, “Modeling of the Curing Kinetics of No-Flow Underfill in Flip-Chip Applications”. IEEE Transactions On Components And Packaging Technologies, Vol. 27, No. 2, June 2004 [4] Fulvio Fontana, Erik Balen, Egidio Perego, Donato Casati, Keith Hicks, Iftikhar Ahmad, “ Variable Frequency Microwave (VFM) Curing of Die Attach and Underfill Materials” , EMPC 2005, June 12-15, Brugge, Belgium. [5] Ming Li, Ting Lin Ting, Chiu Cheng-Hsin, “An investigation into curing behavior and kinetics of underfills for flip chip packages”, International Symposium on Electronic Materials and Packaging, 2000. (EMAP 2000) [6] Dr. Ken Gilleo. The Chemistry & Physics Of Underfill. [8] Debenedetti, P. G.; Stillinger (2001). "Supercooled liquids and the glass transition". Nature 410 (6825): 259–267 [9] André Hedler, Siegfried Ludwig Klaumünzer & Werner Wesch. Amorphous silicon exhibits a glass transition. Nature Materials 3, 804 - 809 (2004) [10] R R Tummala, E J Rymaszewski and AG Klopfenstein, “Microelectronics Packaging Handbook” (Chap-man & Hall, NewYork, 1996). [11] Narasimalu Srikanth, “Warpage Analysis of Epoxy Molded Package using Viscoelastic Based Model (2006). [12] Lin, W., et al, “PoP/CSP Warpage Evaluation and Viscolelastic Modeling; in Proc. IEEE Electronic Components and Technology Conference (ECTC 2008).

[13] MyoungSu Chae, Eric Ouyang, “Strip Warpage Anslysis of a Flip Chip Package Considering the Mold Compound Processing Parameters”; in Proc. IEEE Electronic Components and Technology Conference (ECTC 2013).

XV.APPENDIX MATLAB Code %% Project MSE 598 %% Script for generating plots for the

bimetallic strip %% Temperature T1= 200; T2=25; %% Youngs Modulus %% Copper E1 = 117e9; %%Aluminum E2 = 69e9; %%SS E3 = 200e9; %%Ratio of Modulus n1=E1/E2; n2=E2/E3; n3=E3/E1; nf=[n1 n2 n3]; %% Thickness (in meters) t1=0.1e-3:0.5e-4:1e-2; %t2=0.25e-3; %t3= 0.125e-3; %% Thickness Ratio %m1=1; m = length(t1); for i=1:1:(length(t1)-1) m(i)=t1(i)/t1(i+1); end m(length(t1))=1; %m3=t2/t3; %m4=t1/t3; %mf=[m1 m2 m3 m4]; %% Height of the Strip h = length(t1); for i=1:1:length(t1) h(i)=t1(i)*((1/m(i))+1); end %h2=t1+t2; %h3=t2+t3; %h4=t3+t1; %hf=[h1 h2 h3 h4]; %% Thermal expansion coefficient aCu = 16.6e-6; aAl = 22.2e-6; aSS = 16e-6; t=T1-T2; %% calcualtion of radius of curvature rho1=length(t1); rho2=length(t1); rho3=length(t1);

for i=1:1:length(t1) rho1(i) =

radius(m(i),n1,aCu,aAl,t,h(i)); rho2(i) =

radius(m(i),n2,aAl,aSS,t,h(i)); rho3(i) =

radius(m(i),n3,aSS,aCu,t,h(i)); end rho=[rho1;rho2;rho3]; plot(m,rho1,m,rho2,m,rho3); axis square; title('Change in Radius of curvature'); xlabel('Ratio of thickness'); ylabel('Radius of Curvature(mm)'); legend('Cu/Al strip','Al/SS strip','SS/Cu

strip');