final thesis of control technique for multilevel h-bridge inverter(spwm,svpwm,apod,pod,ipd)
TRANSCRIPT
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Control Techniques for Multilevel H – Bridge Inverters
Thesis submitted to Visvesvaraya National Institute of Technology,
Nagpur
In partial fulfilment of requirement for the award of degree of
BACHELOR OF TECHNOLOGY
(ELECTRICAL AND ELECTRONICS ENGINEERING)
Submitted By
AMEY PATIL (BT11EEE005)
AMEY KHOT (BT11EEE006)
CHARUDATT AWAGATHE (BT11EEE018)
SRIKANT PILLAI (BT11EEE051)
PURUSHOTAM KUMAR (BT11EEE053)
Under the guidance of
Prof. Dr. M.A. CHAUDHARI Department of Electrical Engineering
Visvesvaraya National Institute of Technology
Nagpur 440 010 (India) April 2015
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Visvesvaraya National Institute of Technology, Nagpur
2014 – 2015
CERTIFICATE
This is to certify that the project work entitled “Control Techniques for
Multilevel H – Bridge Inverters”, is a bonafide work by Mr. Amey Patil, Mr. Amey
Khot, Mr. Charudatt Awagate, Mr. Srikant Pillai and Mr. Purushotam Kumar in
the Department of Electrical Engineering, Visvesvaraya National Institute of
Technology, Nagpur, in partial fulfilment of the requirements of the award of
the degree of Bachelor of Technology in Electrical and Electronics Engineering.
Prof. Dr. S.R. Bhide
Head of Department
Department of Electrical Eng.
VNIT, Nagpur
Prof. Dr. M.A. Chaudhari
Mentor and Coordinator
Assistant Professor
Department of Electrical Eng.
VNIT, Nagpur
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Visvesvaraya National Institute of Technology, Nagpur
2014 – 2015
DECLARATION
This is to declare that the project work entitled “Control Techniques for
Multilevel H – Bridge Inverters”, is a bonafide work performed by us, the below
mentioned students. This project work is being submitted and forwarded in
partial fulfilment of the requirements for the award of the degree of Bachelor
of Technology in Electrical and Electronics Engineering from Visvesvaraya
National Institute of Technology, Nagpur.
To the best of our knowledge this project report has not been submitted
to any other institution or university.
Amey Patil Amey Khot Charudatt Awagate
Srikant Pillai Purushotam Kumar
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Acknowledgement
“The finest task of an Engineer – to survey, to plan, to suggest
resources and material, assemble them for task in hand,
implement and procedure results”
- Visvesvaraya
We take this opportunity to acknowledge with deep sense of gratitude
our project guide Prof. Dr. M.A. Chaudhari, Assistant Professor, Department of
Electrical and Electronics Engineering, VNIT Nagpur for her invaluable guidance,
constant motivation, and continuous support which has led to the successful
completion of this project.
We also take this opportunity to pay our sincere thanks to Dr. S.R. Bhide,
Head of Department, Electrical Engineering, VNIT Nagpur, for providing the
requisite facilities needed to complete the project. We would also like to thank
all the teaching and non-teaching staff for supporting us.
We express our thanks to our parents and all our friends for their
constant support and encouragement, which helped us complete this work.
Amey Patil
Amey Khot
Charudatt Awagate
Srikant Pillai
Purushotam Kumar
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Contents
1 Abstract ...................................................................................................... 8
2 Introduction ............................................................................................... 9
2.1 Inverters ............................................................................................... 9
2.1.1 Voltage Source Inverters (VSI) ...................................................... 10
2.1.2 Current Source Inverters .............................................................. 11
2.2 H-Bridge Inverters .............................................................................. 11
2.2.1 Three phase inverter .................................................................... 13
2.3 Inverter Applications .......................................................................... 14
3 Pulse Width Modulation Schemes ............................................................ 16
3.1 Control techniques for inverter output .............................................. 16
3.2 Internal Pulse Control in inverter ....................................................... 17
3.3 Pulse Width Modulation ..................................................................... 17
3.4 Modulation index ............................................................................... 19
3.5 Types of PWM techniques .................................................................. 20
3.5.1 Single PWM .................................................................................. 20
3.5.2 Multiple PWM .............................................................................. 20
3.5.3 Sine PWM ..................................................................................... 21
3.5.4 Space Vector PWM ....................................................................... 22
3.6 Space Vector PWM ............................................................................. 23
3.6.1 Concept of Space Vectors ............................................................. 23
3.6.2 Space Vector implementation in three phase inverter ................. 26
3.6.3 Main Sectors and Voltage Vector states ....................................... 27
3.6.4 Modulation through Space Vectors .............................................. 28
3.6.5 Conventional Switching Sequence ................................................ 29
3.6.6 Steps in SVPWM implementation ................................................. 31
3.6.7 Switching Time during any sector ................................................. 32
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3.6.8 Sector-wise switching pattern and Switching Timetable .............. 34
3.6.9 Output Voltage of SVPWM ........................................................... 36
4 Multilevel Inverters ................................................................................. 38
4.1 Comparison and advantage of Multilevel Inverters ............................ 39
4.1.1 Advantages of Multilevel Inverter: ............................................... 40
4.2 Types of Multilevel Inverters ............................................................. 41
4.2.1 Diode-clamped Multilevel Inverter ............................................... 41
4.2.2 Flying Capacitor Multilevel Inverter ............................................. 44
4.2.3 Cascaded Multilevel Inverter ........................................................ 46
4.2.4 Comparison of Multilevel Topologies ........................................... 48
4.3 Cascaded Multilevel Inverter .............................................................. 50
4.3.1 Cascaded H-Bridge Inverter with Equal DC voltage ...................... 50
4.3.2 Cascaded H-Bridge Inverter with Unequal DC voltage .................. 52
5 Multilevel Inverter PWM schemes ........................................................... 54
5.1 Level Shifted Sine PWM scheme ......................................................... 55
5.2 Types of Level Shifted Sine PWM ....................................................... 56
5.2.1 In-Phase Disposition IPD ............................................................... 56
5.2.2 Alternative Phase opposite Disposition APOD .............................. 57
5.2.3 Phase Opposite Disposition POD .................................................. 58
5.3 Phase Shifted Sine PWM scheme ...................................................... 59
6 Simulations ............................................................................................... 61
6.1 Simple PWM with Three phase Inverter ............................................. 61
6.2 Space Vector PWM for three phase Inverter ..................................... 62
6.3 Comparison between SPWM and SVPWM ......................................... 65
6.4 Simulation of 5-level Cascaded Inverter ............................................ 67
6.4.1 Multilevel Phase shifted Sine PWM Inverter ................................ 67
6.4.2 Multilevel level shifted Sine PWM Inverter .................................. 69
6.5 Simulation of 7-level Cascaded Inverter by Unequal DC voltages ....... 71
6.6 Comparison between phase shifted and level shifted ........................ 72
6.7 Conclusions ........................................................................................ 74
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7 References................................................................................................ 75
8 Appendices ............................................................................................... 76
8.1 Appendix 1- List of Figures.................................................................. 76
8.2 Appendix 2-List of Tables .................................................................... 78
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1 Abstract
Inverter serves a long variety of applications ranging from simple converting of
battery power to sinusoidal AC to high power HVDC transmission of electricity for a
very long distance. Its irreplaceable need in variable frequency drives which are used
on a very large scale worldwide, makes inverters very invaluable. Still there is much
scope for improvement in the inverting technology and so they have been a well
researching topic across the academics. Inverters have constantly gone over many
technological improvements, starting from the development of the switching gates
technologies, improvements in their max power handling capacities and reduction in
switching losses to improvement in the triggering circuitry. Developing of new pulse
triggering techniques and their specific adjustments as per the demand.
In this thesis, we look upon the various pulse triggering techniques implemented
by inverters and their comparison. We also discuss the methods and benefits of
increasing the level of inverters, including the reducing of Total Harmonic Distortion,
increase bus utilization and other such factors. This thesis has primarily focused on
Sinusoidal Pulse Width Modulation (SPWM), Space Vector concept & transformation,
Conventional Space Vector Pulse Width Modulation (SVPWM) technique,
computations for Space Vector PWM and then on the benefits of increasing the level
of inverter with discussion on different types of multilevel inverters, especially the
cascaded H-Bridge multilevel inverter. Along with the multilevel, we have worked on
the carrier based Sine PWM modes, namely phase shifted pulse width modulation and
level shifted pulse width modulation are can be used in the cascaded H-Bridge
Inverter. Simulations were done using PSIM and MATLAB Simulink for the given PWM
techniques. And it was observed that comparatively Space vector technique utilizes
DC bus voltage more efficiently and generates less harmonic distortion when
compared with Sinusoidal PWM.
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2 Introduction
2.1 Inverters
Inverters are the power electronic circuit, which converts the DC voltage
into AC voltage. The DC source is normally a battery or output of the controlled
rectifier. The output voltage waveform of the inverter can be square wave,
quasi-square wave or low distorted sine wave. The output voltage can be
controlled with the help of drives of the switches. The pulse width modulation
techniques are most commonly used to control the output voltage of inverters.
Such inverters are called as PWM inverters. The output voltage of the inverter
contain harmonics whenever it is not sinusoidal. These harmonics can be
reduced by using proper control schemes.
Inverters can be broadly classified into two types. They are-
Voltage Source Inverter (VSI)
Current Source Inverter (CSI)
When the DC voltage remains constant, then it is called voltage inverter
(VSI) or voltage fed inverter (VFI). When input current is maintained constant,
then it is called current source inverter (CSI) or current fed inverter (CFI).
Sometimes, the DC input voltage to the inverter is controlled to adjust the
output. Such inverters are called variable DC link inverters. The inverters can
have single phase or three-phase output.
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A voltage source inverter is fed by a stiff dc voltage, whereas a current
source inverter is fed by a stiff current source.
A voltage source can be converted to a current source by connecting a
series inductance and then varying the voltage to obtain the desired
current.
A VSI can also be operated in current-controlled mode, and similarly a CSI
can also be operated in the voltage control mode.
The inverters are used in variable frequency ac motor drives, uninterrupted
power supplies, induction heating, static VAR compensators, etc.
The following sections gives us the comparative study between VSI and CSI
2.1.1 Voltage Source Inverters (VSI)
VSI is fed from a DC voltage source having small or negligible impedance.
Input voltage is maintained
constant.
Output voltage does not
dependent on the load.
The waveform of the load
current as well as its magnitude
depends upon the nature of
load impedance.
VSI requires feedback diodes.
The commutation circuit is
complicated.
Power BJT, Power MOSFET, IGBT and GTO with self-commutation can be
used in the circuit.
Figure 2-1: Voltage source inverter
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2.1.2 Current Source Inverters
CSI is fed with adjustable
current from a DC voltage
source of high impedance.
The input current is constant
but adjustable.
The amplitude of output
current is independent of the
load.
The magnitude of output
voltage and its waveform
depends upon the nature of the load impedance.
The CSI does not require any feedback diodes.
Commutation circuit is simple as it contains only capacitors.
2.2 H-Bridge Inverters
As previously mentioned, the purpose of an inverter is to convert DC
power to AC power. Inverters are an integral part of many technologies
including uninterruptable power supplies, induction heating, high-voltage
direct current power transmission, variable frequency drives, electric vehicle
drives, and multiple renewable energy applications. All of these technologies
use inverters to achieve different goals, but all produce AC power from a DC
input. There are many varieties of inverter designs. The most common topology
used is show in the figure 2-3 and is referred to as the H-bridge topology.
Figure 2-2: Current source inverter
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The term H Bridge is derived from the typical graphical representation of such
a circuit. An H bridge is built with four switches (solid-state or mechanical).
When the switches S1 and S4 are closed a positive voltage will be applied across
the motor. By opening S1 and S4 switches and closing S2 and S3 switches, this
voltage is reversed, allowing reverse operation.
Using the nomenclature above, the switches S1 and S2 should never be
closed at the same time, as this would cause a short circuit on the input voltage
source. The same applies to the switches S3 and S4. This condition is known as
shoot-through.
Its basic configuration is shown in figure. This topology is used in
conjunction with either the square wave, or pulse width modulation (PWM)
switching schemes.
The square-wave switching scheme is a method for controlling the
switches (labelled S1 through S4) in order to achieve a square wave AC output
signal. The AC output is achieved by using a control signal with a 50% duty cycle
wired to S1 and S4. An inverted copy of the same signal is also wired to S2 and
Figure 2-3: Current source inverter
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S3. This switching scheme ensures that S1 and S4 are always on when S2 and S3
are off. It should be easily seen how such a switching scheme creates the square
wave output shown in figure. The advantage of using an H-bridge inverter is
that only a single, simple control signal is required to control four transistors.
The disadvantage, however, is that the square wave output is a low quality AC
signal that injects many harmonics into any loads to which it is powering. We
thus aim to reduce the harmonics in the output AC voltage by use of various
modulation techniques.
2.2.1 Three phase inverter
A Basic three phase inverter consist of three legs, each attached to the
phase output line. The upper and lower switching transistor are S1 & S4 for R
phase, S3 & S6 for Y phase and S5 & S2 for B phase respectively.
Figure 2-4: Basic three phase inverter
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2.3 Inverter Applications
DC power source utilization
An inverter converts the DC electricity from sources such
as batteries or fuel cells to AC electricity.
Uninterrupted powers source utilization
An uninterruptible power supply (UPS) uses batteries and an inverter to
supply AC power when main power is not available. When main power is
restored, a rectifier supplies DC power to recharge the batteries.
Electric motor speed control
Inverter circuits designed to produce a variable output voltage range are
often used within motor speed controllers. The DC power for the inverter
section can be derived from a normal AC wall outlet or some other
source. Control and feedback circuitry is used to adjust the final output
of the inverter section which will ultimately determine the speed of the
motor operating under its mechanical load.
Power grid
Grid-tied inverters are designed to feed into the electric power
distribution system. They transfer synchronously with the line and have
as little harmonic content as possible. They also need a means of
detecting the presence of utility power for safety reasons, so as not to
continue to dangerously feed power to the grid during a power outage.
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Solar
A solar inverter is a balance of system (BOS) component of a photovoltaic
system and can be used for both, grid-connected and off-grid systems.
Solar inverters have special functions adapted for use
with photovoltaic arrays, including maximum power point
tracking and anti-islanding protection.
HVDC
With HVDC power transmission, AC power is rectified and high voltage
DC power is transmitted to another location. At the receiving location, an
inverter in a static inverter plant converts the power back to AC. The
inverter must be synchronized with grid frequency and phase and
minimize harmonic generation.
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3 Pulse Width Modulation Schemes
3.1 Control techniques for inverter output
This section examines various methods of output voltage control by means
of inverter gain control. The inverter gain is defined as the ratio of output ac
voltage to input dc voltage. Such gain control is useful in many applications
where the variations of ac output voltage cannot be tolerated due to the
variations in dc input voltage. It is also necessary when volts/Hertz control of
induction motor speeds has to be implemented. The control of motor voltage
is required along with frequency in order to avoid saturation of the motor
magnetic circuit. Various techniques are available for varying the inverter gain.
The most efficient method of controlling the gain and therefore the output
voltage is to incorporate Pulse Width Modulation (PWM) control within the
inverters. In addition to PWM method, there are methods involving external
control of ac output voltage and dc input voltage. To distinguish these methods
from the PWM method, PWM method is referred to as the internal control
method since the output voltage control is realized by means of modifications
in the conduction patterns of the inverter switches. Various methods for the
control of output voltage of inverters can be enumerated as follows:
(1) External control of the AC output voltage
(2) External control of the DC input voltage
(3) Internal control of the inverter output voltage
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In the first two methods, extra circuits for the control of either dc input
or ac output become necessary. The third method, however, does not require
such circuits. This can be clearly understood in the remaining section that
discusses these methods in considerable detail.
The first two methods require the use of peripheral components whereas
the third method requires no external components. Mostly the internal control
of the inverters is dealt, and so the third method of control is discussed in great
detail in the following section.
3.2 Internal Pulse Control in inverter
Inverter output voltage can also be adjusted by exercising a control
within the inverter itself. Pulse width modulation is the most commonly used
technique to control the output voltage of inverter, the various techniques are:
o Single PWM
o Multiple PWM
o Sine PWM
o Space Vector PWM
3.3 Pulse Width Modulation
Pulse-width modulation (PWM) is the basis for control in power
electronics. The theoretically zero rise and fall time of an ideal PWM waveform
represents a preferred way of driving modern semiconductor power devices.
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With the exception of some resonant converters, the vast majority of power
electronic circuits are controlled by PWM signals of various forms. The rapid
rising and falling edges ensure that the semiconductor power devices are
turned on or turned off as fast as practically possible to minimize the switching
transition time and the associated switching losses. Although other
considerations, such as parasitic ringing and electromagnetic interference (EMI)
emission, may impose an upper limit on the turn-on and turn-off speed in
practical situations, the resulting finite rise and fall time can be ignored in the
analysis of PWM signals and processes in most cases. Hence only ideal PWM
signals with zero rise
and fall time will be
considered in this
chapter.
Pulse width
modulation is a
technique in which a
fixed input dc voltage is
given to the inverter
and a controlled ac
output voltage is
obtained by adjusting
the on and off periods
of the inverter
components. This is most popular method of controlling the output voltage and
this method is termed as pulse width modulation technique. PWM is an internal
control method and it gives better result than an external control methods.
Figure 3-1: PWM Duty cycle comparison
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There are number of PWM methods for variable frequency voltage-sourced
inverters. A suitable PWM technique is employed in order to obtain the require
In this method, a fixed dc input voltage is given to the inverter and a
controlled ac output voltage is obtained by adjusting the on and off periods of
the inverter components. Inverters employing PWM principle are called PWM
inverters. PWM techniques are characterized by constant amplitude pulses. The
width of these pulses is modulated to obtain inverter output voltage control
and to reduce its harmonic content. The advantages possessed by PWM
technique are
1. The output voltage control with this method can be obtained without any
additional components.
2. With this method, lower order harmonics can be eliminated or minimized
along with its output voltage control. As higher order harmonics can be
filtered easily, the filtering requirements are minimized.
The main disadvantage of this method is that the SCRs are expensive as they
must possess low turn on and turn off times. This is the most popular method
of controlling the output voltage of an inverter in industrial applications.
Benefits include – Microprocessor control – Efficient use of power –
Tolerance to analog noise – Not susceptible to component drift.
3.4 Modulation index
Modulation index is the ratio of peak magnitudes of the modulating
waveform and the carrier waveform. It relates the inverter's dc-link voltage and
the magnitude of pole voltage (fundamental component) Output by the
inverter. The ratio of the peak magnitudes of modulating wave) and the carrier
wave (VC) is defined as modulation-index.
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𝑀 =𝑉𝑝
𝑉𝑐
3.5 Types of PWM techniques
3.5.1 Single PWM
In single pulse-width modulation control, there is only one pulse per half-
cycle and the width of the pulse is varying to control the output voltage.
Fig.-3-2 shows the generation of gating signals of single pulse width
modulation. The gating signals are generated by the signals of single pulse width
modulation. The single pulse-width modulation converts the reference signal to
the square wave signal. This process is obtained by inter the reference signal to
the zero-crossing circuit witch consider the positive part of the input signal is
positive part of the output signal (square wave) and the negative part of the
input signal is negative part of the output signal.
3.5.2 Multiple PWM
The harmonic content can be reduced by using several pulses in each
half-cycle of output voltage. The generation of gating signals for turning on and
off transistors is shown in Fig. The gating signals are produced by comparing
reference signal with triangular carrier wave. The frequency of the reference
signal sets the output frequency (𝑓O) and carrier frequency (𝑓C) determine the
number of pulses per half cycle.
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3.5.3 Sine PWM
In single-pulse and multiple pulse modulation techniques the width of all
pulses are same but in sinusoidal pulse width modulation the width of each
pulse is varied in proportion to the amplitude of a sine wave. In this technique
the gating signals are generated by comparing a sinusoidal reference signal with
a triangular carrier wave. The gating signal of the inverter is obtained by taking
the repeating sequence (triangular wave) as the control signal and comparing it
Figure 3-2: Bipolar Sine PWM
Figure 3-3: Unipolar Sine PWM
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with the reference wave (sinusoidal wave). In order to detect or eliminate the
zero sequence currents we use zero hold circuit and by comparing them with
the help of greater than or equal to blocks.
A Sinusoidal Pulse Width Modulation technique is also known as the
triangulation, sub oscillation, sub harmonic method is very popular in industrial
applications. In this technique a high frequency triangular carrier wave is
compared with the sinusoidal reference wave determines the switching instant.
It is to be noted that by controlling the modulation index one can control the
amplitude of applied output voltage.
3.5.4 Space Vector PWM
Space Vector modulation technique is another method available for
obtaining output voltage above that of the standard Sine PWM technique. This
is achieved by rotating a reference vector around the state diagram, which is
composed of six basic non zero vectors forming a hexagon. The complete full
circular rotation of the reference vector in the state diagram constitutes unit
pulse time cycle i.e. 20ms for a frequency of 50Hz.
Space Vector technique is further discussed in the immediate section 3.6 along
with its basic principle and conventional implementation.
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3.6 Space Vector PWM
Space Vector Modulation (SVM) was originally developed as vector
approach to Pulse Width Modulation (PWM) for three phase inverters. It is the
more sophisticated technique for generating sine wave that provides a higher
voltage to the motor with lower total harmonic distortion. And it is one of the
most widely used PWM technique for Variable Frequency Drive Applications.
The method is highly computation-intense with dynamic calculations done to
calculate the TON time of every switch within every sampling interval. One of
major advantage of SVPWM is the reduction of Total Harmonic Distortion
(THD), created by the rapid switching created by the PWM algorithm. The main
aim of any modulation technique is to obtain variable output having a maximum
fundamental component with minimum harmonics. Space Vector PWM
(SVPWM) method is an advanced; computation intensive PWM method and
possibly the best techniques for variable frequency drive application.
Also SVPWM has the aptitude for accurate digital implementation which
can be realised through Digital Signal Processor (DSP). This Superior
Performance has enabled it to find wide spread applications in recent years.
3.6.1 Concept of Space Vectors
Space Vector involves a constant amplitude vector rotating at a constant
frequency obtained from their three phase sinusoidal forms. The rotating
vector is rotated in a stationary d-q coordinate frame plane and made to imitate
its equivalent 3 phase rotating vector via 2 phase vectors. This is known as
coordinate transformation.
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For three phase system,
𝑉𝑅𝐸𝐹 = 𝑉𝑅𝑁 + 𝑉𝑌𝑁 + 𝑉𝐵𝑁
Where,
𝑉𝑅𝑁 = 𝑉𝑚 sin(𝜔𝑡)
𝑉𝑌𝑁 = 𝑉𝑚 sin(𝜔𝑡 − (2𝜋3⁄ ))
𝑉𝑌𝑁 = 𝑉𝑚 sin(𝜔𝑡 + (2𝜋3⁄ ))
And with d-q plane,
𝑉𝑅𝐸𝐹 = 𝑉𝑑 + 𝑉𝑞
With this we are able to obtain an equivalent VREF from three phase
directly through 2 vector method as shown in figure 3-4.
We therefore obtain Vd and Vq as follows
𝑉𝑑 = 𝑉𝑅𝑁 + 𝑉𝑌𝑁 cos(2𝜋3⁄ ) + 𝑉𝐵𝑁 cos(4𝜋
3⁄ )
= 𝑉𝑅𝑁 − (12⁄ )𝑉𝑌𝑁 − (1
2⁄ )𝑉𝐵𝑁
= 𝑉𝑅𝑁 + (12⁄ )𝑉𝑅𝑁
= (32⁄ )𝑉𝑅𝑁
𝑉𝑑 = 𝑉𝑅𝑁 + 𝑉𝑌𝑁 cos(2𝜋3⁄ ) + 𝑉𝐵𝑁 cos(4𝜋
3⁄ )
= 𝑉𝑅𝑁 − (12⁄ )𝑉𝑌𝑁 − (1
2⁄ )𝑉𝐵𝑁
= 𝑉𝑅𝑁 + (12⁄ )𝑉𝑅𝑁
= (32⁄ )𝑉𝑅𝑁
Figure 3-4: Coordinate Transformation RYB to d-q
25
And in Matrix form as,
⌈𝑉𝑑
𝑉𝑞 ⌉ = [
32⁄ 0 0
0 √32
⁄ − √32
⁄ ] . [
𝑉𝑅𝑁
𝑉𝑌𝑁 𝑉𝐵𝑁
]
𝑉𝑞 = 𝑉𝑅𝑁 cos(3𝜋2⁄ ) + 𝑉𝑌𝑁 cos(𝜋
6⁄ ) + 𝑉𝐵𝑁 cos(5𝜋6⁄ )
= 0 − (√32
⁄ ) 𝑉𝑌𝑁 + (√32
⁄ ) 𝑉𝐵𝑁
= (√32
⁄ ) (𝑉𝑌𝑁 − 𝑉𝐵𝑁)
Figure 3-5: Three phase inverter
26
3.6.2 Space Vector implementation in three phase
inverter
The Circuit Model for a typical three phase voltage source PWM inverter
is shown in Fig 3-5. Here, S1 to S6 are the six power switches that shape the
output waveform.
When an upper transistor is switched ON, the corresponding lower
transistor is switched OFF. The ON – OFF states of the upper transistors S1, S3
& S5 determines the Voltage vector state.
Figure 3-6 denotes the VREF
rotation as the switches are
switched ON and OFF. Only the
upper transistor switching is
considered here.
So ‘+ - -‘denotes S1=ON, S3=OFF &
S5=OFF and so on.
Above Figure 3-6 shows Vector space location of every state denoted along
with their corresponding switching states of the upper switches of the circuit.
Figure 3-6: VREF rotating along Voltage Space Vectors
27
3.6.3 Main Sectors and Voltage Vector states
Voltage vectors created divides the cycle into 6 sectors as observed in
figure 3-8. Here 6 vector states forms the six corners of a hexagon structure
around which the reference voltage revolves. Other 2 states namely, (111) &
(000) are null vectors as produce no effective output.
The rotating VREF takes the intermediate values between each sector using
the adjacent space vector as d-q plane.
Figure 3-7: Equivalent Switching pattern of the space vectors
Figure 3-8: Space Vector Diagram
28
3.6.4 Modulation through Space Vectors
The main factor by which Space Vector Modulation comes out superior
is because of its ability to occupy intermediate values between the space
vectors providing smooth transition for reference voltage VREF as it rotates.
This is achieved by having an average over the sampling period, since the
reference voltage is sampled at regular time interval TS. Within this sampling
period, VREF is synthesized using adjacent vectors and the null vector.
In Figure 3-9, it can be observed that there are 3 averaged values existing
for each sector. The averaging of the VREF is by having one branch of the adjacent
space vector ON for a fraction of the sampling time and then another one so
that overall vector average of both of them yields the desired average vector.
(- - -) or (000) is numbered as state-(0)
(+ - -) or (100) is numbered as state-(1)
(+ + -) or (110) is numbered as state-(2)
(- + -) or (010) is numbered as state-(3)
(- + +) or (011) is numbered as state-(4)
(- - +) or (001) is numbered as state-(5)
(+ - +) or (101) is numbered as state-(6)
(+ + +) or (111) is numbered as state-(7) Figure 3-9: Sector Distribution
29
Let us consider Sector 1 for calculation purposes.
If T is the sampling time, then V1 is applied for T1 and V2 is applied for T2
while Zero voltage is applied for the rest of the time period. Here Zero voltage
is TZ, which is the sum of T0 & T7. i.e. T0 + T7 = TZ
𝑇𝑧 = 𝑇 − 𝑇1 − 𝑇2
This way every intermediate value is sampled between adjacent voltage vectors
of each sector and a much smoother reference voltage is obtained as shown in
fig 3-10.
3.6.5 Conventional Switching Sequence
SVPWM is implemented through many different switching sequence
patterns, the most common and widely used is the conventional switching
Figure 3-10: Sector 1 VREF approximation over a sampling time
30
sequence, which maintains switching of one transistor at a time to minimise
switching losses.
Conventional Switching
sequence for sector 1 is
presented as shown above figure
3-11. This sequence is followed
for every intermediate VREF value
in this sector.
1. - - -
2. + - -
3. + + -
4. + + +
5. + + +
6. + + -
7. + - -
8. - - -
Conventional
Switching Sequence
In Sector 1
Figure 3-11: Switching Sequence for all VREF pattern in sector (only T1 T2 T0 varies)
Figure 3-12: Graphical switching pattern for different sectors
31
It can be easily observed that above sequence implements V1 (+ - -) and
V2 (+ + -) only along with the Zeros V0 (- - -) & V7 (+ + +). The only thing that varies
within a sector is the TON time for both the vectors i.e. T1, T2.
Likewise switching sequence for other sectors can be obtained
implementing their required vectors with appropriate Zero vectors. Figure 3-12
above shows the approximate switching sequence graphically. Note that the
null vectors (or Zero vectors) are used in all the sector sequence (1 to 6).
3.6.6 Steps in SVPWM implementation
Switching times T1 & T2 (for sector 1) or T2 & T3 (for sector 2) is calculated
during each sampling period and implemented accordingly.
Here we demonstrate calculation for Sector 1, which can be similarly
followed for other sectors by substituting their required adjacent voltage space
vectors. T1 T2 T0 & T7 are calculated by Volt-Second integral of VREF for a given
sampling period in the sector.
We have,
𝑉𝑅𝐸𝐹𝑇𝑆 = 𝑉1. 𝑇1 + 𝑉2 . 𝑇2 + 𝑉𝑍. 𝑇𝑍
𝑇𝑆 = 𝑇1 + 𝑇2 + 𝑇𝑍
By Volt-Second integral of VREF
1
𝑇∫ ��𝑅𝐸𝐹 𝑑𝑡
𝑇
0
= 1
𝑇[∫ ��0 𝑑𝑡
𝑇0
0
+ ∫ ��1 𝑑𝑡𝑇1
0
+ ∫ ��2 𝑑𝑡𝑇2
0
+ ∫ ��7 𝑑𝑡𝑇7
0
]
��𝑅𝐸𝐹 . 𝑇 = 𝑉0. 𝑇0 + 𝑉1. 𝑇1 + 𝑉2
. 𝑇2 + 𝑉7. 𝑇7
��𝑅𝐸𝐹 . 𝑇 = 0. 𝑇0 +2
3𝑉1. 𝑇1 +
2
3𝑉𝑑 . (cos 𝜋
3⁄ + 𝑗 𝑠𝑖𝑛 𝜋3⁄ ). 𝑇2 + 0. 𝑇7
32
��𝑅𝐸𝐹 . 𝑇 = 2
3𝑉1. 𝑇1 +
2
3𝑉𝑑(cos 𝜋
3⁄ + 𝑗 𝑠𝑖𝑛 𝜋3⁄ )𝑇2
𝑆𝑝𝑙𝑖𝑡𝑖𝑛𝑔 𝑟𝑒𝑎𝑙 𝑎𝑛𝑑 𝑖𝑚𝑎𝑔𝑖𝑛𝑎𝑟𝑦 𝑝𝑎𝑟𝑡𝑠
𝑇 |��𝑅𝐸𝐹| 𝑐𝑜𝑠 𝛼 = 2
3𝑉𝑑𝑇1 +
1
3𝑉𝑑𝑇2 𝑇 |��𝑅𝐸𝐹| 𝑠𝑖𝑛 𝛼 =
1
√3𝑉𝑑𝑇2
Solving for T0, T1, and T2 & T7 gives:
𝑇1 = 3
2𝑚 [(𝑇
√3⁄ ) cos 𝛼 − (𝑇
3⁄ ) sin 𝛼]
𝑇2 = 𝑚𝑇 sin 𝛼
Where,
𝑚 =𝑉𝑅𝐸𝐹
(𝑉𝑑 √3⁄ )⁄
Above Equations are derived for Sector 1, similarly other sector
equations are to be derived for their respective switching time calculations.
3.6.7 Switching Time during any sector
Step 1. Determine Vd, Vq, VREF, and angle (α)
Here, VREF and angle (α) are obtained through Vd & Vq which are
calculated through the following matrix,
⌈𝑉𝑑
𝑉𝑞 ⌉ = [
32⁄ 0 0
0 √32
⁄ − √32
⁄ ] . [
𝑉𝑅𝑁
𝑉𝑌𝑁 𝑉𝐵𝑁
]
And so,
𝛼 = tan−1(𝑉𝑑
𝑉𝑞) |𝑉𝑅𝐸𝐹| = √𝑉𝑑
2 + 𝑉𝑞2
For T0 & T7
TZ = T – T1 – T2
T0 = T7 = 0.5 TZ
33
Step 2. Determine time duration T1, T2, T0
Switching time is calculated based on the Volt-Second integral i.e.
𝑉𝑅𝐸𝐹𝑇𝑆 = 𝑉1. 𝑇1 + 𝑉2 . 𝑇2 + 𝑉𝑍. 𝑇𝑍
𝑇𝑆 = 𝑇1 + 𝑇2 + 𝑇𝑍
Giving results as
𝑇1 = 3
2𝑚 [(𝑇
√3⁄ ) cos 𝛼 − (𝑇
3⁄ ) sin 𝛼]
𝑇2 = 𝑚𝑇 sin 𝛼
Where,
𝑚 =𝑉𝑅𝐸𝐹
(𝑉𝑑 √3⁄ )⁄
Step 3. Determine the switching time of each transistor (S1 to S6)
Switching time for every vector state (e.g. T1 or T2 for sector 1) is
calculated and the corresponding switches which defined the state (e.g. state
’+ - -’ or ‘100’ is defined as S1, S6 & S2 as positive while S4, S3 & S5 as closed)
are triggered for the calculated time. This is done for all the required switches.
34
3.6.8 Sector-wise switching pattern and Switching
Timetable
Following is the graphical representation of the switching sequence
during each sector. Their values are calculated dynamically as mentioned in the
previous section.
Figure 3-13: Switching plots for all 6 sectors
35
And the switching time for each sector can be summarized as shown
below.
Table 3-1: Switching time for each sector 1-6
Sector Upper Switches
(S1, S3, S5) Lower Switches
(S4, S6, S2)
1
S1 = T1 + T2 + T0/2 S4 = T0/2
S3 = T2 + T0/2 S6 = T1 + T0/2
S5 = T0/2 S2 = T1 + T2 + T0/2
2
S1 = T2 + T0/2 S4 = T1 + T0/2
S3 = T1 + T2 + T0/2 S6 = T0/2
S5 = T0/2 S2 = T1 + T2 + T0/2
3
S1 = T0/2 S4 = T1 + T2 + T0/2
S3 = T1 + T2 + T0/2 S6 = T0/2
S5 = T2 + T0/2 S2 = T1 + T0/2
4
S1 = T0/2 S4 = T1 + T2 + T0/2
S3 = T2 + T0/2 S6 = T1 + T0/2
S5 = T1 + T2 + T0/2 S2 = T0/2
5
S1 = T2 + T0/2 S4 = T1 + T0/2
S3 = T0/2 S6 = T1 + T2 + T0/2
S5 = T1 + T2 + T0/2 S2 = T0/2
6
S1 = T1 + T2 + T0/2 S4 = T0/2
S3 = T0/2 S6 = T1 + T2 + T0/2
S5 = T2 + T0/2 S2 = T1 + T0/2
36
3.6.9 Output Voltage of SVPWM
The Line to Neutral (phase) voltage obtained [VRN VYN VBN] is obtained
through the following matrix.
[
𝑉𝑅𝑁
𝑉𝑌𝑁
𝑉𝐵𝑁
] = 1
3 𝑉𝐷𝐶 [
2 −1 −1−1 2 −1−1 −1 2
] [����
��
]
The inverter here undergoes through 8 vector states with the following
switching configuration as shown in figure 3-14.
Figure 3-14: Switching states of the inverter
37
According to those states following output voltage table is derived for
every input Voltage Vector trigger pulse.
Table 3-2: Output Voltage table
Voltage Vectors
Switching Vectors Line to neutral
Voltage Line to line Voltage
R Y B VAN VBN VCN VRY VYB VBY
V0 0 0 0 0 0 0 0 0 0
V1 1 0 0 23⁄ − 1
3⁄ − 13⁄ 1 0 -1
V2 1 1 0 13⁄ 1
3⁄ − 23⁄ 0 1 -1
V3 0 1 0 − 13⁄ 2
3⁄ − 13⁄ -1 1 0
V4 0 1 1 − 23⁄ 1
3⁄ 13⁄ -1 0 1
V5 0 0 1 − 13⁄ − 1
3⁄ 23⁄ 0 -1 1
V6 1 0 1 13⁄ − 2
3⁄ 13⁄ 1 -1 0
V7 1 1 1 0 0 0 0 0 0
38
4 Multilevel Inverters
The Inverter is an electrical device which converts direct current (DC) to
alternate current (AC). The inverter is used for emergency backup power in a
home. The inverter is used in some aircraft systems to convert a portion of the
aircraft DC power to AC. The AC power is used mainly for electrical devices like
lights, radar, radio, motor, and other devices.
Now a day’s many industrial applications have begun to require high
power. Some appliances in the industries however require medium or low
power for their operation. Using a high power source for all industrial loads may
prove beneficial to some motors requiring high power, while it may damage the
other loads. Some medium voltage motor drives and utility applications require
medium voltage. The multi-level inverter has been introduced since 1975 as
alternative in high power and medium voltage situations. The Multi-level
inverter is like an inverter and it is used for industrial applications as alternative
in high power and medium voltage situations.
Multi-level inverters are the modification of basic bridge inverters. They
are normally connected in series to form stacks of level.
Figure 3-1: Typical Inverter Display panel
39
The topological structure of multilevel inverter must cope with the
following points-
It should have less switching devices as far as possible.
It should be capable of enduring very high input voltage such as HVDC
transmission for high power applications.
Each switching device should have lower switching frequency owing to
multilevel approach.
4.1 Comparison and advantage of Multilevel
Inverters
Table 4-1: Comparison between Conventional Inverters And Multilevel Inverters
Sr.no Conventional inverter Multilevel inverter
1 Higher THD in output voltage Low THD in output voltage
2 More switching stresses on devices
Reduced switching stresses on devices
3 Not applicable for high voltage applications
Applicable for high voltage applications
4 Higher voltage levels are not produced
Higher voltage levels are produced
5 Since 𝑑𝑣𝑑𝑡⁄ is high, the EMI
from the system is high
Since 𝑑𝑣𝑑𝑡⁄ is low, the EMI from the
system is low
6 Higher switching frequency is used hence switching losses is
high
Lower switching frequency can be used and hence reduction in
switching losses
7 Power bus structure, control schemes are simple
Control scheme is complex as the number of levels increases
40
4.1.1 Advantages of Multilevel Inverter:
The multilevel converter has a several advantages such as-
Common Mode Voltage:
The multilevel inverters produce common mode voltage, reducing the stress of
the motor and don’t damage the motor.
Input Current:
Multilevel inverters can draw input current with low distortion.
Switching Frequency:
The multilevel inverter can operate at both fundamental switching frequencies
that are higher switching frequency and lower switching frequency. It
should be noted that the lower switching frequency means lower
switching loss and higher efficiency is achieved.
Reduced harmonic distortion:
Selective harmonic elimination technique along with the multi-level topology
results the total harmonic distortion becomes low in the output waveform
without using any filter circuit.
41
4.2 Types of Multilevel Inverters
Multilevel inverters are classified on the basis of the circuit structure and
are of three types
4.2.1 Diode-clamped Multilevel Inverter
The main concept of this inverter is to use diodes and provides the multiple
voltage levels through the different phases to the capacitor banks which are in
series. A diode transfers a limited amount of voltage, thereby reducing the
stress on other electrical devices. The maximum output voltage is half of the
input DC voltage. It is the main drawback of the diode clamped multilevel
inverter. This problem can be solved by increasing the switches, diodes,
capacitors.
Multilevel Inverters
Common DC sources
Diode clamped Inverters
Flying Capacitor Inverters
Separate DC sources
Cascaded Inverters
Figure 4-2: Types of Multilevel Inverter
42
Due to the capacitor balancing issues, these are limited to the three levels.
This type of inverters provides the high efficiency because the fundamental
frequency used for all the switching devices and it is a simple method of the
back to back power transfer systems.
Table 4-2: Switching sequence for 5 level Diode Clamped Inverter
Output S1 S2 S3 S4 S1’ S2’ S3’ S4’
VDC 1 1 1 1 0 0 0 0
VDC/2 0 1 1 1 1 0 0 0
0 0 0 1 1 1 1 0 0
-VDC/2 0 0 0 1 1 1 1 0
-VDC 0 0 0 0 1 1 1 1
Figure 4-3: Topology of the diode-clamped inverter (a) three-level inverter, (b) Five -level inverter
43
Applications of Diode Clamped Multilevel Inverter:
Static VAR compensation
Variable speed motor drives
High voltage system interconnections
High voltage DC and AC transmission lines
Advantages
When the number of levels is high enough, harmonic content will be low
enough to avoid the need for filters.
Efficiency is high due to all devices which are being switched at the
fundamental frequency.
We are able to control the reactive power flow.
The control method is easy for a back to back intertie system.
Disadvantages
Excessive clamping diodes are being required when the number of levels
get high.
It is hard to do a real power flow control for individual converter.
44
4.2.2 Flying Capacitor Multilevel Inverter
The main concept of this inverter is to use capacitors. It is of series
connection of capacitor clamped switching cells. The capacitors transfer the
limited amount of voltage to electrical devices. In this inverter switching states
are like in the diode clamped inverter. Clamping diodes are not required in this
type of multilevel inverters. The output is half of the input DC voltage. It is
drawback of the flying capacitors multi-level inverter. It also has the switching
redundancy within phase to balance the flaying capacitors. It can control both
the active and reactive power flow. But due to the high frequency switching,
switching losses will takes place.
Figure 4-4: Topology of the Flying Capacitor Multilevel inverter (a) three-level inverter, (b) Five -level inverter
45
Applications of Flying Capacitors Multilevel Inverter:
Induction motor control using DTC (Direct Torque Control) circuit.
Static VAR generation.
Both AC-DC and DC-AC conversion applications.
Converters with Harmonic distortion capability.
Sinusoidal current rectifiers.
Advantages:
Huge amount of storage capacitors will provide additional ride through
capabilities during power rage.
Switch combination redundancy are provided for balancing different
voltage levels.
When the number of levels is high enough, the harmonic content will be
low enough not to use the filter.
We are able to control both the real and reactive power flow, and making
a possible voltage source converter candidate for high voltage dc
transmission.
46
Disadvantages:
When the number of converter levels get high, a huge amount of storage
capacitor is required. Those high level systems are more difficult to
package and those bulky capacitors are expensive.
The switching frequency and switching losses will soar high for real power
transmission and the converter control will get very complicated.
Table 4-3: Switching sequence for 5 level Inverter
4.2.3 Cascaded Multilevel Inverter
A cascade multilevel inverter is a power electronic device built to synthesize
a desired AC voltage from several levels of DC voltages. Such inverters have
been the subject of research in the last several years, where the DC levels were
considered to be identical in that all of them were either batteries, solar cells,
etc. A multilevel converter was presented in which the two separate DC sources
were the secondary of two transformers coupled to the utility AC power. In
contrast, in this paper, only one source is used without the use of transformers.
The interest here is interfacing a single DC power source with a cascade
Output S1 S2 S3 S4 S1’ S2’ S3’ S4’
VDC 1 1 1 1 0 0 0 0
3VDC/4 1 1 1 0 0 0 0 1
VDC/2 1 1 0 0 0 0 1 1
VDC/4 1 0 0 0 0 1 1 1
0 0 0 0 0 1 1 1 1
47
multilevel inverter here the other DC sources are capacitors. Currently, each
phase of a cascade multilevel inverter requires ‘n’ DC sources for 2n+1 levels in
applications that involve real power transfer.
Applications of Cascaded Multilevel Inverter:
Motor drives
Active filters
Electric vehicle drives
DC power source utilization
Power factor compensators
Back to back frequency link systems
Interfacing with renewable energy resources.
Figure 4-5: a) Inverter Single Stage b) 5 level Cascaded Inverter c) 7 level Cascaded Inverter
48
Advantages:
The modularized structure allows easy packaging and storage.
The quantity of possible voltage levels is more than DC and FC type.
Disadvantages:
Separated DC sources or capacitor are required for each module.
A more complex controller is required due to the amount of capacitors,
which need to be balanced.
4.2.4 Comparison of Multilevel Topologies
Table 4-4: Comparison of multilevel inverter Topologies
Sr. No.
Topology Diode
Clamped Flying
Capacitor Cascaded
1 Power
semiconductor switches
2(m-1) 2(m-1) 2(m-1)
2 Clamping
diodes per phase
(m-1)(m-2) 0 0
3 DC bus
capacitors (m-1) (m-1) (m-1)/2
4 Balancing
capacitors per phase
0 (m-1)(m-
2)/2 0
5 Voltage
unbalancing Average High very small
6 Applications Motor drive
system, STATCOM
Motor drive system,
STATCOM
Motor drive system, PV, fuel cells,
battery system
49
The diode clamped inverters particularly the three-level structure have a
wide popularity in motor drive applications besides other multilevel inverter
topologies. However, it would be a limitation of complexity and number of
clamping diodes for the DCMLIs, as the level exceeds. The FCMLIs are based on
balancing capacitors on phase buses and generate multilevel output voltage
waveform clamped by capacitors instead of diodes. The FCMLI topology also
requires balancing capacitors per phase at a number of (m-1)*(m-2)/2 for an
m-level inverter and it will cause to increase the number of required capacitor
in high level inverter topologies and complexity of considering DC-link
balancing. Nowadays, the multilevel inverters have become more attractive for
researchers and manufacturers due to their advantages over conventional
three-level pulse width-modulated (PWM) inverters.
They offer improved output waveforms, smaller filter size, low EMI, lower
total harmonic distortion (THD). Multilevel inverter topology has the least
components for a given number of levels. Cascaded H-Bridge-MLI topology is
based on the series connection of H-bridges with separate DC sources. Since the
output terminals of the H-bridges are connected in series, the DC sources must
be isolated from each other. The need of several sources on the DC side of the
inverter makes multilevel technology attractive for photovoltaic applications.
50
4.3 Cascaded Multilevel Inverter
4.3.1 Cascaded H-Bridge Inverter with Equal DC voltage
As the name suggests, the cascaded H-bridge multilevel inverter uses
multiple units of H-bridge power cells connected in a series chain to produce
high ac voltages. A typical configuration of a five-level CHB inverter is shown
in Fig. below, where each phase leg consists of two H-bridge cells powered by
two isolated dc supplies of equal voltage E. The CHB inverter in Fig can
produce a phase voltage with five voltage levels. When switches S11, S21, S12,
and S22 conduct, the output voltage of the H- bridge cells H1 and H2 is VH1 =
VH2 = E, and the resultant inverter phase voltage is VAN = VH1 + VH2 = 2E, which
is the voltage at the inverter terminal A with respect to the inverter neutral
N. Similarly, with S31, S41, S32, and S42 switched on, VAN = –2E. The other three
voltage levels are E, 0, and –E, which correspond to various switching states
Figure 4-6: Cascaded H-Bridge with equal DC Voltage
51
summarized in Table. It is worth noting that the inverter phase volt- age VAN
may not necessarily equal the load phase voltage VAO, which is the voltage at
node A with respect to the load neutral O.
It can be observed from Table that some voltage levels can be obtained by
more than one switching state. The voltage level E, for instance, can be
produced by four sets of different (redundant) switching states. The switching
state redundancy is a common phenomenon in multilevel converters. It
provides a great flexibility for switching pattern design, especially for space
vector modulation schemes.
Switching table for 5 level CHB inverter:
Table 4-5: Switching table for 5 level
Equal DC CHB inverter
Output Voltage
VAN
Switching State VH1 VH1 S11 S31 S12 S32
2E 1 0 1 0 E E
E
1 0 1 1 E 0 1 0 0 0 E 0 1 1 1 0 0 E 0 0 1 0 0 E
0
0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 E -E 0 1 1 0 -E E
-E
0 1 1 1 -E 0 0 1 0 0 -E 0 1 1 0 1 0 -E 0 0 0 1 0 -E
-2E 0 1 0 1 -E -E
52
4.3.2 Cascaded H-Bridge Inverter with Unequal DC voltage
To operate a seven level cascaded
multilevel converter consider two
unequal dc sources, the magnitude of
voltage of first dc source is E and the
second DC source is 2E. With unequal
DC voltages, the number of voltage
levels can be increased without
necessarily increasing the number of
H-bridge cells in cascade. This allows
more voltage steps in the inverter
output voltage waveform for a given
number of power cells. Figure 4-7
shows two inverter topologies,
where the dc voltages for the H- bridge cells are not equal. In the seven-level
topology, the dc voltages for H1H2 are E and 2E, respectively. The two-cell
inverter leg is able to produce seven voltage levels: 3E, 2E, E, 0, –E, –2E, and
–3E. The relationship between the voltage levels and their corresponding
switching states is summarized in Table. In the nine-level topology, the dc
voltage of H2 is three times that of H1. All the nine voltage levels can be
obtained by replacing the H2 output voltage of VH2 = ±2E in Table with VH2 =
±3E and then calculating the inverter phase voltage VAN.
Figure 4-7: One leg with unequal DC voltage
53
Switching table for 7 level CHB inverter:
Table 4-6: Switching table for 7 level unequal DC CHB inverter
Output Voltage
VAN
Switching State VH1 VH1
S11 S31 S12 S32
3E 1 0 1 0 E 2E
2E 1 1 1 0 0 2E 0 0 1 0 0 2E
E 1 0 1 1 E 0 1 0 0 0 E 0 0 1 1 0 -E 2E
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0
-E 1 0 0 1 E -2E 0 1 1 1 -E 0 0 1 0 0 -E 0
-2E 1 1 0 1 0 -2E 0 0 0 1 0 -2E
-3E 0 1 0 1 -E -2E
54
5 Multilevel Inverter PWM schemes
Carrier based PWM schemes:
The carrier-based modulation schemes for multilevel inverters can be
generally classified into two categories: phase-shifted PWM and level-shifted
PWM.
Both modulation schemes can be applied to the CHB inverters.
Figure 5-1: Level-shifted PWM for a Seven-level CHB inverter
(mf = 15, ma = 0.8, fm = 50 Hz and fcr = 900 Hz)
55
5.1 Level Shifted Sine PWM scheme
For carriers signals, the time values of each carrier waves are set to [0
1/600 1/300] while the outputs values are set according to the disposition of
carrier waves.
After comparing, the output signals of comparator are transmitted to the
IGBT. It requires (m-1) triangular carriers, all having the same frequency and
amplitude. The frequency modulation index is given by mf = fcr/fm. The
switching frequency of the inverter using the level-shifted modulation is equal
to the carrier frequency, that is, (device switching frequency) fC = fcr. Average
device switching frequency is device switching frequency) fC = fcr/ (m – 1).The
conduction time of the devices is not evenly distributed either.
𝑚𝑎 = ��𝑚
��𝑚(𝑚 − 1) 𝑓𝑜𝑟 0 ≤ 𝑚𝑎 ≤ 1
Where, 𝑉�� is the peak amplitude of the modulating wave 𝑉�� and ��cr is
the peak amplitude of each carrier wave.
56
5.2 Types of Level Shifted Sine PWM
5.2.1 In-Phase Disposition IPD
In-Phase Disposition (IPD), where all carriers are in phase.
All the carrier signals are in phase.
Figure 5-2: Switching pattern produced using the IPD carrier-based PWM scheme:
(a) Two triangles and the modulation signal (b) S1RY (c) S2RY (d) S1RN (e) S2RN
57
5.2.2 Alternative Phase opposite Disposition APOD
Alternative Phase Opposite Disposition (APOD), where all carriers are
alternatively in opposite disposition.
All the carriers above zero reference are in phase but are in opposition
with those below zero reference.
Figure 5-3: Simulation of carrier-based PWM scheme using APOD for a five-level inverter. (a) Modulation signal and carrier waveforms
(b) Phase “R” output voltage
58
5.2.3 Phase Opposite Disposition POD
Phase Opposite Disposition (POD), where all carriers above the zero
reference are in phase but in opposition with those below the zero reference.
The modulating signal of each phase is displaced from each other by 120°.
All the carrier signals have same frequency FC and amplitude AC while the
modulating signal has a frequency of fm and amplitude of Am. The fc should be
in integer the multiples of fm with three-times. This is required for all the
modulating signal of all the three phases see the same carriers, as they are 120°
apart. The carrier waves and the modulating signals are compared and the
output of the comparator defines the output in the positive half cycle the
comparator output will have the value high, if the amplitude of the modulating
Figure 5-4: Simulation of carrier-based PWM scheme using POD.
(a) Modulation signal and phase carrier waveforms (b) Phase “R” output voltage.
59
signal is greater than that of the carrier wave and zero otherwise. Similarly for
the negative half cycle, if the modulating signal is lower than the carrier wave
the output of the comparator is high and zero otherwise.
5.3 Phase Shifted Sine PWM scheme
In Phase Shifted Sine PWM all the triangular carriers have the same
Figure 5-5: Phase-shifted PWM for seven-level CHB inverters (mf = 3, ma = 0.8, fm = 50 Hz, and fcr = 180 Hz).
60
frequency and same peak-peak amplitude .but there is a phase shift between
any two adjacent carrier waves. For m Voltage levels (m-1) carrier signals are
required and they are phase shifted with an angle of θ= (360°/m-1). The gate
signals are generated with proper comparison of carrier wave and modulating
signal.
In general, a multilevel inverter with m voltage levels requires (m – 1)
triangular carriers In the phase-shifted multicarrier modulation, all the
triangular carriers have the same frequency and the same peak-to-peak
amplitude, but there is a phase shift between any two adjacent carrier waves,
given by PhCR = 360°/(m – 1).
61
6 Simulations
Simulations are major here mainly are done through PSIM, except for Space
Vector PWM and their related comparison cases which need computational and
algorithmic calculations which cannot be meet through PSIM. MATLAB Simulink
modelling is done and used for such cases.
Simulations are done to observe the output waveform, calculate the Total
harmonic Distortion THD, perform FFT analysis and observe the dominant
harmonics created and derive conclusions accordingly. Various PWM
techniques are also compared on the basic of their THDs, Data bus utilizations
and other parameters.
6.1 Simple PWM with Three phase Inverter
Figure 6-1: Sinusoidal PWM
62
Figure 6-1 shows Gate pulses created by comparator action between the
carrier wave and the reference sinusoidal waves of R, Y and B phases.
Figure 6-2 shows Line voltage, phase voltage and line current for VDC =
540V. Observed voltages are Vph = 230V and VL= 400V for fC = 2 kHz & ma= 1.
6.2 Space Vector PWM for three phase Inverter
Figure 6-2: ma=1 VDC= 540V fC = 2 kHz
Figure 6-3: Simulink model used for Space Vector PWM
63
Following SVPWM simulation curves are based on input VDC =500V; ma = 0.8; fC = 2 kHz
Figure 6-4: phase Voltage Vph = 230V
Figure 6-5: line Voltage VL = 400V
Figure 6-6: line current waveform
64
Figure 6-8: THD analysis without filter
Figure 6-7: THD analysis with filter
65
6.3 Comparison between SPWM and SVPWM
THD analysis of SVPWM and SPWM were compared and tabulated from table
6-1 to 6-3. It was observed that SVPWM generates lesser THD for every
corresponding SPWM for any given ma.
Table 6-1: SVPWM comparison for different modulation index
Table 6-2: SVPWM and SPWM comparison for different modulation index Without filter
Table 6-3: SVPM and SPWM comparison for different modulation index With filter
ma VL RMS VL THD VPH THD IL THD
1 400 52.48 % 52.62 % 1.63 %
0.8 356.8 76.84 % 76.89 % 1.72 %
0.6 308.8 106.06 % 106.07 % 2.07 %
ma SVPWM SPWM
VL THD IL THD VL THD IL THD
1 52.48 % 1.63 % 69.56 % 2.51 %
0.8 76.84 % 1.72 % 91.00 % 2.94 %
0.6 106.06 % 2.07 % 122.00 % 3.59 %
ma SVPWM SPWM
VL THD IL THD VL THD IL THD
1 4.00 % 0.23 % 4.93 % 0.20 %
0.8 4.25 % 0.17 % 5.14 % 0.26 %
0.6 5.12 % 0.17 % 5.82 % 0.29 %
66
Figure 6.7 & 6.8 plots the variation of THD voltage as we vary the ma (amplitude
modulation index) for both SVPWM and SPWM.
Fig 6.7 is done without filter addition and while fig 6.8 values represents the
results with the addition of a filter circuit.
1 0.8 0.6
SVPWM 52.51 76.9 106.06
SPWM 69.56 91 122
52.51
76.9
106.06
69.56
91
122
40
50
60
70
80
90
100
110
120
130
140
Lin
e V
olt
age
THD
ma
THD vs ma without filter
1 0.8 0.6
SVPWM 4 4.25 5.12
SPWM 4.93 5.14 5.82
4
4.25
5.12
4.93
5.14
5.82
3.5
3.7
3.9
4.1
4.3
4.5
4.7
4.9
5.1
5.3
5.5
5.7
5.9
6.1
Lin
e V
olt
age
THD
THD vs ma with filter
Figure 6-9: THD vs ma without filter comparison between SVPWM and SPWM
Figure 6-10: THD vs ma with filter comparison between SVPWM and SPWM
67
6.4 Simulation of 5-level Cascaded Inverter
The 5 level cascaded Inverter is basically obtained by cascading of 2 H-
Bridges in each phase legs. Pulse triggering is done via 2 methods, Phase shifted
sine PWM and Level shifted Sine PWM. Simulations on both are done as shown
in the next sections.
6.4.1 Multilevel Phase shifted Sine PWM Inverter
The simulation of phase shifted Sine PWM as done as shown in the figure 6-12.
The parameter setting was as below-
VDC-1 = 100V VDC-2 = 100V
ma = 0.8 mf = 15 i.e. fC = 750Hz
Figure 6-12 follows the said parameters.
Figure 6-11: PSIM simulation model for 5 level cascaded H-bridge Inverter
68
Accordingly we obtain the following values-
RMS VL = 252.13V RMS Vph= 146.42V
THD Vph = 38 % THD VL = 29 %
Figure 6-12: Phase shifted Sine PWM – a) Phase shifted carrier waves with input phase sine waves
b) Phase voltage VRN c) Line Voltage VRY
69
6.4.2 Multilevel level shifted Sine PWM Inverter
Simulation for all three types of Level shifted Sine PWM were performed,
namely IPD, POD and APOD. Which are shown in the subsequent following
diagrams. VDC used is 100V for all thee.
Figure 6-13 IPD gives the following results:
RMS Vph= 120.73V THD Vph= 38.28 %
RMS VL= 200V THD VL= 21.7 %
Figure 6-14 POD gives the following results:
RMS Vph= 120.41V THD Vph= 37.52 %
RMS VL= 207.84V THD VL= 35.17 %
Figure 6-13: IPD (In phase Disposition)
Figure 6-14: POD (Phase opposite Disposition)
70
Figure 6-15 APOD gives the following results:
RMS Vph= 121.41V THD Vph= 36.48 %
RMS VL= 204.62V THD VL= 30 %
Comparing all three methods, IPD was observed as the better option,
which has lower VL THD value compared to POD and APOD.
Figure 6-15: APOD (Alternate Phase opposite Disposition)
71
6.5 Simulation of 7-level Cascaded Inverter by
Unequal DC voltages
The 7 level simulation of cascaded Inverter by Unequal DC voltage is shown
in figure 6-16.
Parameters set during simulation of 7 level cascaded Inverter by unequal
DC voltages-
VDC-1 = 100V; VDC-2 = 200V; fC = 750Hz; ma = 0.8
Following values were obtain from the simulation-
RMS VL = 311.71V RMS Vph = 185V
THD VL=44.15 % THD Vph = 35.53 %
Figure 6-16: 7 level cascaded inverter with Unequal DC voltage
72
THD values obtained for unequal DC voltage source are more than that
for equal voltage source CHB inverter, but the VRMS obtained is greater in this
case.
6.6 Comparison between phase shifted and level
shifted
Table 6-4: Comparison between phase shifted and level shifted
Table 6-5: THD (%) Analysis of Line Voltages of CHB Inverter
Based on Different Schemes
Comparison Phase Shifted Modulation
Level Shifted Modulation (IPD)
Device switching frequency
Same for all devices Different
Device conduction period Same for all devices Different
Rotating of switching patterns
Not required Required
Line to line voltage THD Good Better
Comparison Phase Shifted Modulation
Level Shifted Modulation (IPD)
Device switching frequency
Same for all devices Different
Device conduction period Same for all devices Different
Rotating of switching patterns
Not required Required
Line to line voltage THD Good Better
73
Table 6-6: THD (%) Analysis of Line Voltages of CHB Inverter based on Different Schemes at mf=20 VDC=100V
ma Phase shifted IPD 7 level- 2 cell ( unequal DC)
1 25 16.9 27.65
0.8 25 21.73 36.01
0.6 27 25.5 40.72
0.4 68 25.57 79.61
0.2 68.6 25.59 153.55
0.2 0.4 0.6 0.8 1
Phase Shifted PWM 68.6 68 27 25 25
In Phase Disposition 25.59 25.57 25.5 21.73 16.9
7 level 2 Cell 153.55 79.61 40.72 36.01 27.65
68.6 68
27 25 2525.59 25.57 25.5 21.73 16.9
153.55
79.61
40.72 36.0127.65
10
30
50
70
90
110
130
150
Vo
ltag
e TH
D
fs=1kHz (frequency of Switching device) Five Level Inverter
Figure 6-17: THD plot between different PWM schemes
74
6.7 Conclusions
Two multicarrier based PWM schemes, the phase- and level-shifted
modulations, are presented. Various aspects associated with the modulation
schemes for the CHB multilevel inverters are discussed, which include gate
signal arrangements, spectrum analyses, and THD profiles. The performance of
the modulation schemes is compared.
PWM strategies viz. SPWM and SVPWM are implemented in
MATLAB/SIMULINK software and its performance is compared with
conventional PWM techniques. Owing to their fixed carrier frequencies fC in
conventional PWM strategies, there are cluster harmonics around the multiples
of carrier frequency. PWM strategies viz. Sinusoidal PWM and SVPWM utilize a
changing carrier frequency to spread the harmonics continuously to a wideband
area so that the peak harmonics are reduced greatly.
In this project first comparative analysis of Space Vector PWM with
conventional SPWM for a two level Inverter is carried out. The Simulation study
reveals that SVPWM gives 15% enhanced fundamental output with better
quality i.e. lesser THD compared to SPWM.
75
7 References
1. W. A. Hill and C. D. Harbourt, “Performance of Medium Voltage Multilevel Inverters”,
IEEE Industry Applications Society (IAS) Conference, Vol. 2, pp. 1186–1192, 1999.
2. P. W. Hammond, “A New Approach to Enhance Power Quality for Medium Voltage AC
Drives”, IEEE Transactions on Industry Applications, Vol. 33, No. 1, pp. 202–208, 1997.
3. P.S. Bhimbra, “Power Electronics”, 2 ed., New Delhi, Khanna Publications, 2004.
4. G. Narayanan, IISc(Bangalore), Lectures on “Pulse width Modulation for Power
Electronic converters’” NTPEL
5. Muhammad H. Rashid, “Power Electronics Circuits, devices, and Applications”,
Prentice-Hall of India Private Limited, Third Edition, 2004.
6. N. Mohan, T. M. Undeland, et al, “Power Electronics - Converters, Applications and
Design”, 3rd edition, John Wiley & Sons, New York, 2003.
7. Hong Hee Lee, Phan Quoc Dzung, Le Dinh Khoa, Le Minh Phuong & Huynh Tan Thanh,
“The adaptive space vector PWM for four switch three phase inverter fed induction
motor with DC – Link Voltage Imbalance” in Hong School of Electrical Engineering,
University of Ulsan, Korea, 2008, IEEE, DOI: 10.1109/TENCON.2008.4766516
8. Kapil Jain, Pradyumn Chaturvedi, “MATlab -based Simulation & Analysis of Three -
level SPWM Inverter”, International Journal of Soft Computing and Engineering
(IJSCE), March 2012, Volume-2, Issue-1.
9. Moin Sheik, “Multilevel Inverter topologies and control scheme” [Online],
Available:https://www.academia.edu/6742849/Multilevel_Inverter_3-
level_topologies_Diode_and_capacitor_clamped_and_controlscheme_spwm
10. Hind Djeghloud and Hocine Benalla, “Space Vector Pulse Width Modulation Applied
to Three-Level Voltage Inverter”, 5th International Conference on Technology and
Automation ICTA’05, Thessaloniki, Greece, Oct 2010.
11. Jae Hyeong Seo, Chang Ho Choi, Dong Seok Hyun, “A New Simplified space-Vector
PWM Method for Three-Level Inverters”, IEEE Transactions on Power Electronics,
Volume 16, Issue 4, July 2010, Pages 545 – 550.
12. Dong-Myung Lee, Jin-Woo Jung, and Sang-Shin Kwak, “Simple Space Vector PWM
Scheme for 3-level NPC Inverters Including the Over modulation Region”, Journal of
Power Electronics, Vol. 11, No. 5, September 2011.
76
8 Appendices
8.1 Appendix 1- List of Figures
Figure 2-1: Voltage source inverter................................................................. 10
Figure 2-2: Current source inverter................................................................. 11
Figure 2-3: Current source inverter................................................................. 12
Figure 2-4: Basic three phase inverter ............................................................ 13
Figure 3-1: PWM Duty cycle comparison ........................................................ 18
Figure 3-2: Bipolar Sine PWM ......................................................................... 21
Figure 3-3: Unipolar Sine PWM ....................................................................... 21
Figure 3-4: Coordinate Transformation RYB to d-q ......................................... 24
Figure 3-5: Three phase inverter ..................................................................... 25
Figure 3-6: VREF rotating along Voltage Space Vectors..................................... 26
Figure 3-7: Equivalent Switching pattern of the space vectors ....................... 27
Figure 3-8: Space Vector Diagram ................................................................... 27
Figure 3-9: Sector Distribution ........................................................................ 28
Figure 3-10: Sector 1 VREF approximation over a sampling time .................... 29
Figure 3-11: Switching Sequence for all VREF pattern in sector (only T1 T2 T0
varies) ............................................................................................................. 30
Figure 3-12: Graphical switching pattern for different sectors ....................... 30
Figure 3-13: Switching plots for all 6 sectors................................................... 34
Figure 3-14: Switching states of the inverter .................................................. 36
Figure 3-1: Typical Inverter Display panel ....................................................... 38
Figure 4-2: Types of Multilevel Inverter .......................................................... 41
Figure 4-3: Topology of the diode-clamped inverter (a) three-level inverter, . 42
Figure 4-4: Topology of the Flying Capacitor Multilevel inverter .................... 44
Figure 4-5: a) Inverter Single Stage b) 5 level Cascaded Inverter .................... 47
Figure 4-6: CHB with equal DC voltage ................Error! Bookmark not defined.
Figure 4-7: One leg with unequal DC voltage .......Error! Bookmark not defined.
Figure 5-1: Level-shifted PWM for a ............................................................... 54
Figure 5-2: Switching pattern produced.......................................................... 56
Figure 5-3: Simulation of carrier-based PWM scheme using APOD for a five-level
inverter. (a) Modulation signal and carrier waveforms ................................... 57
77
Figure 5-4: Simulation of carrier-based PWM scheme .................................... 58
Figure 5-5: Phase-shifted PWM for seven-level CHB inverters ........................ 59
Figure 6-1: Sinusoidal PWM ............................................................................ 61
Figure 6-2: ma=1 VDC= 540V fC = 2 kHz ............................................................. 62
Figure 6-3: Simulink model used for Space Vector PWM ................................ 62
Figure 6-4: phase Voltage Vph = 230V .............................................................. 63
Figure 6-5: line Voltage VL = 400V ................................................................... 63
Figure 6-6: line current waveform .................................................................. 63
Figure 6-7: THD analysis with filter ................................................................. 64
Figure 6-8: THD analysis without filter ............................................................ 64
Figure 6-9: THD vs ma without filter comparison between SVPWM and SPWM
....................................................................................................................... 66
Figure 6-10: THD vs ma with filter comparison between SVPWM and SPWM . 66
Figure 6-11: PSIM simulation model for 5 level cascaded H-bridge Inverter ... 67
Figure 6-12: Phase shifted Sine PWM – .......................................................... 68
Figure 6-13: IPD (In phase Disposition) ........................................................... 69
Figure 6-14: POD (Phase opposite Disposition) ............................................... 69
Figure 6-15: APOD (Alternate Phase opposite Disposition) ............................. 70
Figure 6-16: 7 level cascaded inverter with Unequal DC voltage .................... 71
Figure 6-17: THD plot between different PWM schemes ................................ 73
78
8.2 Appendix 2-List of Tables
Table 3-1: Switching time for each sector 1-6 ................................................. 35
Table 3-2: Output Voltage table ..................................................................... 37
Table 4-1: Comparison between Conventional Inverters ................................ 39
Table 4-2: Switching sequence for 5 level Diode Clamped Inverter ................ 42
Table 4-3: Switching sequence for 5 level Inverter ......................................... 46
Table 4-4: Comparison of multilevel inverter Topologies ............................... 48
Table 4-5: Switching table for 5 level .............................................................. 51
Table 4-6: Switching table for 7 level unequal DC CHB inverter ...................... 53
Table 6-1: SVPWM comparison for different modulation index ..................... 65
Table 6-2: SVPWM and SPWM comparison for different modulation index ... 65
Table 6-3: SVPM and SPWM comparison for different modulation index....... 65
Table 6-4: Comparison between phase shifted and level shifted .................... 72
Table 6-5: THD (%) Analysis of Line Voltages of CHB Inverter ......................... 72
Table 6-6: THD (%) Analysis of Line Voltages of CHB Inverter based on Different
Schemes at mf=20 VDC=100V ........................................................................... 73