8/6/2019 Final Uart

1/19

8/6/2019 Final Uart

2/19

Serial CommunicationIntroduction

Serial communication buses

Asynchronous and

synchronous communication

UART block diagram

UART clock requirements

Transmitter and receiver operation

Operation modes in UART

8/6/2019 Final Uart

3/19

Parallel communication implies sending awhole byte (or more) of data over multipleparallel wires

Serial communication implies sending databit by bit over a single wire

There are 2 types of serial communication: Asynchronous

Synchronous

8/6/2019 Final Uart

4/19

8/6/2019 Final Uart

5/19

In the synchronous mode, the transmitter and receiver share acommon clock

The transmitter typically provides the clock as a separate signal inaddition to the serial data

Transmitter Receiver

Data

Clock

The Receiver

j Extracts the data using

the clock provided by

the transmitter

j Converts the serial data

back to the parallel

form

The Transmitter

j Shifts the data onto the

serial line using its own clock

j Provides the clock as a

separate signal

j No start, stop, or parity bits

added to data

1 byte-wide Data 1 byte-wide Data

8/6/2019 Final Uart

6/19

Asynchronous transmission is easy to implement but lessefficient as it requires an extra 2-3 control bits for every8 data bits

This method is usually used for low volume transmission

D0 D1 D2 D3 D4 D5 D6 D7

Start Bit 1 or 2 Stop BitsParity Bit

1 Asynchronous Byte

8/6/2019 Final Uart

7/19

Start bitindicates the beginning of the data word

Stop bitindicates the end of the data word

Parity bitadded for error detection (optional)

Data bitsthe actual data to be transmitted

Baud ratethe bit rate of the serial port

Throughputactual data transmitted per sec (total bits transmittedoverhead)

Example: 115200 baud = 115200 bits/sec

If using 8-bit data, 1 start, 1 stop, and no parity bits, the effectivethroughput is: 115200 * 8 / 10 = 92160 bits/sec

8/6/2019 Final Uart

8/19

UART

Universal Asynchronous Receiver TransmitterSerial Data Transmission

8/6/2019 Final Uart

9/19

8/6/2019 Final Uart

10/19

Microcontroller waits until TDRE = '1'

Loads data into TDR

Clears TDRE

UART transfers data from TDR to TSR Sets TDRE

UART outputs start bit ('0') then shifts TSR

right eight times followed by a stop bit ('1')

8/6/2019 Final Uart

11/19

418_11

Transmitter SM Chart

8/6/2019 Final Uart

12/19

UART waits for start bit

Shifts bits into RSR

When all data bits and stop bit are received

RSR loaded into RDR

Set RDRF

Microcontroller waits until RDRF is set

Read RDR

Clear RDRF

8/6/2019 Final Uart

13/19

8/6/2019 Final Uart

14/19

Receiver SM Chart

8/6/2019 Final Uart

15/19

Advantage:

The data transfer is through single wire so noneed to use number of wires.

Disadvantage:The data transfer is slow.

8/6/2019 Final Uart

16/19

commonly used technique for controlling

power to inertial electrical devices

8/6/2019 Final Uart

17/19

8/6/2019 Final Uart

18/19

Telecommunications

Power delivery

Voltage regulation

8/6/2019 Final Uart

19/19