finding the missing memristor · logic layer cmos layer for control cache layer storage layer(s)...

© Copyright 2010 Hewlett-Packard Development Company, L.P. 1 © Copyright 2010 Hewlett-Packard Development Company, L.P.

Stan Williams

HP Senior Fellow

Finding the Missing Memristor

© Copyright 2010 Hewlett-Packard Development Company, L.P. 2

2

Acknowledgments People who did the work:

Over 60 current and former members

of the IQS Lab and 40 members of

other HP orgs –

esp. Greg Snider, Phil Kuekes,

Duncan Stewart, Dimitri Strukov,

Matthew Pickett, Julien Borghetti,

Jianhua Yang, John Paul Strachan,

Gilberto Ribeiro & many others!

Our partners at LBNL and NIST

Supported in part by DARPA


Memristor & NDR

Circuit ECC

Device Physics and Mathematical Model

Architecture and Circuit Design

Within Specs?


THE COMMERCIAL EFFORT

Janice Nickel with first 300 mm memristor wafer


Tunneling Probability Depends

Exponentially on the

Barrier Width and Height -

Molecular isomerization leads to switching

Tunneling Gap

Bar

rier

Hei

gh

t

Tunneling Gap

Bar

rier

Hei

gh

t

meta

l ele

ctr

ode

meta

l ele

ctr

ode

meta

l ele

ctr

ode

meta

l ele

ctr

ode

Slide from a talk given in 2002


Hysteretic switch: on/off states

S

S

S

S

S M

e

N

O

O

S

O

O

O

O

O

M e O

O

O

M e O

O

O

M e O

O

O

O

O

S

N

N

N

N +

+

+

+

4 P

F 6 —

-10x10-3

-5

0

5

10

Cu

rre

nt (A

)

-2.0 -1.0 0.0 1.0

Voltage (V)

voltage-configured on/off switch


The “sharp right turn”

Courtesy: Fuller, et al. National Academy of Science Report 2010

Single core performance plateauing after decades of exponential growth !

© Copyright 2010 Hewlett-Packard Development Company, L.P. 8 © Copyright 2010 Hewlett-Packard Development Company, L.P. 8

Memristor History


3 FUNDAMENTAL PASSIVE LINEAR CIRCUIT ELEMENTS

RESISTOR v = R i

CAPACITOR q = C v

INDUCTOR φ = L i

Capacitor - 1745

Volta / von Kleist & van Musschenbroek

Benjamin Franklin

Inductor – 1831

Michael Faraday

Joseph Henry

Resistor – 1827

Georg Ohm


CHUA DEFINED THE MEMRISTOR IN 1971 BUT DID NOT KNOW A PHYSICAL EXAMPLE

RESISTOR dv = R di

CAPACITOR dq = C dv

INDUCTOR dφ = L di

MEMRISTOR dφ = M dq

dq /dt = i

dφ

/dt =

v

i q

v

φ

“Memristor - the missing circuit element,”

IEEE Trans. Circuit Theory 18, 507 (1971)

Formal mathematical proofs:

Not physics based

No causality implied by definition

Relation between φ and q an effect,

not the cause, of memristance!

M is a “memory resistor” –

it is a nonvolatile resistive memory!

Proved that no equivalent circuit to M could be made using any R, C and L – is a new and unique „basis function‟

Built equivalent circuit using transistors


EXPANDED THE CONCEPT TO „MEMRISTIVE SYSTEM‟ IN 1976

( )v R w i

( )dw

f idt

L. O. Chua, “Memristor - the missing circuit element,” IEEE Trans. Circuit Theory 18, 507–519 (1971).

L. O. Chua and S. M. Kang, "Memristive devices and systems," Proc. IEEE, 64 (2), 209-23 (1976).

RESISTOR dv = R,di

CAPACITOR dq = C dv

INDUCTOR dφ = L di

MEMRISTOR dφ = M dq

dq /dt = i

dφ

/dt =

v

i q

v

φ

MEMRISTIVE SYSTEMS

The pinched hysteresis loop

Rigorous mathematical definition

© Copyright 2010 Hewlett-Packard Development Company, L.P. 12 12

Resistor

Curr

ent

Capacitor

Inductor

Voltage

Curr

ent

Memristor

Voltage

dv = R di dq = C dv

dφ = L di dφ = M dq

Voltage

Time

Curr

ent

What makes a memristor “fundamental”? The inability to duplicate it‟s properties with the other passive circuit elements


RERAM IS A MEMRISTOR


14

Metal Oxide Resistive Switches: observation of pinched hysteresis

“Memory effects” in oxides

have been known for decades:

G. Dearnaley et al., Rev. Prog. Phys. (1970):

a review with 150+ references

Just a few recent

references: metal:

S. Seo et al., APL (2003) Ni

B. J. Choi et al., JAP (2005) Ti

H. Sim et al., Microel. Eng. (2005) Nb

D. Lee et al., EDL (2005) Zr

A. Chen et al., IEDM’05 Cu

M. Kund et al., IEDM’05 Ag

D. C. Kim et al., APL (2006) Nb

N. Banno et al., IEICE TE (2006) Cu(S)

T.-N. Fang et al., ICMTD’07 Cu

L. Courtade et al., ICMTD’07 Ni

W. Guan et al., APL (2007) Zr

S.-W. Kim & Y. Nishi, NVMTS’07 Cu(S)

D. Stewart, NVMTS’07 Ti

K.-C. Liu et al., NVMTS’07 Hf

D. Lee et al., APL (2007) Mo

Percentage

2.28%

Current (uA)

0.005 0.01 0.05 0.1 0.5 1 5 10

-2

-1

0

1

2

15.9%

50.0%

84.1%

97.7%

Percentage

2.28%

Current (uA)

0.005 0.01 0.05 0.1 0.5 1 5 10

-2

-1

0

1

2

15.9%

50.0%

84.1%

97.7%

ON OFF

With time, data are becoming more reproducible:

A. Chen et al. (IEDM’05)

Just a few examples:

B. J. Choi et al. (2005) D. Lee et al. (2007)

-2 0 2 4-20.0µ

-10.0µ

0.0

10.0µ

20.0µ

30.0µ

40.0µ

50.0µ

Cu

rre

nt

(A)

Voltage (V)

Ilim set by transistor Vg

OFF-stateVTFL

2

2LeNV t

TFL

ON-state: SCLC

with shallow

traps

-2 0 2 4-20.0µ

-10.0µ

0.0

10.0µ

20.0µ

30.0µ

40.0µ

50.0µ

Cu

rre

nt

(A)

Voltage (V)

Ilim set by transistor Vg

OFF-stateVTFL

2

2LeNV t

TFL

ON-state: SCLC

with shallow

traps

A. Chen et al. (2005)

Cu

Cu2O

TE

slide courtesy K. Likharev


OUR SWITCHING DEVICES: PT/TIO2/PT

Top electrode

Bottom electrode

~30 nm TiO2

15 nm Pt

15 nm Pt

5 nm Ti

• Dimensions: 30 nm – 16 μm

-200

-100

0

100

200

Curr

en

t (

uA

)

-2 -1 0 1 2Voltage ( V )

10-9

10-7

10-5

-2.0 -1.0 0.0 1.0

OFF

ON


DRIFT, DIFFUSION AND THERMOPHORESIS


Vacancy Drift Model of Bipolar TiO2 ReRAM physical model has to be consistent with memristor equations!

– Semiconducting TiO2 Bipolar Switch

Previously: fixed semiconductor structure and only electronic motion.

Now: ionic motion dynamically modulates the semiconductor structure

controlling the electronic current.

ONV

( )( )

Rdw ti t

dt L

ONV( ) ( )

Rw t q t

L

)()(

1)(

)( ONOFF tiL

twR

L

twRtv

D. Strukov et al., Nature (May 1, 2008)

Pt Pt TiO2 TiO2-x

w(t1)

Pt Pt TiO2 TiO2-x

w(t2)

Drift velocity

State variable w is the drift front

)(1)(

2

ONV

OFF tqD

RRq

M

L

© Copyright 2010 Hewlett-Packard Development Company, L.P. 18 18

-

-

-

-

- +

+ +

+ + +

+ +

+

+ +

+

+ +

mobile

donors

fixed

acceptors

electronic

current

V I

+

Electrons: ∙(-en(x) μn φn(x)) = 0

Holes: ∙(ep(x) μp φp(x)) = 0

Ions: -∙(- eDi ND(x) - eND(x) μi E0sinh[φ(x)/E0]) = e

∂ND(x)/∂t

Poisson: -εε0∆φ(x) = e[p(x)-n(x)+ fD(x) ND(x) - fA(x) NA]

- Ohmic interfaces for electrons

- Blocking interfaces for ions

- Switch in a nanosecond, store for >10 years

Coupled Ionic-Electronic Drift-Diffusion Model

Strukov et al, Small (2009)

Store information as the positions of atoms


x x+a

(a)

(c)

Vn

T

UA

TakB

Eaq

(b)

Factors affecting switching

Fick diffusion –

Concentration gradient

Limits state lifetime

Drift –

Potential gradient

Bipolar switching speed

Thermophoresis –

Temperature gradient

Unipolar switching


DRIFT – DIFFUSION MODEL OF BIPOLAR SWITCHING

Off switching:

wON

doped undoped

w(t)

L

V

D. Strukov et. al, Small 2009, 5, No. 9, 1058–1063

Slow – diffusion opposes drift Fast – diffusion aids drift


metal

insulator

(a)

(b)

metal

insulator

1

0.1

10

0.01

1

0.1

10

0.01

Vac

ancy

co

nce

ntr

atio

n (

nV/n

M)

0 1 Radius (r/R)

0 1 Radius (r/R)

timetime

time

Time (ln[t/τ])

01inf

-1-2-3-4

initial

Time (ln[t/τ])

inf210

initial

Vac

ancy

co

nce

ntr

atio

n (

nV/n

M)

metal

insulator

(a)

(b)

metal

insulator

1

0.1

10

0.01

1

0.1

10

0.01

Vac

ancy

co

nce

ntr

atio

n (

nV/n

M)

0 1 Radius (r/R)

0 1 Radius (r/R)

timetime

time

Time (ln[t/τ])

01inf

-1-2-3-4

initial

Time (ln[t/τ])

inf210

initial

Vac

ancy

co

nce

ntr

atio

n (

nV/n

M)

Thermophoresis-induced radial switching

Vacancies „breath‟ in and out of a conducting channel

The origin of „unipolar‟ switching

Strukov and Williams, submitted


Figure 2

t4

t3

t2

t1

VO source/sink electrode

xL0 xOFF xON

w(t)wOFF wOFF

Analytical solution to drift-diffusion equation (solid lines)

2

1/ 2

1 1( , ) 1 exp 1

4 2 24

x

S S

x t x tN x t N dx N erfc

Dt DtDt

10

100

1000

104

105

106

0

0.5

1

1.5

2

-5 -4.5 -4 -3.5 -3 -2.5

t v(s)

0

0.2

0.4

0.6

0.8

1

Sw

itchin

g p

roba

bili

ty -4.75V

-4.5V

-4.25V -4.0V -3.75V

-3.5V

-3.25V

-3V

-2.75V

(a)

0

0.2

0.4

0.6

0.8

1

1 10 100 1000 104

105

106

107

Sw

itch

ing p

rob

ab

ility

Cumulative time (s)

7V 6.5V

6V

5.5V

5V 4.5V

4V

3.5V

(c)

10

100

1000

104

105

106

0

0.4

0.8

1.2

1.6

2

4 5 6 7

t v(s)

External bias (Volts)

(b)

(d)

2

ln[ ]1( ; , )

2 2 4

V V

OFF

w

w k b tP t V w erfc

Dt


MOLECULAR DYNAMICS SIMULATION

Simple 2D model of O vacancies in TiO2

Red Dots – O vacancies

Blue Background – TiO2

Vacancy attractions cause „filaments‟


How to Measure and Model

a Memristor


1.0

0.5

0.0

V in

t (V

) (c)

40

20

0

I (µ

A)

3 2 1 0 -1

State-Test Protocol: must keep time stamp Memristors are dynamical devices!

Example time series

State Evolution State Test

10 -6

10 -5

10 -4

10 -3

I (A

)

-0.1 -1 V (V)

t = 0s

110 ms

790 ms

0.1 1

4.7ms 28 ms 160ms

970ms 5.7s 33s

t

State Data and I-V Fit to

Simmons Tunneling Equation

– Time series of I-V tests taken during the 4.5V OFF–switching state test

– Lines on state data are best fits to a series resistor RS plus Simmons tunnel barrier

– Conduction model extrapolates well to high positive voltage

Matthew Pickett et al., J. Appl. Phys. 106, 074508 (2009)


STATE VARIABLE TIME EVOLUTION

Analytical approximations (lines) accurately represent device dynamical

behavior (data points).

Extremely non-linear dynamics come from exponential I-V and drift

1.8

1.6

1.4

1.2

w (n

m)

10 -5 10

-3 10 -1 10

1

t (s)

3.0 3.5 4.0

4.5 5.0 5.5

cc

ON

ON

ONw

w

b

i

w

aw

i

ifw

absexpexpsinh

ON switching: OFF switching:

cc

OFF

OFF

OFFw

w

b

i

w

aw

i

ifw

absexpexpsinh

Applied V

1.8

1.7

1.6

1.5

1.4

w (

nm

)

10 -5 10

-3 10 -1

t (s)

-1.25 -1.25 -1.25

-1.4 -1.4

Applied V

Matthew Pickett et al., J. Appl. Phys. 106, 074508 (2009)


-1 -0.5 0 0.5 1 1.5-1000

-500

0

500

1000

1500

2000

Vmem

(V)

i me

m (

A)

0 2 4 6-4

-2

0

2

4

6

t (s)

Vext

SPICE MODEL


STRUCTURAL MODEL

– Four Point measurement device

schematic including

• Metallic channel

• tunnel barrier

– Typical device in study

• negative polarity turns device ON

• positive polarity turns device OFF

V Ti4O7

w

Pt

Pt

(a)

S

A 10

-8

10

-6

10

-4

-2 0 2

(b) I (A)

Vint (V)

OFF ON

Voltage

Source

Current

Amplifier

Voltage

Amplifier

Metallic

Channel

Tunnel Barrier

Width

(state variable)

Conducting Channel

Series Resistance (fit)

TiO2

TiO2-x


Materials Characterization


3.2µm

AFM Direct Observation of the Conducting Channel

AFM

TE

After forming a device, we can peel off the top

electrode. With AFM, we see the conducting channel

postulated from the electrical measurements. Can we

determine the composition?


SCANNING TRANSMISSION X-RAY MICROSCOPY (STXM)

Devices need to be on membranes for transmission experiment

Pt

TiO2

Pt

Si3N4

Si

1.5μm x 1.5μm junction

Side view

Top view

Si3N4

Membrane


455 460 465 470 0

2

4

6

8

X-ray energy (eV)

Ab

so

rptio

n (

a.u

.)

STXM, E = 460 eV

TiO2 Anatase, heated > 330° C

TiO2 Amorphous

TiO2-x Reduced

500 nm

Chemical/Structural Mapping by XAS

JP Strachan, MD Pickett, JJ Yang, S Aloni, ALD Kilcoyne,

G Ribeiro, RS Williams, Advanced Materials 22, 3573

(2010)


500 nm

TEM - Electron diffraction

100 nm

Amorphous Anatase (and Pt)

Single Crystal Ti4O7


ELIMINATE ELECTROFORMING!

1.0x10 -3

0.5

0.0

-0.5

Curr

ent

(A)

-1.5 -1.0 -0.5 0.0 0.5 1.0

Device Voltage (V)

Pt / 35nm “Ti4O7” / 5nm TiO2 / Pt

No electroforming step

OFF state = virgin state

TiO2 Pt

Pt

Ti4O7

ON

OFF


Switching Speed, Energy and Endurance


THE QUESTIONS PEOPLE ASK

– Switching voltages/currents (volts/nA - A)

– Write/Erase/Read speed and energy (<1ns, ~1pJ)

– ON/OFF ratio (>1000:1)

– Retention time (>years)

– Endurance >10 billion and counting

– Scaling limits (10 nm pitch? ~1 terabit/sq cm/layer)

– Endurance and failure mechanisms (heating, electromigration)

– Nature of ON and OFF states (metal/insulator)

– Electroforming (can eliminate)

– Devices are evolving rapidly with understanding


High-speed setup for memristor characterization

Pulse Generator

3-dB Power Splitter Memristor

Scope


Zseries

Coplanar transmission line (CPW)

CPW probe

wpad

s

wmemristor spad

Top electrode

Bottom electrode

w

memristor

junction

Microwave transmission line measurements:

high speed switching time and energy


SET and RESET in ~ 100 picoseconds @ ~2V

SWITCHING TIMES


switch

SWITCHING ENERGY @ ~0.5V


– Endurance: >1010 cycles =>

Yang et al., APL 97, 232102 (2010)

SOME RECENT RESULTS (TAOX):


A Future

ENDURANCE

Year

2008 2009 2010 2011 2012

Endur

anc

e (c

ycle

s)

103

104

105

106

107

108

109

1010

1011

1012

1013

1014

1015

SAIT results

HP Labs results

DRAM consumer replacement

FLASH (SLC)


Memristor Logic


Bertrand Russell

Bertrand Russell studied logic

extensively in the early 1900’s. He

viewed the ‘Material Implication’

operation, which along with

FALSE forms a complete

basis for universal computing, as

especially interesting.


P Q

VP=VCOND VQ=VSET

1 1 1

0 0 1

1 1 0

1 0 0

q p IMP q

q p

a)

c)

b)

10-8

10-6

10-8

10-6

10-8

10-6

10-8

10-6

Cu

rren

t (

am

ps)

p q q

-0.4

-3.0

-5.0 V (

volts)

2µs 1ms

time

p

RG

IMP in in out

q

in in out

Experimental Test of Memristor IMP operation

Borghetti et al., Nature (2010)


P Q VP VQ

S VS

VS = VCLEAR Step 1:

Step 2:

Step 3:

a)

-6

-4

-2

0

V (

vo

lts)

Cu

rre

nt

(am

ps)

time

IMP

s s s p q

10-6

10-4

10-6

10-4

10-6

10-4

10-6

10-4

p q

IMP in in out c) VS = VSET

VS = VSET VQ = VCOND

VP = VCOND

1

1 0 1

1 1 0

1 0 0

s

0

s=0 s p IMP s s p NAND q

s s q

0 0 1

1 0 0

1 1 1

1 1 0

s s p

0 0 1

1 0 0

s q p

0 1

b)

s q IMP s

0

0

0

0 0 1

1 0 0

RG

Step 1 Step 2 Step 3 Steps 1-3

Experimental Demonstration of Memristor NAND

Borghetti et al., Nature (2010)


CMOS NAND gate

Area = 36×(FP)2

= 0.122 @ 30 nm hp

SIMPL NAND gate

Area = 3×(FP)2

= 0.012 @ 30 nm hp

Area comparison of NAND gates


SUMMARY OF IMPLICATION LOGIC

– Memristors state machines.

– Linear array + demux; simple and dense.

– State encoded with impedance, not voltage.

– No static power dissipation.

– Nonvolatile.

– Material Implication (IMP) and FALSE are complete

– Need to ask how the nanoscale world wants to compute, not impose our

preconceptions!


SYNAPTIC COMPUTING


50

HYBRID XBAR SYNAPTIC CIRCUIT

CMOS/memristor hybrid circuit with

multi-layer Xbar & analog synapses


THE MEMRISTOR AS AN ANALOG SYNAPSE:

V1

V2

V3

V4

V5

V6

Calculate the dot product

Itot = V ∙ M-1

For a chip with 109 memristors

and a clock speed of 1 MHz,

The equivalent computation is

1015 FLOPS, i.e. a petaFLOP

(floating point operation per sec)

M1

M2

M3

M4

M5

M6

Itot

. . .


3D ARCHITECTURE


ARCHITECTURE: 4-D ADDRESS SPACE FOR M CROSSBARS!

1

2

3

4

5

A

B

C

D

E

1 2 3 4 5A B C D E

N2 access devices

N data/control lines

~N2β2 Xpoint

devices per layer

(out of N4 total)

device in 1st layer

device in 2nd layer

Xbar layer

wiring layer

CMOS layer

M = N2/b2

Can address any crosspoint in M crossbars with a single sparse set of vias!

The CMOS pitch can be much larger than the crossbar pitch

Virtual N2 x N2 crossbar

PNAS 106 (2009) 20155-20158


3D CROSSBAR ARCHITECTURE: LOGIC AND STORAGE

Logic layer

CMOS layer

for control

Cache layer

Storage layer(s)

Memory layer

Computation localized

in space – enables

high speed, low

latency and power

Longer range data transport done with photonics

PNAS 106 (2009) 20155-20158 Many layers per mask step needed –

Unlikely to be developed by industry


NEGATIVE DIFFERENTIAL RESISTANCE


THRESHOLD SWITCHING IN OXIDES

Chopra, Proc. IRE, 1963 Geppert, Proc. IRE, 1963

Threshold switching and

resulting oscillations first

observed in niobium oxide

and later in related oxides.

these are the same materials

that display memristance.

Thus, we obtain two important

and different properties from

the same CMOS compatible

material system.


WHY IS THIS INTERESTING NOW?

Nanoscale crossbar circuits: •4F2 integration density •Stackable/CMOS compatible •2 terminal devices •Switching power scales with area •Switching speed scales with area-1

•Based on „bulk properties‟ – no statistical issues with small volume doping


MEMRISTANCE AND NEGATIVE DIFFERENTIAL RESISTANCE


NEGATIVE DIFFERENTIAL RESISTANCE/ INSULATOR TO METAL TRANSITION

Ti4O7 I-V-T

SPICE

experiment model

Free oscillations

2 2

0 2

4 ( )1( , ) exp

2

met chan MIT ambamb

chan met

r r T Tu i T W

r i

insmet

chan

ambchan

uu

L

rTiG

222)1(

),(


FAST TRANSITION DYNAMICS

IM Phase transition time ≤ 400 ps Primary limitation is capacitance of oscilloscope Potential for multi-GHz electronics

DC/AC conversion „self-oscillations‟


MEMRISTORS AND NDR COMPLEMENT CMOS

The materials used to make memristors and the newly discovered NDR devices are completely CMOS compatible – they can be inserted into the “interconnect” layers to provide a wide range of functionality. For many applications, memristors and NDR devices can replace significant numbers of transistors in a circuit, and in the process dramatically increase the functionality per transistor and speed of operation while decreasing the power consumption of the circuit.


Q&A

finding the missing memristor · logic layer cmos layer for control cache layer storage layer(s)...

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