finite state machines -...
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![Page 1: Finite State Machines - fpga-fhu.user.jacobs-university.defpga-fhu.user.jacobs-university.de/wp-content/uploads/2014/10/chap... · Moore machine versus Mealy machine 5. VHDL description](https://reader031.vdocument.in/reader031/viewer/2022021801/5b524f857f8b9adf538d1b2a/html5/thumbnails/1.jpg)
RTL Hardware Design
by P. Chu
Chapter 10 1
Finite State Machines
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RTL Hardware Design
by P. Chu
Chapter 10 2
Outline
1. Overview
2. FSM representation
3. Timing and performance of an FSM
4. Moore machine versus Mealy machine
5. VHDL description of FSMs
6. State assignment
7. Moore output buffering
8. FSM design examples
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RTL Hardware Design
by P. Chu
Chapter 10 3
1. Overview on FSM
• Contain “random” logic in next-state logic
• Used mainly used as a controller in a large system
• Mealy vs Moore output
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RTL Hardware Design
by P. Chu
Chapter 10 4
2. Representation of FSM
• State diagram
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RTL Hardware Design
by P. Chu
Chapter 10 5
• E.g.
a memory
controller
• Signal not
asserted =
default
value
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RTL Hardware Design
by P. Chu
Chapter 10 6
• ASM (algorithmic state machine) chart
– Flowchart-like diagram
– Provide the same info as an FSM
– More descriptive, better for complex
description
– ASM block
• One state box
• One ore more optional decision boxes: with T or F
exit path
• One or more conditional output boxes: for Mealy
output
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RTL Hardware Design
by P. Chu
Chapter 10 7
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RTL Hardware Design
by P. Chu
Chapter 10 8
State diagram and ASM chart conversion
• E.g. 1.
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RTL Hardware Design
by P. Chu
Chapter 10 9
• E.g. 2.
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RTL Hardware Design
by P. Chu
Chapter 10 10
• E.g. 3.
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RTL Hardware Design
by P. Chu
Chapter 10 11
• E.g. 4.
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RTL Hardware Design
by P. Chu
Chapter 10 12
• E.g. 6.
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RTL Hardware Design
by P. Chu
Chapter 10 13
• Difference between a regular flowchart
and ASM chart:
– Transition governed by clock
– Transition done between ASM blocks
• Basic rules:
– For a given input combination, there is one
unique exit path from the current ASM block
– The exit path of an ASM block must always
lead to a state box. The state box can be the
state box of the current ASM block or a state
box of another ASM block.
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RTL Hardware Design
by P. Chu
Chapter 10 14
• Incorrect ASM charts:
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RTL Hardware Design
by P. Chu
Chapter 10 15
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RTL Hardware Design
by P. Chu
Chapter 10 16
3. Performance of FSM
• Similar to regular sequential circuit
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RTL Hardware Design
by P. Chu
Chapter 10 17
• Sample timing diagram
(mealy)
(moore)
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RTL Hardware Design
by P. Chu
Chapter 10 18
4. Moore vs Mealy output
• Moore machine:
– output is a function of state
• Mealy machine:
– output function of state and inputs
• From theoretical point of view
– Both machines have similar “computation
capability”
• Implication of FSM as a controller?
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RTL Hardware Design
by P. Chu
Chapter 10 19
• E.g., edge detection circuit
– A circuit to detect the rising edge of a slow
“strobe” input and generate a “short”
(about 1-clock period) output pulse.
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RTL Hardware Design
by P. Chu
Chapter 10 20
• Three designs:
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RTL Hardware Design
by P. Chu
Chapter 10 21
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RTL Hardware Design
by P. Chu
Chapter 10 22
• Comparison
– Mealy machine uses fewer states
– Mealy machine responds faster
– Mealy machine may be transparent to glitches
• Which one is better?
• Types of control signal
– Edge sensitive
• E.g., enable signal of counter
• Both can be used but Mealy is faster
– Level sensitive
• E.g., write enable signal of SRAM
• Moore is preferred
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RTL Hardware Design
by P. Chu
Chapter 10 23
VHDL Description of FSM
• Follow the basic block diagram
• Code the next-state/output logic according
to the state diagram/ASM chart
• Use enumerate data type for states
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RTL Hardware Design
by P. Chu
Chapter 10 24
• E.g. 6.
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RTL Hardware Design
by P. Chu
Chapter 10 25
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RTL Hardware Design
by P. Chu
Chapter 10 26
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RTL Hardware Design
by P. Chu
Chapter 10 27
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RTL Hardware Design
by P. Chu
Chapter 10 28
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RTL Hardware Design
by P. Chu
Chapter 10 29
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RTL Hardware Design
by P. Chu
Chapter 10 30
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RTL Hardware Design
by P. Chu
Chapter 10 31
• Combine next-state/output logic together
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RTL Hardware Design
by P. Chu
Chapter 10 32
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RTL Hardware Design
by P. Chu
Chapter 10 33
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RTL Hardware Design
by P. Chu
Chapter 10 34
6. State assignment
• State assignment: assign binary
representations to symbolic states
• In a synchronous FSM
– All assignments work
– Good assignment reduce the complexity of
next-state/output logic
• Typical assignment
– Binary, Gray, one-hot, almost one-hot
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RTL Hardware Design
by P. Chu
Chapter 10 35
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RTL Hardware Design
by P. Chu
Chapter 10 36
State assignment in VHDL
• Implicit: use user attributes enum_encoding
• Explicit: use std_logic_vector for the
register
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RTL Hardware Design
by P. Chu
Chapter 10 37
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RTL Hardware Design
by P. Chu
Chapter 10 38
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RTL Hardware Design
by P. Chu
Chapter 10 39
Handling the unused state
• Many binary representations are not used
• What happens if the FSM enters an unused state?
– Ignore the condition
– Safe (Fault-tolerant) FSM: go to an error state or return to the initial state.
• Easy for the explicit state assignment
• No portable code for the enumerated data type
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RTL Hardware Design
by P. Chu
Chapter 10 40
6. Moore output buffering
• FSM as control circuit
– Sometimes fast, glitch-free signal is needed
– An extra output buffer can be added, but
introduce one-clock delay
• Special schemes can be used for Moore
output
– Clever state assignment
– Look-ahead output circuit
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RTL Hardware Design
by P. Chu
Chapter 10 41
• Potential problems of the Moore output
logic:
– Potential hazards introduce glitches
– Increase the Tco delay (Tco = Tcq + Toutput)
• Can we get control signals directly from
the register?
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RTL Hardware Design
by P. Chu
Chapter 10 42
Clever state assignment
• Assigning state according to output signal
patterns
• Output can be obtained from register directly
• Extra register bits may be needed
• Must use explicit state assignment in VHDL
code to access individual register bit
• Difficult to revise and maintain
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RTL Hardware Design
by P. Chu
Chapter 10 43
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RTL Hardware Design
by P. Chu
Chapter 10 44
• VHDL code
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RTL Hardware Design
by P. Chu
Chapter 10 45
Look-ahead output circuit
• Output buffer introduces one-clock delay
• The “next” value of Moore output can be
obtained by using state_next signal
• Buffer the next value (cancels out the one-
clock delay)
• More systematic and easier to revise and
maintain
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RTL Hardware Design
by P. Chu
Chapter 10 46
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RTL Hardware Design
by P. Chu
Chapter 10 47
• Modification over original VHDL code:
– Add output buffer
– Use state_next to replace state_reg in Moore
output logic
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RTL Hardware Design
by P. Chu
Chapter 10 48
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RTL Hardware Design
by P. Chu
Chapter 10 49
7. FSM design examples
• Edge detector circuit
• Arbitrator (read)
• DRAM strobe signal generation
• Manchester encoding/decoding (read)
• FSM base binary counter
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RTL Hardware Design
by P. Chu
Chapter 10 50
Edge detecting circuit (Moore)
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RTL Hardware Design
by P. Chu
Chapter 10 51
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RTL Hardware Design
by P. Chu
Chapter 10 52
Use clever state assignment
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RTL Hardware Design
by P. Chu
Chapter 10 53
Use look-ahead output
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RTL Hardware Design
by P. Chu
Chapter 10 54
Edge detecting circuit (Mealy)
![Page 55: Finite State Machines - fpga-fhu.user.jacobs-university.defpga-fhu.user.jacobs-university.de/wp-content/uploads/2014/10/chap... · Moore machine versus Mealy machine 5. VHDL description](https://reader031.vdocument.in/reader031/viewer/2022021801/5b524f857f8b9adf538d1b2a/html5/thumbnails/55.jpg)
RTL Hardware Design
by P. Chu
Chapter 10 55
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RTL Hardware Design
by P. Chu
Chapter 10 56
• Edge detecting circuit (direct implementation):
– edge occurs when previous value is 0 and new
value is 1
– Same as Mealy design with state assignment:
zero => 0, one => 1
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RTL Hardware Design
by P. Chu
Chapter 10 57
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RTL Hardware Design
by P. Chu
Chapter 10 58
• DRAM strobe signal generation
– E.g.,120ns DRAM (Trc=120ns):
Tras=85ns, Tcas=20ns, Tpr=35ns
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RTL Hardware Design
by P. Chu
Chapter 10 59
• 3 intervals has to be at least 65ns, 20 ns, and 35 ns
• A slow design: use a 65ns clock period – 195 ns (3*65ns) read cycle
• The control signal is level-sensitive
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RTL Hardware Design
by P. Chu
Chapter 10 60
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RTL Hardware Design
by P. Chu
Chapter 10 61
• Should revise the code to obtain glitch-free output
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RTL Hardware Design
by P. Chu
Chapter 10 62
• A faster design: use a 20ns clock period
– 140 ns (7*20ns) read cycle
idle mem r1
ras_n<=0
p1cras_n<=0cas_n<=0
r2
ras_n<=0
r3
ras_n<=0
p2
mem'
r4
ras_n<=0
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RTL Hardware Design
by P. Chu
Chapter 10 63
SummaryRepresenting FSMs
State Diagrams / ASM Charts
Timing and Performance
Moore/Mealy Outputs
Coding FSMs for Synthesis
Follow the block diagram: memory, ns/o logic
State assignment
Glitch-free Outputs: Clever, Buffering
FSM design examples