first, fast and final - achieving first-time- right ...€¦ · 1.e-19 1.e+01 1.e+02 1.e+03 1.e+04...

Company Confidential 1

First, Fast and Final - Achieving First-Time-Right Silicon in Analog Designs

Part I: Can first-time-right analog design be achieved working with foundries? – Selecting the right process

> Presenters: Volker Herbig, Dr. Konrad Bach

> Moderator: Thomas Hartung, VP Marketing

Welcome to our Webinar Fall Series:

September 11th, 2013


Agenda

> Brief Introduction to X-FAB by Thomas Hartung, VP Marketing, X-FAB Group

> Presentation „Can first-time-right analog design be achieved working with foundries? – Selecting the right process ” by Volker Herbig & Konrad Bach

> Q & A

> Duration: approx. 1 hour in total


Webinar Series on Achieving First-Time-Right in Analog Design

> Part I – 10 & 11 Sept.Can first-time-right analog design be achieved working with foundries? – Selecting the right process

> Part II – 25 & 26 Sept.Pre-requisites for first-time-right success – Modeling and process characterization

> Part III – 09 & 10 Oct.Taming the analog beast – Using X-FAB’s PDKs and the right design methodology

> Part IV – 23 & 24 Oct.Making analog designs successful – Tips & tricks

Introducing the Presenters


Volker HerbigDirector Technical Marketing

Dr. Konrad BachTeamleader Process Development CMOS


Can first-time-right analog design be achieved working with foundries – Selecting the right process

Presenters: Volker Herbig Director Technical MarketingKonrad Bach X-FAB Fellow

Moderator: Thomas Hartung VP Marketing

September 11th, 2013

First, Fast and Final

Analog market

2013F IC Market by Product Type ($275.9B)

2013F IC Market by Application($275.9B)

($42.8B)

Today Automotive Applications

Reduce emissions Improve safetyMore comfort

Controller /Pump

Networking ICs

TPMS /Energy Harvesting

HMI Gesture Recognition

Controller / Pump

Process Requirements180 nm / 130 nm nodeHV CMOS/ NBL/ SOIEmbedded µC Driver / Predriver (40 VDS) NVM – eFlash, EEPROMPHYHigh Temperature

Todays Medical / Industrial Applications

Ultrasonic

Cell AnalysisDNA Analysisand GenomeSequencing

Blood Presure Sensors

X-Ray

Aging population in western world drive medical costGrowing population in 3rd world needs affordable health care

Ultrasonic

Miniaturization

3D imaging capability

Process Requirements180 nmSOIAnalogLarge Driver Array ( 200 VDS) Trimming

Today Communication Application

Power Management

Battery Management

Video

Touch

Transmitter

Microphone Amplifier Motion sensing

Compass

Audio

long battery life timesmaller footprintalways connected

Market Challenges

Fragmented market with many product with low volumeBut with highest quality requirementsBut with Highest reliability requirements With increasing complexity of IC design 20

15

10

05

350 250 180 130 90

Design Challenges

Low NoiseLow PowerNVMHigh TemperatureHigh Voltage integrationESD robustness Die Size constrains High ReliabilityTime-To-Market…

Cost of redesign

% o

f lif

e tim

e si

licon s

pen

d

Market

Re-spin cost (option, redesign)Time to Market

What is reality at X-FAB ?

35%

19%

14%15%

7%

4%2% 2% 2%

1 2 3 4 5 6 7 8 9

# of iterations

%

First Time Right Eco System

Topic Customer Designer Foundry EDA Vendor IP Vendor OSAT*

Process Selection

Models

ESD

Design Methodology

PDK

IP

Manufacturing

EDA Tools

Application know how

DFM/ DFT

Packaging & Test

*)Outsourced Assembly and Test

Webinar Topics & Resources

Online Resources – X-FAB Webinar replays covering a wide range of topics relevant to first time right

Webinar Series – First, Fast and Final1. Selecting the right process 2. Modeling and process characterization3. PDKs and the right design methodology4. Making analog designs successful – Tips & tricks


Selecting the right Process

> Introduction> Active Devices> Passive Devices> Substrate noise


Contents



Introduction

…the real world is analog…

– many integrated circuits have to deal not only with digital signalsThere are not only « 0 » and « 1 », black and white, low and high…

– Intermediate states and values have to beencomparedstoredcalculatedmanaged…

– but of course also digital decisions have to be made

> The selected manufacturing process has to support

– mixed signal circuits


Introduction

…mixed signal

– demands always an considerable part of digital functions– they are nowadays always built with CMOS– the neccessary gate density defines which feature size has to be chosen

e.g.

– the feature size defines a process platform

> but the process platform and the available devices may have a strong impact on the analog features

feature sizegate

density1 µm 600

0.6 µm 30000.35 µm 180000.18 µm 120000


Contents


Active Devices for Analog Designs

> CMOS key elements are the nmos and pmos FETS– for use in analog circuitry several properties are to consider:

> Linearity


active region:Id grows linear with Vdimportant for switching

saturation regionId grows linear with Vgand is nearlyindependent on Vd

very interesting for analog

Active Devices

> the independence on VD but linearity with Vg is more pronounced for longer channels

– but one need a certain linear hedroom

Vd – Vt should be large enough

> this linear behaviour is interesting for analog circuits


Active Devices for Analog Designs / headroom

> With the normal CMOS scaling the maximum allowed drain and gate voltage also scales down.

– But in order to keep the off state leakage low the Vt is even slightly increased

the available gate voltage “headroom” for analog applications gets reduced

> a second operating voltage for MOS transistors is important for analog application.– e.g. 5 V in 0.35 µm– and 3.3 or even 5 V in 0.18 µm


feature size Vd [V] [V] headroom1 µm 5 0.70 4.30

0.6 µm 5 0.75 4.250.35 µm 3.3 0.80 2.500.18 µm 1.8 0.85 0.95

Active Devices for Analog Designs / headroom

> But of course this increases the process effort–not only a second gateoxide is needed –also the Vt adjustment and even the LDD needs extra implant masks

> another interesting measure to increase the headroom is the Vt reduction

–lower Vt e.g. down to 0.3 V for the analog part only despite increased leakage–use for the nmos the „natural“ or „zero“ channel (Vt ~ 0 V) –also the „nomally on type“ (depletion nmos) is an important device for analog

> the penalty of increased off state leakage can be reduced by using not the minimum length or can even be tolerated because the off state is not that important for analog


Active Devices / Noise

> MOSFETS usually have their current path immediately under the Si/SiO2 interface

> the interface impacts the carrier mobility and due to trapping and detrapping in interface states also the carrier concentration

> the consequence is a noise in the current which increases with lower frequencies:

1/ F noise

> Fortunately the positively charged interface together with the workfunktion of an n-type gate and the typical channel doping causes the current in a pmos channel to flow not directly under the surface

> buried channel pmos FETS are very interesting devices for low noise analog applications


1.E-26

1.E-25

1.E-24

1.E-23

1.E-22

1.E-21

1.E-20

1.E-19

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Frequency (Hz)

Spe

ctra

l ID

(A^2

/Hz)


> but a buried channel is susceptible for leakage at very short channel length

> therefore often in sub half micron process platforms a dual workfunction approach is used

– the pmos gate is not longer n-doped but p– also the pmos gets a surface channel

> the risk of leakage is reduced> but the benefit of low noise is lost!


pmos noise

transistors made with the same process platform

red: n-type gateblue and green: p-type gate

> unfortunately buried nmos FET channels can not be built in a similar simple way

> the only chance to get a buried n-channel for a FET is the use of jucnction controlled FETs (J-FET)

> Processes with several deep wells enable such J-FETS– but note: the channel is there where differences of dopings are

relevant– it is hard to keep the Vt under tight control



> Usually such deep wells were introduced in order to adress high voltages (e.g. the 40 V for automotive application)

– one needs at least one deep n-well and an isolated p-well to built automotive nmos and pmos

> But such deep wells also enables vertical bipolar transistors

> And they are even better suited than all FETs for analog



Active Devices for Analog Designs / BJT

> BJT as current controlled devices are quite linear> the output collector current is proportional to the input base current

the gain (beta) is the proportionality factor> This proportionality is nearly constant for several collector current

decades


> CMOS processes with one deep n-well and an isolated p-well enable– an isolated vertical npn

– an vertical pnp (whereby the substrate forms the collector)



> isolated pnp can also be built in CMOS processes but they are lateral

– a lateral pnp looks like a pmos– but the gate is grounded– the current flows not along the interface

> the current path in all BJTs is away from the surface/interface> BJT therefore have always lower noise than MOSFETS

> But there may be a parasitic pnp to te substrate!



> BJT in CMOS are often „exploited parasitic devices“> they come for free but may not always be under good control> in order to get stable high performing and in particular very fast BJT

special measures are needed

> like– buried highly doped collector– poly silicon emitter– self aligned base connection– selectively implanted collector

> BiCMOS or BCDMOS

If very high speed is not that important

the „exploited parasitic BJTs“are a very interesting alternativefor analog circuitry



Devices for Analog Designs / Matching

> BJTs also beat the MOSFETs in terms of matching

> the mismatch for a pair of devices at a given active area is much better for a BJT than for any MOSFET


0.250.51248128

0

10

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50

60

70

80

90

100

0 0.5 1 1.5 2 2.5

1µm CMOS0.8µm CMOS0.6µm CMOS0.35µm CMOS0.18µm CMOS0.6 BiCMOSW*L

Delta Vt resp. Vbe in mVvs. 1/sqrt(L*W), (L and W in µm)

Devices for Analog Designs / Matching

> But interesting to see

– the MOSFETs match the better the smaller the features sizethe root cause is not the feature size but the gateoxide thicknessfor thinner gateoxides more dopands are needed to keep the threshold highfluctuations (for a give area) have lower impact


0.250.51248128

0

10

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30

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50

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100

0 0.5 1 1.5 2 2.5

1µm CMOS0.8µm CMOS0.6µm CMOS0.35µm CMOS0.18µm CMOS0.6 BiCMOSW*L


Contents


Passive Devices for Analog Designs / Resistors

>



> dielectric isolated resistors made in polisilicon layers are less sensitive agains that depletion effect

> for the junction isolated ones the Voltage Coefficient depends on the doping level and on the doping profile slope


Resistor Technology Sheet Resistance[Ohm/sq.]

Voltage coefficient[10-3/K]

n-diff XH035 85 1.6n-well XH035 1160 3.9n-well XC06 900 6.8

HIRES POLY XH035 1000 0.1


> Another important question is the temperature dependency of the resistance

> Fortunately in semiconductors two effects compete and this can be exploited to adjust the temperature dependency

> the carrier mobility is temperature dependent – the higher the temperature the more “they disturb each other” – we have a positive temperature coefficient for the resistivity.

> But in semiconductors the number of carriers can be drastically increased with temperature – which would cause a negative temperature coefficient.



> Both effects together allow to find a doping level whereby only a very low dependency of the sheet resistance on the temperature remains

> For poly silicon with the usual thicknesses this is in the area of 200 Ohms

> Note: the dependency is not linear – real independence can only be achieved for a given temperature range



> some examples from X-FAB‘s process portfolio


XH035 rp1 rp2 rzp2 rpp1 rnp1 rhp

RS 40 100 200 500 1000 10000

TC 0.8 0.6 -0.2 -0.5 -2.8 -4.3

*) *) for LL and LT other parametersXH018 rpp1 rnp1 rpp1k rnp1h

RS 280 330 1000 6700

TC -0.11 -1.4 -0.9 -5.7

XP018 rpp1 rnp1 rnp1h

RS 280 330 6700

TC -0.04 -1.4 -5.7

Passive Devices for Analog Designs / Capacitors

> Key parameter for a capacitor are – high capacitance per area– withstand a given voltage– be independent on the applied voltage (= linear) – match well with partners

> as long as semiconductors are used inside the plates accumulation and depletion may occure



> this will cause nonlinearities!

– black curve:both plates are metal

– green curvehighly doped semiconductor of the same type

– bluelower doped but same hight and type

– yellow and redeven lower and unsymmetrical doping



> Poly Poly Capacitors (PIP) need high and identical doping to get good linearity for analog application

> Metal Isolator Metal (MIM) capacitors have initially a better linearity

> for PIPs and for MIMs the silicon substrate acts as a third plate –we get a parasitic capacitor to the substrate

> This parasitic becomes lower with thicker insulatorbetween substrate and bottom plateMIMs benefit over PIPsin particular if they are arranged between the higher metal layers



> PolyPoly Caps and MIMs need additional processeffort

> Metal Fringe capacitors are an interesting alternative

> They exploit the third dimension

> and don‘t need extra processing steps> if 6 metal layers are available one gets comparable area capacitance



Contents

> Introduction> Active Devices> Passive Devices> Substrate noise> Summary

Substrate Coupling / Lateral Isolation

> Mixed signal systems on chips bare always the risk of cross talk between elements

> fast digital switches may cause changes in the substrate potential which impacts sensible analog circuitry

> different methodes to deal with are established



> Use of epi wafers instead of low doped bulk wafers

– they high doping in the depth builds a „good grounding“

– it can prevent too high lateral potential fluctuations– but it does not really isolate the nmos bodies



> Another often used approach is the well in well isolation

– we call it ISOMOS pmos and nmos are (junction) isolated from bulk

– this approach comes along with the mentioned wells for High Voltage which also enables the vertical bipolars

– but parasitic pnp and npn constructions remain which can open unwanted bipolar effects



> the well in well isolation can be improved with highly doped buried layers

– parasitic bipolars can be suppressed – the wanted BJTs but also High Voltage transistors (DMOS) can be

improvedBCDMOS



> the best isolation can be achieved by dielectric isolation with Silicon on insulator (SOI)

> the substrate as agent for cross talk is completely isolated


Benefits/Trade-offs of Technology Architectures

Architecture Benefits Trade-offs

Junction-isolated bulk Silicon

BCD Technology

SOI Technology





• Cost efficient• Suitable for many applications• Good thermal conductivity

• Intrinsic parasitic bipolar elements can cause Latch-up

BCD Technology

SOI Technology







BCD Technology • Integration of vertical bipolar transistors• Suppression of parasitic bipolar

transistors

• Increased process effort, e.g. epitaxy, implantations

SOI Technology







BCD Technology • Integration of vertical bipolar transistors• Suppression of parasitic bipolar

transistors

• Increased process effort, e.g. epitaxy, implantations

SOI Technology • Bidirectional dielectric lateral and vertical isolation

• Area efficient isolation techniques• Denser layouts• Voltage-stacking• Suppressed cross-talk

• No parasitic bipolar effects (Latch-up) and reduced leakages and parasitic capacitances higher speed

• Enables special applications • Ease-of-design

• Higher raw wafer price• Parasitic MOS effects• Lower thermal

conductivity



Contents

> Introduction> Active Devices> Passive Devices> Substrate noise> Summary

Summary

> a CMOS process for mixed signal applications should have not only– MOSFETs

with dedicated properties, also

– Bipolars – Resistors– Capacitors

are essential

> Their properties may improve with scaling– like matching– fringe capacitors can be exploited

> But some properties may also degrade– like noise behaviour of surface channel p-mos

> Some of the devices appear feasible from the architecture point of view– but feasible means not always available– look for characterisation results and ask for support and maintenance

> Not only the devices, also the isolation scheme is important for mixed signal– Trench SOI is a very intersting alternative – in particular for our first time right goal



Q & A> Please ask your questions by using the "Questions" field.

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X-FAB Feature Explorer

> Get a quick overview of X-FAB's broad foundry technology portfolio or your next chip design.

> Includes a Non-Volatile Memory (NVM) and High-Voltage selector functionality

> Available at– www.xfab.com


Thank you for your attention.

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first, fast and final - achieving first-time- right ...€¦ · 1.e-19 1.e+01 1.e+02 1.e+03 1.e+04...

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