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Nuclear Instruments and Methods in Physics Research A 604 (2009) 390–392

Contents lists available at ScienceDirect

Nuclear Instruments and Methods inPhysics Research A

0168-90

doi:10.1

$ Wo� Corr

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journal homepage: www.elsevier.com/locate/nima

First generation of deep n-well CMOS MAPS with in-pixel sparsification forthe ILC vertex detector$

Gianluca Traversi a,b,�, Antonio Bulgheroni c,d, Massimo Caccia c,d, Marcin Jastrzab c,d,e,Massimo Manghisoni a,b, Enrico Pozzati b,f, Lodovico Ratti b,f, Valerio Re a,b

a University of Bergamo, Italyb INFN-Pavia, Italyc University of Insubria, Como, Italyd INFN-Milano, Italye AGH-University of Science and Technology, Krakow, Polandf University of Pavia, Italy

a r t i c l e i n f o

Available online 12 February 2009

Keywords:

CMOS pixels

MAPS monolithic active pixel sensors

Charged particle tracking

02/$ - see front matter & 2009 Published by

016/j.nima.2009.01.195

rk supported by Italian Institute for Nuclear

esponding author at: University of Bergamo,

ail address: gianluca.traversi@unibg.it (G. Tra

a b s t r a c t

In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel

sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named

sparsified digital readout (SDR0), for the first time we implemented a sparsification logic at the pixel

level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the

substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive

detectors. In this work, the experimental characterization of the SDR0 chip, including data from

radioactive source (55Fe) tests, will be presented.

& 2009 Published by Elsevier B.V.

1. Introduction

Future experiments at the International Linear Collider (ILC)will need highly granular, thin, radiation tolerant, fast vertexdetectors installed very close to the interaction region. Among thepossible candidates [1–3], the requirement for low materialbudget detectors in the interaction regions of the experimentsmakes monolithic active pixel sensors (MAPS) interesting for apossible implementation at the ILC machine [4]. In these devices,where the charge released in the epitaxial layer by a minimumionizing particle is collected via thermal diffusion, the collectingn-well/p-epi junction and the front-end electronics are integratedonto the same substrate. Moreover, since the low resistivitysubstrates of CMOS technologies cannot be depleted as it iscommonly done in silicon detectors, MAPS detectors may bethinned by means of micromachining techniques without sig-nificantly degrading their performances. CMOS MAPS have beendeveloped by several groups over the last few years. These designsfollow the very simple readout scheme adopted for imagingapplications, based on the use of only three transistors in the pixelcell, with a sequential readout. However, with sensor matrices oflarge size, sequential processing architectures may not be able to

Elsevier B.V.

Physics (INFN).

Italy.

versi).

comply with the integration time constraints set by vertexingapplications at the ILC. A new approach in the design of CMOSMAPS exploits the deep n-well (DNW) option to improve thereadout speed performance of these devices and, at the sametime, to increase the sensitive element area. Results from DNWMAPS prototype chips have been published in Refs. [5–7], showingthe viability of the concept, and demonstrating good sensitivity ofthe pixel both to 55Fe photons and to 90Sr electrons. The collectingelectrode is realized with the DNW of the triple well process. If alarge area DNW sensor, as compared to standard MAPS, islaid out, the effect of PMOS n-wells interfering with the chargecollection in the main electrode may be overlooked. Thisallows the designers to lay out more complex and higherperformance circuits taking advantage of fully complementaryMOS architecture.

This paper presents the complete characterization of a newDNW prototype device, designed according to ILC vertex detectorspecifications.

2. Description of the prototype chip

The sparsified digital readout (SDR0) prototype is a proof-of-principle design which is aimed at studying the feasibility of apixel level SDR0 architecture in a CMOS MAPS matching therequirements for the Vertex Tracker at the ILC. The chip has beenfabricated in the STMicroelectronics 130 nm triple-well CMOS

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Table 1Equivalent noise charge (ENC) for the structures equipped with an injection

capacitance.

Tested structure ENC [e� rms]

C1 (CD ¼ 90 fF) 50

C2 (CD ¼ 120 fF) 65

C3 (CD ¼ 60 fF) 45

M3 central pixel 60

Fig. 1. Firing efficiency of a pixel belonging to M1 matrix fit with an error function

in the post-acquisition processing. The standard deviation of the pixel noise

G. Traversi et al. / Nuclear Instruments and Methods in Physics Research A 604 (2009) 390–392 391

process provided through CMP multiproject wafers. The elemen-tary cell in the MAPS integrated in the SDR0 chip comprising ananalog section, including a charge sensitive amplifier and athreshold discriminator, and a digital section including a 5-bittime stamp register and a number of logic blocks implementingthe sparsification logic. The sparsification architecture implemen-ted in this chip is based on a token passing scheme, which wasdeveloped for the BTeV pixel and silicon strip readout chips [8,9].MAPS sensor operation in the prototype chip is tailored on thestructure of the ILC beam and features two different processingphases: a detection, or acquisition, phase (corresponding to thebunch train interval) and a readout phase (corresponding to theintertrain interval). The readout architecture is easily scalable tolarger matrices. A detailed description of these blocks and theSDR0 scheme has been published in Ref. [10]. In the SDR0prototype, the pixel pitch is 25mm. In the case of the binaryreadout presently implemented in the chip, the spatial resolutionrequired for the ILC Vertex Detector demands a pixel layout pitchsmaller than 20mm. To achieve this reduced size, an optimizationof the pixel cell layout will be carried out in the next prototypes.The reduction of the pixel pitch may be also achieved by using amore scaled CMOS technology or new technological solutionssuch as use of vertical integration [11]. The prototype chips havebeen fabricated with two different substrate thickness (250 and100mm) to test the possible dependence of the sensor response onthis parameter. The results presented in this paper are relevant to100mm substrate thickness.

Different test structures are available in the SDR0 chip for theexperimental characterization. The prototype chip includes:

coincides with the parameter p1 (1DACu ¼ 1:22 mV).

�

M1: a 16� 16 matrix chiefly conceived for the test of thedigital sparsified readout architecture. � M2: an 8� 8 matrix with the same digital sparsified readout

architecture of M1 and selectable access to the output of thecharge preamplifier in each cell.

� M3: a 3� 3 matrix with all the outputs of the charge

preamplifiers accessible at the same time; charge can beinjected at the preamplifier input in the central pixel through a60 fF metal–insulator–metal (MIM) capacitor.

� Three readout channels (named C1, C2 and C3) where the DNW

is not connected to the preamplifier input; a detectorsimulating capacitance (60, 90, 120 fF MIM capacitor) isconnected to the gate of the input device; charge can beinjected at the preamplifier input in the central pixel through a60 fF MIM capacitor.

3. Characterization of the prototype chip

The analog front-end of the elementary cell consists of a chargepreamplifier followed by a threshold discriminator featuring achip-wide adjustable threshold. In the design of the circuit, thehigh frequency noise contribution has been reduced by purposelylimiting the charge preamplifier bandwidth. The choice of amodified, shaper-less version of a classical readout chain forcapacitive detectors was forced by the dimension of the pixel.Among the test structures available in the SDR0 chip, thoseprovided with a calibration capacitance at the preamplifier inputhave been tested through charge injection from an external pulser.

Noise characterization in terms of equivalent noise charge(ENC) has been performed by measuring the rms noise voltage atthe preamplifier output on the structures where it is available. Theresults are reported in Table 1. In those structures where only thelatch output is available, the noise values were obtained byprocessing the data acquired from threshold scans while injectinga fixed charge at the channel input. In this case it is possible to use

an error function to fit the firing efficiency curves of latches,which are the actual output blocks in the SDR0 MAPS. In the SDR0threshold scans, a low power InGaAs/GaAlAs/GaAs laser source,operating at a wavelength l of 1060 nm, has been employed toinject charge at the channel input. The pulse width of the injectedcharge, about 20 ns, has been kept shorter than the collection timeof MAPS devices (about 100 ns). Due to the large uncertaintydegree in the laser calibration, the ENC has been determined byusing the charge sensitivity obtained with a 55Fe source asdiscussed in the following. For each threshold voltage value,delivered to the pixel comparators by an external 12 bits DAC, thelaser has been fired and the pixel read out 1000 times. Boththe two matrices M1 and M2 have been investigated with thethreshold scan method and the digital information has beenprocessed providing, for each pixel in the matrices, a plot like theone in Fig. 1. The ENC can be calculated by dividing the p1parameter in the figure by the charge sensitivity and keeping intoaccount that 1 DAC unit corresponds to 1.22 mV. In order todetermine the ENC, in M1 matrix, all pixels have been illuminatedat the same time with a laser beam. For this purpose the spot size,which is close to 20mm at the focal distance, has been widened byacting on the distance between the focuser lens and the chip. Thenoise distribution is fitted by means of a Gaussian function, whichprovides a mean value of 65 e� rms with a standard deviation ofabout 14 e� rms. The ENC for M2 matrices is about 60 e� rms.

The same threshold scan method already described can beexploited in order to measure the threshold dispersion. In Fig. 1,the p0 parameter indicates the threshold voltage value corre-sponding to a 0.5 hit probability and such a value, when no chargeis injected, is the DC voltage value at the preamplifier output. Thethreshold dispersion is calculated by dividing the standarddeviation, associated with the p0 parameter distribution, by thecharge sensitivity averaged over the entire matrix. Thresholddispersion measurements have been performed on the two

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103

102

10

1

Cou

nt

Preamplifier output [DACu]0 50 100 150 200 250 300 350

Amplitude @ 1640e-

pedeSubHistoEntriesMeanRMS

8000850.8273.46

Fig. 2. Cumulative 55Fe spectrum relative to eight of nine pixels in M3 matrix

(1DACu ¼ 1:22 mV).

G. Traversi et al. / Nuclear Instruments and Methods in Physics Research A 604 (2009) 390–392392

matrices which provide 60 e� for M1 and 55 e� for M2,respectively.

The response of the sensor was also tested with a radiationsource. Soft X-ray from an 55Fe source were used to measure theconversion gain and the ENC in channels not equipped withcalibration capacitance. Photons absorbed in the silicon via thephotoelectric effect release all their energy in the detector. Forthe 5.9 keV line this corresponds to 1640 e/h pairs generated in thesilicon.

An 8-input Struck-DAQ system was used to sample simulta-neously eight of nine channels of the 3� 3 matrix, at a frequencyup to 80 MHz. The memory depth in the sampling buffers allowsfor the storage of 2048 samples acquired in a continuous and FIFOfashion. When a triggering event take place the content of theseregisters is saved into memory for post-acquisition processing. Inorder not to lose the signal rise edge, in correspondence of eachtriggering event, the 2048 samples are properly acquired provid-ing 848 samples before the trigger and 1200 afterwards. In orderto speed up the measurements, matrix M3, with 9 outputaccessible at the same time, was tested and each one of the eightmonitored signals were used to trigger the acquisition. Thetriggering condition takes place every time one of the acquired

signals crosses a threshold level whose value, in the SDR0 tests,was chosen around the middle of the signal dynamic andcorresponds to 3000 DAC units. Fig. 2 shows the cumulativespectrum relative to eight of nine pixels. The distance between thetwo fitted peaks is used to extract the mean value of the chargesensitivity and is about 650 mV/fC.

Beside the threshold scan methods, the digital readout has alsobeen tested in order to verify the correct operation of the digitalcircuitry. The digital readout has been successfully tested at afrequency up to 50 MHz.

4. Conclusions

A MAPS for vertexing applications at the ILC has beenfabricated using a 130 nm triple-well CMOS process. The firstprototype chips, in which for the first time a sparsification logic atthe pixel level has been implemented, were successfully tested,although issues such as the pixel pitch has to be addressed inorder to meet the ILC requirements. The results presented in thispaper are an initial step toward the design and submission in2009 of a larger matrix (256� 256 pixel) for beam test purposes.

Acknowledgments

The authors wish to thank R. Yarema and the FNAL ILC R&Dgroup for the useful discussions about the digital processingscheme implemented in the DNW-MAPS demonstrator. Theauthors are also indebted to V. Speziali for her useful suggestions.

References

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1485–1489.[8] D.C. Christian, et al., Nucl. Instr. and Meth. A 549 (2005) 165.[9] V. Re, et al., IEEE Trans. Nucl. Sci. NS-53 (4) (Aug. 2006) 2470.

[10] G. Traversi, et al., Nucl. Instr. and Meth. A 581 (2007) 291.[11] R. Yarema, 3D circuit integration for vertex and other detectors, presented at

the Vertex 2007, September 23–28, 2007, Lake Placid, NY, USA.