fit([ lee, · compared without performing detailed designs and with no knowledge of the internal...

Stress and Loss Analysis of Quasi-Resonant Converters

by

Ashraf W. Lotfi

Thesis submitted to the Faculty of the

Virginia Polytechnic Institute and State University

in partial fulfillment of the requirements for the degree of

Master of Science

in

Electrical Engineering

APPROVED:

Dr. Fit([ C. Lee, Chairman

Dr. Vatche Vl?rperiaiL(Co-Chairman

May, 1988

Blacksburg, Virginia

/DJr. Bdi. Cho

Stress and Loss Analysis of Quasi-Resonant Converters

by

Ashraf W. Lotfi

Dr. Fred. C. Lee, Chairman

Electrical Engineering

(ABSTRACT)

Quasi-Resonant Converters (QRCs) have been proposed recently in the effort of increasing the

switching frequency and reducing the switching losses. There are several merits and demerits of this

class of converters. The most important aspects of this research are to assess the advantages and

limitations of QRCs in terms of their device current and voltage stresses and a determination of the

factors affecting them. The losses in the various elements are also determined to provide a reason-

able estimate of the converter efficiency. The work in both tasks is normalized permitting a direct

comparison of one topology with another without performing any detailed design or knowledge of

the internal parameters of each converter. As a result of the analysis of switching losses, an accurate

estimation of MOSFET switching times is presented providing more insight into the switching be·

havior of these converters. Experimental results confrrm the accuracy of the theoretical predictions

of device current and voltage stresses along with the converter losses and efficiency. Factors affecting

the the device stresses derived theoretically are demonstrated experimentally. Computer simulation

is used to confrrm the theoretical analysis of transistor switching times used in determining the

switching losses in the devices.

Ackno'lvledgements

I would like to express my sincere gratitude for my advisor, Dr. Fred C. Lee.for his support

and guidance in this research. My deepest thanks go to Dr. Vatche Vorperian for his unlimited and

creative supervision of this work. I would also like to thank Dr. Bo Cho for his helpful comments

and suggestions. I must also thank all the members of the excellent VPEC group, in particular Mr.

Ray Ridley, whose help and advice has contributed in many aspects of this work and my own

knowledge. I fmally dedicate this thesis to my parents for their care and support.

Acknowledgements iii

Table of Contents

Introduction . . . . . . . . . . . . • . . . . . . . • . • . . . . • • • . . . . . . • . . . . . • . . • . . . . . . . . . . . • . . 1

Stress Analysis in PWM, ZCS and ZVS Converters . . . . . . . • • • . • • • • • • • . . . . • • . . • . . . • 3

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.2 The Design Constraint and Normalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 Peak Stresses in PWM Converters ........................................ 7

2.3.1 Effects of Line Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 Peak Stresses in ZCS-QRCs

2.4.1 Normalization of Stresses

2.4.2 Effect of Line Variation

2.5 Peak Stresses in ZVS-QRCs


. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

........................................... 26

.......................................... 28

2.5.2 Effects of Line and Load Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.6 Stress Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2. 7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Design Guidelines for Quasi-Resonant Converters . • • . . • . . . . . . • . . . . . . . . . . • . . . • . . . . 47

Table of Contents iv

3.1 Design Procedure for ZCS-QRCs ........................................ 48

3.1.1 Design of Resonant Tank Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.1.2 Evaluation of the Low-Pass Filter Inductor ............................. 50

3.1.3 Effect of Transformer Turns Ratio on Stresses . . . . . . . . . . . . . . . . . . . . . . . • . . . 52

3.2 Design Procedure for ZVS-QRCs . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . . 55

3.2.1 Design of Resonant Tank Elements ...........................•....... 55

3.2.2 Evaluation of the Low-Pass Filter Inductor ............................. 59

3.2.3 Effect of Transformer Turns Ratio on Stresses • . . . . . . . . . . . . . . . . . . . . . . . . • . 65

3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . • . . . . • . . . . . . . 69

Analysis of Loss Mechanisms in PWM, ZCS and ZVS Converters • • • • • • • • • • • • • • • • • • • • 71

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . • . . . . . • . . . • . 71

4.2 Loss Analysis in PWM Converters • . . . . . . • . . • • . . . . . • . • . . . • . . . • . . . . . . . • . • • 73

4.2.1 MOSFET Conduction Losses in PWM Converters .••...•.•••.•.....••.••. 73

4.2.2 MOSFET Switching Loss in PWM Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.2.3 MOSFET Parasitic Impedance Loss . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . • 82

4.2.4 Freewheeling Diode Losses in PWM Converters . . . . . . . . . . . . • . . • . . . . • . . . • . 86

4.3 Loss Analysis in ZCS-QRCs . . . . . . . . . . . . . . . . • . . . . . • . • . . . . . • . • • • . • • . • . . . 89

4.3.1 MOSFET Conduction Losses in ZCS-QRCs .....•..•.........•••....•.. 89

4.3.2 MOSFET Switching Losses in ZCS-QRCs . . . • . . . . • . . • . . . . . . • . • . • • • . . . • . 98

4.3.3 Freewheeling Diode Losses in ZCS-QRCs 106

4.3.4 Losses in the Resonant Tank ........................... , ...•... , . . . 108

4.4 Loss Analysis in ZVS-QRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

4.4.1 Transistor Conduction Losses . . . . . . . . . . . . • . . . . . . . . . . • . . . . . • • . . . . . . . 112

4.4.2 MOSFET Switching Losses in ZVS-QRCs . . • • . . • • . • • • • • . . • • . . • • • . • • . • . 116

4.4.3 Rectifier Diode Losses in ZVS-QRCs .......•..•.........•....•...••. , 120

4.4.4 Resonant Tank Losses . . . . . . . . . . . . . . . • . . . • . . • . . . . • . • • . . • . . • . . . . . . 121

4.5 Comparison of Losses . . . . . . . . . . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . • . . . . . . . 126

Table of Contents v

4.5.1 Conduction Losses in the Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4.5.2 Losses in the Resonant Tank of QRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

4.5.3 Comparison of Switching Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Analysis of Transistor Switching Times . . . . • . . . . . . • . . . . . . . . . . . . . . . . . . . • . . . . . . 130

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

5.2 MOSFET Switching Tum-off Time .................................. ·... 131

5.2.1 Tum-off in PWM Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

5.2.2 Tum-off in QRCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

5.3 MOSFET Switching Tum-on Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.4 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

Experimental Results and Verification . . . . . . . . . . • . . . . . . . . • . • . . • . . . • • . . . • • . . . • 166

6.1 A SOW Full-Wave Zero-Current-Switched Flyback Quasi-Resonant Converter . . . . . . 166

6.1.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

6.1.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

6.2 A SOW Half-Wave Zero-Voltage-Switched Flyback Quasi-Resonant Converter . . . . . . 175

6.2.1 Effect of Load Range on Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.2.2 Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

6.2.3 Prediction of Peak Stresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

6.2.4 Estimation of Losses in the Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Conclusions • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . 184

References . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . • • . . . . . . . . • . • • . • . . . • . . . • . . . 187

Vita .......................................................... ~ . . . . . 189

Table of Contents vi

Chapter 1

Introduction

The introduction of Quasi-Resonant-Converters (QRCs) has prompted more interest regarding

their characteristics and performance. A clear potential for high frequency operation ( into the

Megahertz range ) has been demonstrated in several experimental circuit designs. A concise the-

oretical explanation of the basic operation of these converters has been provided in [2,3,4]. How-

ever, there is a further need to understand their non-ideal performance along with their merits and

limitations. Furthermore, an analysis that would permit a simple and direct comparison of QRCs

with conventional pulse-width-modulated (PWM) converters should be emphasized. These and

other objectives are discussed in the foregoing analysis and an attempt to lay an analytical founda-

tion for an overall comparison of PWM converters, zero-current-switched (ZCS) and zero-

voltage-switched (ZVS) QRCs is presented.

The major tasks undertaken in this research can be summarized as follows

• The analysis of voltage and current stresses in PWM, ZCS and ZVS converters how they

compare to each other.

• Determining the proper design rules for QRCs that would result in an optimized design for

each topology (Buck, Boost, Buck-Boost and Flyback).

Introduction

• Investigating the major loss mechanisms encountered in ZCS and ZVS-QRCs providing

theoretical estimates of efficiency and ranges of frequency operation. (A similar analysis of

PWM converters is also performed for the purpose of comparison with QRCs.)

• An investigation of the various large-signal transistor switching times that are involved in the

transitional losses of any switching regulator. Such an analysis would provide a theoretical

estimation of these switching times.

• Establishing and utilizing a normalization technique that permits different converters to be

compared without performing detailed designs and with no knowledge of the internal partic-

ulars of each converter. A comparison can be performed directly by mere knowledge of the

specifications. This technique is used to compare QRCs with PWM converters.

These tasks are presented individually in each chapter of this work. Theoretically derived results

are verified using computer circuit simulators and experimental bread-boards. Conclusions, limi-

tations and future suggestions of this work are then presented providing a guide for extensions to

further research.

Introduction 2

Chapter 2

Stress Analysis in PWM, ZCS and ZVS Converters

2.1 Introduction

The introduction of quasi-resonant converters (QRCs) has lead to a new class of converters

capable of operating at frequencies in the megahertz range as reported in recent literature. One of

the major drawbacks of QRCs is the increased current and voltage levels in the semiconductor de-

vices as compared to much lower stresses in conventional non-resonant (PWM) converters. By

analyzing stresses in QRCs it is possible to identify the factors affecting their peak levels and thus

a proper design can be made so that stresses are minimized. Furthermore, once expressions have

been found for the stresses, a normalization technique outlined in [ 1] can be used to normalize

stresses in both PWM and QRCs to yield expressions that are independent of the internal partic-

ulars of the given converter. The resulting expressions would be functions of the given specifica-

tions (conversion ratio, M, input line variation and output load variation) and a dimensionless

design constraint, C, which to be minimized for minimal stresses within a permissible range of val-

Stress Analysis in PWM, ZCS and ZVS Converters 3

ues. Using ( the proper design of the converter is obtained to attain minimal stresses for the given

set of specifications.

Once the stresses have been normalized, it becomes a very simple process to compare stresses

in various converters. The process of choosing a certain topology becomes very simple because

relative stresses can be found directly without going through the actual design procedure of each

topology.

Section 2 of this chapter explains the concept of the design constraint and subsequently the

normalization process.

Section 3 deals with the peak stresses in PWM converters. The design constraint and normal-

ized formulas are presented.

In section 4 stresses in zero-current-switched (ZCS) QRCs are obtained and normalized. Stress

dependencies are outlined.

Section 5 presents the normalized results for zero-voltage-switched (ZVS) QRCs and it is

shown that the specified load range becomes a major factor affecting the voltage stress and must

be taken into consideration in the design process.

With all the formulations normalized, section 6 presents the stress comparison of PWM, ZCS-

and ZVS-QRCs in the Buck, Boost and Buck-Boost topologies. The effect of the turns ratio, n, in

the flyback converter is also discussed.


2.2 The Design Constraint and Nonnalization

We first start by explaining the idea of the design constraint C • Expressions for the actual

stresses can be extracted from the actual current and voltage waveforms of each given converter.

Peak values extracted will depend on several particulars of the converter at hand. In PWM con-

verters the peak current stress, IP, will be of the form

where f. is the switching frequency, L1 is the fllter inductor, R is the load resistance and Dis the duty

ratio. On the other hand, in QRCs the peak stresses have a different form. For instance, the peak

current stress in ZCS-QRCs has the form

IP = .flJ., M, R, Z.)

where z. is the characteristic impedance of the resonant tank. Similarly, the peak transistor voltage

stress for ZVS-QRCs has the form

Vp =fl.. V., Af, R, Z.)

These expressions and those for the diode stresses are dependent on the each converter's particulars;

L1 and f. for PWM converters and z. for QRCs. The only possible way to compare these converters

would be to design each one separately and then calculate the peak stresses in each. It is thus de-

sirable to normalize these expressions so that they depend only on the given specillcations along

with a dimensionless quantity C, which for any converter, must be minimal for minimal stresses over

its permissible range. We thus search for C such that

(2.1)

/peak = j',_(M, C) (2.2)


where Vpeak is the normalized peak voltage stress = ~/ V. , and Ip•ak is the normalized current stress

= IP/ I. and ( is the design constraint.

The design constraint will relate to the given converter particulars. In PWM converters ( is

related to the inductor ripple, !ilL , while in QRCs it is related to the characteristic impedance, z .. Minimizing C in the design process will result in minimal stresses. It is also found that C will be

constrained over a range of values in order to ensure proper operation of the converter. For example

in PWM converters the ripple cannot be smaller than zero and this will impose a constraint on(.

Once we have arrived at Eqs. (2.1) and (2.2) then direct comparisons between various converters

can be made without any detailed design.


2.3 Peak Stresses ill PWM Cotlverters

The actual values of the peak current and voltage stresses can be obtained from the actual

waveforms existing in the circuit. We will consider Buck, Boost and Buck-Boost PWM converters

shown in Fig. 2.1a operating in continuous conduction mode (CCM).

Let

Ipr = peak transistor current

V,r = peak transistor voltage

IpD = peak diode current

v;.D = peak diode voltage

I L = de current in L1

l1I L = ripple in L1

I.= de output current

I, = de input current

v.. = de output voltage

V1 = de input voltage

M = de conversion ratio = V.fV,

Figure 2.1 b shows the current waveform in the ftlter inductor. We can see that the peak current

depends on the amount of ripple in L,. If we defme lx as

I, Buck

lx = 11 Boost

111 + 11 Buck-Boost

then we can can determine the peak current in L1 to be


(2.3)

7

Buck VG R

(a)

lmax --------T-·

----------------~------

I AIL _.;__

I min

DTs ' DTs

(b)

Figure 2.1 a) Circuit diagrams of typical Buck, Boost and Buck-Boost converters. b) The current waveform in the filter inductor of any PWM converter.


Similarly, the peak voltage stresses in the transistor and diode are found to be

where

V~ = Vo Boost (2.4)

V" + ~ Buck-Boost

It is evident that the peak voltage stresses depend solely on the application ( v. and ~) whereas

the ripple in L1 has a direct effect on the peak current stress. A proper design would try to minimize

the quantity L1ILfl~ which, with an infmite inductor L1 , would be zero. It is thus apparent that the

design constraint Cc for PWM converters in CCM is given by

(2.5)

where (cis a design constraint on the current in L1 in PWM converters representing its percent ripple

(different values of Cc will be defmed for ZCS-QRCs). This constraint should be made as close as

possible to zero for minimal stresses. Ideally Cc = 0.0, however a practical choice of 0.1 is acceptable.

Using this defmition of Cc the normalized current stresses can be readily found.

For the Buck converter

I I ...!.!... =..!!?.... = (1 + 0 I. I.

(2.6a)

For the Boost converter


For the Buck-Boost converter

The peak voltage stress is given by

1

vpr vpD M -=-=1 v. v. 1

l+-M

2.3.1 Effects of Line Variation

Buck

Boost Buck-Boost

(2.6b)

(2.6c)

(2.7)

Converters are usually designed to satisfy a set of specifications which include a range of input

volt~ges ( V8 min - ~max) and a range of output loads (!.min - I. max>· Equations (2.6) and (2. 7) are for

a single application (M, I.). Over its range operation, the converter will experience a maximum

peak stress (Ip max , v;, max> at some point.

It is seen from Eqs. (2.6) and (2.7) that the maximum peak current stress occurs at full load

(!.max) and low line (Mmax) , whereas the maximum peak voltage stress occurs at high line (Mm;n)·

Then for both the transistor and diode by making these substitutions in Eqs. (2.6) and (2.7) we

arrive at

I 1 + Cc ;max = Mmax(l + Cc)

omax (1 + Mmax)(l + Cc)

and


Buck Boost Buck-Boost

(2.8)

10

VpT,.,o,r

v.

(a)

(b)

0

0

0 If) . r--

8 If)

0 If)

N

0.5

Mmi.n

Buck.

1.0 1.5 2.0 2.5

Mmu

Figure 2.2 Effect of conversion ratio on: a) Peak voltage stress and b) peak current stress in PWM converters.

Stress Analysis in PWM, ZCS and ZVS Converters II

Buck

Boost

Buck-Boost

Figure 2.2 shows the effect of varying M on IP max and ~max .


(2.9)

12

2.4 Peak Stresses in ZCS-QRCs

The ZCS-QRC goes through four topological modes [3,4}. The peak current of the switch and

the reverse voltage across the diode both occur during the resonant stage. Their corresponding time

functions are given by

(2.10)

where ir(t) and vD(t) are the instantaneous transistor current and reverse diode voltage respectively

and

z. = J 2 = characteristic impedance of the tank

w. = .;&. = tank resonant frequency L.c.

Figure 2.3 shows the transistor and diode current and voltage waveforms from which the peaks are

extracted. Hence, from Eq. (2.10) the peak transistor current is

Ipr=I.+ ~· 0

(2.11)

Also from Figure 2.3 the peak voltage is

(2.12)

As for the diode, we have from Eq. (2.10) and Fig. 2.3


l I I Transistor current li(\1--""-lx

I ~ v I 'CJ

Diode voltage

I I

Transistor voltage vxH (

Diode Current 'xK \ timt:

I l I 1 ~ l 1 l I'

mode interval r; 7i 7j 7;,

Figure 2.3 Transistor and diode time domain waveforms of the ZCS-QRC.



In order to fmd the proper design constraint, Cc, it is necessary to examine the de conversion

characteristics of ZCS-QRCs. A typical characteristic is shown in Fig. 2.4. It is noted that the

characteristics always terminate beyond a certain point where the zero-current-switching property

is lost.

Let Q, = R, = ZR =normalized load resistance, (similar to the quality factor in a parallel W~c D

resonant circuit). Then, for any topology, the ZCS property is lost whenever M > Q,. A proper

design would ensure that M ~ QP for the entire range of operation. In other words,

Q,_ ~ 1 for proper operation M

(2.14)

The peak transistor current stresses can be expressed in terms of the ratio ~ . Manipulating Eq.

(2.11) we get

For the Buck ZCS-QRC

(2.15a)

For the Boost ZCS-QRC

lpr =M(l + QP) la M

(2.15b)

For the Buck-Boost ZCS-QRC

Stress Analysis in PWM, ZCS and ZVS Converters IS

M

M

Q ·r--· p=lO 0 5.0

I V g v I v 0 l I v / 0 co I v v /

/ 0 !I v

/ _0.

0 ... I v /~ / 0 If I / v ~ rfj [,0 / 0

~ v

o.zo o ... o 0.60

(a)

0 Cl)

z.o l .0

I/ 1/ /

/

0.80 1.00

Qp = 10.0 1.0 v

Vi 0 / 0 co / 0 I v 0 ... v u., 0 / !

R v 0 v 0 ~ / '1:l.oo o.zo 0.60 0.80 1.00

(b)

fs

fo

Figure 2.4 Typical de conversion ratio to switching frequency characteristics of a Buck ZCS-QRC. a) Half wave mode. b) Full wave mode.


IpT = (1 + M)(l + Qp) 4 Jlf

(2.15c)

The ratio QP/ M also plays a significant role in detennining the current waveform during reso-

nance and hence, the peak current. A proper design would use a value of QP/ M that permits lowest

possible stress while still maintaining zero current turn off. Figure 2.5 shows the switch current

during resonance with different values of QP/M. With the limiting value of 1.0, it is clear that the

peak is lowest and while simultaneously zero current turn off is maintained ( at the border ). It is

also interesting to note that an increased value of QP/ M will result in excess reverse current which

in tum increases the conduction losses, another reason to minimize (1/M.

Now that the effect of QP/M on the design has been established, we can identify QP/M as a

dimensionless design constraint and thus

(2.16)

Substituting Eq. (2.16) into Eqs. (2.15) yields the normalized expressions for current stress in

ZCS-QRCs. Notice that the design constraint , Cc, appears only in expressions for the transistor

current stress whereas the voltage stress is independent of Cc • This is because Cc is related to the

characteristic impedance, Z11 of the resonant tank, and it is the switch current, not voltage, that

resonates. A similar discussion holds for the diode voltage and current. These stresses are simply

given by Eqs. (2.12) and (2.13).

2.4.2 Effect of Line Variation

As stated earlier, a range of input voltages and output currents is always specified. This trans-

lates into the two specifications


~4-----------i-----------+-----------4-----------J 'o 20 40 time

60 80

Figure 2.5 The effect of varying the ratio Qpl M on the transistor current waveform in a ZCS-Q RC.


8 10 0 _5_:) Z 0 I 0

v., M=-v, s

L v '/ ~ I{ I v v

0 I _L v / v

2 0

MfNX -0 ~ 0

Mm.in -2

k;max V LV I I v /Os.S

L v v ~ v II / v: Vo. 1/j ~ v mm

0

~ 8 v '1l .00 o.zo o.4o I 0.60 0.60 I. 00

/min fmu

Figure 2.6 Tile region of operation of a ZCS-QRC for the ranges of line and load variations given in Eq. (2.17) showing the minimum and maximum switching frequencies.


lvf min :$; 1\1 :$; i'vf max Rmin :$; R :$; Rmax

(2.17)

These two specifications can be outlined on the de conversion characteristics to form a region over

which the converter will operate and consequently the range offrequenciesf.min tof.max· Figure 2.6

shows this range of operation. In defining this region we must ensure that the design constraint,

Cc is satisfied. This means that the point ( Mmax• Qpmin ) must lie at the terminal point of the char·

acteristics to ensure zero current turn off. Since this point is the boundary between zero and non-

zero switching, one would make a design at a point slightly below the terminal point. This would

guarantee ZCS and would also take into account possible component drifts or variances from their

nominal design values. Hence our design constraint would be made slightly higher than unity and

would be defined as

(2.18)

From Eq. (2.15) we can see that Ipr is a maximum when 10 =lomax and V, = V,max, i.e. at full

load Qpmin and high line Mm;n· Using these values along with Eq. (2.18) we can obtain the maxi-

mum peak current stress Iprmax • If the nominal value of the input voltage is V,nom then we can

deftne the percent line variation , <5, as

0 = ~nom- ~min ~""m

t <5 < 1.0 (2.19)

vgnom could be taken as the midpoint between v, min and ~max . The line variation 0 is related to

Mby

(2.20)

We can thus derive the following expressions for the stresses.


a)Buck converter:

i)Transistor stresses

ii)Diode stresses

b)Boost converter:


ii)Diode stresses

c)Buck-Boost converters:


/pTmax = 1 + ".~-_-2_ 1' 1 Q .. ' ... ~ . f. max 1 - c5 1 - c5

V,rmax =-1-V. Mmin

fpDmax = l lomax

VpDmax =-2-v. Mmin

fpTmax = Mmax(l + C.) VpTmax = 1 v.

[pDmax -M I - max

omax

VpDmax = 2 v.

1) The current stress is obtained by using Eq. (2.15c),

~r (M) = (1 +M)(l + Q~;n) = (1 +M)(l +C. M;t) 0


(2.21)

(2.22)

(2.23)

(2.24)

(2.25)

21

0 U)

{pTma:r: .

(\J -10

0 0 0 -0 U) ·------~--~~~------------~~~ .

8 U)

l I I

0 (c i\JL N[mav: U) I

• "b (b) (a)

3 4

Mmin M

Figure 2.7 The peak current stress of a lluck·lloost ZCS·QRC as a function of M showing the two possible cases (a) and (b) for maximum peak stress.


which is plotted in Fig. 2.7. This equation is parabolic in nature and has a local minimum at

M = }.;[ L given by

(2.26)

From Fig. 2. 7 we can see that the maximum peak current stress can occur at either Mm;n or Mmax

depending on the relative value of Mmin with respect to C • • This gives rise to two distinct cases:

Case (a): Mmin > Cc ~1.0

In this case the maximum peak current stress will occur at M = M max and we get

(2.27)

Case (b): Mmin < Ca ~1.0

Figure 2. 7 shows that in this case the maximum peak current stress will occur at M = Mmin and

hence from Eq. (2.25) we get

(2.28)

If we use the approximate value of 1 for C., then Eq. (2.28) can be approximated by

(2.29)

This equation is plotted in Fig. 2.8 which shows that with no line variation (o = 0) the current stress

is double the input and output currents and increases rapidly as the specified line variation increases.

2) The transistor voltage stress for both cases (a) and (b) is given by

(2.30)

ii)Diode stresses


co

(!)

N

9J.oo 0.25 0.50 0.75 1.00

Line variation, b

Figure 2.8 The effect of line variation on the maximum peak transistor stress in a Buck-Boost ZCS-QRC.


I ;Dmax = 1 + 1'1max omax (2.31)

VpD max = 2( 1 + _1_) Vo Jvfmin

It is clear that the transistor switch experiences a maximum peak current that increases as the

line variation increases (for Buck and step down Buck-Boost converters). However, the voltage

stress depends on lvfmin and increases as the maximum line voltage increases.


2.5 Peak Stresses in ZVS-QRCs

The zero-voltage, quasi-resonant switch is the dual of the zero-current, quasi-resonant switch

[4J. As a result dual relations are expected since the switch voltage resonates in the ZVS-QRC in a

similar fashion when compared to the switch current in a ZCS-QRC. However, a distinct difference

exists when we examine the the de conversion characteristics of ZVS-QRCs. Compared to those

of a ZCS-QRC, the characteristics of a ZVS-QRC always have a negative slope with respect to the

control parameter f./f. . This reversed slope will cause the terminal constraint point ( where

QP = M ) to have a reversed dependency on QP and M when compared to that encountered in the

ZCS case. Consequently new dependencies will appear in the stress expressions that did not exist·

previously in the ZCS-QRC, namely the variation in load current (!.min- lomax) . This range will

be shown to be the major factor affecting the voltage stress in ZVS-QRCs.

First we extract the peak stresses from the actual circuit waveforms that exist in any

ZVS-QRC. The ZVS-QRC goes through four topological modes [4}. The peak voltage stress of

the switch and peak forward current in the freewheeling diode both occur during the resonant stage.

Their corresponding time functions are given by

vr{t) = Vx + IxZo sin w.t in(t) = /x(l -cos w.t)

(2.32)

where vr{t) and iv(t) are the instantaneous transistor voltage and diode current respectively. Figure

2.9 shows the transistor and diode voltage waveforms from which the peaks are extracted. Hence

from Eq. (2.32) the peak transistor voltage is given by

(2.33)

while from Fig. 2.9 the peak current is

(2.34)


Transistor voltage

resonant current

Diode voltage

Transistor current

mode interval

v~h

I I '(\1 I I ! 1xZo

vx LS: lx

vx

lx

I I

D I I

H l L

If 1 ,,

I I I rn

t I, 1

(\ ~\

\

I .. time

Figure 2.9 The time waveforms of the transistor and diode voltages and currents in a typical ZVS-QRC.


As for the diode we have from Eq. (2.32) and Fig. 2.9

(2.35)


As was discussed in the ZCS-QRC case, it is the terminal point on the de conversion charac-

teristic that is used to determine the design constraint, C • • From Fig. 2.10 we can see that the

ZVS-QRC loses its zero-voltage switching property whenever QP > M. A proper design would en-

sure that QP :::;; M for the entire range of operation In other words, for proper operation we must

have

(2.36)

The peak transistor voltage stress can be expressed in terms of the ratio ~ . Using the definition

of QP and /x in Eq. (2.32) we can obtain the following.

For the Buck ZVS-QRc

(2.37a)

For the Boost ZVS-QRC

(2.37b)

For the Buck-Boost ZVS-QRC


M

g

0 Cl

0 I~ 0.9J

~ 0.00

l\ "" 0 <D ., 0

0 .... 0

2 0

0 0

--·

1-

'b.oo

I~

1\ f\_ \ "\

f\ '\

0.20

0.00

0 <D ~ 0.80 0

I~

""" ~0.50 ~

"'""' "' b-... "' 1-~

""' r:-, "" 0.2C ~ ..............

~ 0. ~--

0

0.60 0.80 1.00

(a)

0 <D ~ 0

0 .... a

0 N

a

a 0

<=tJ. 00 o.zo

'""' 0.50

~~

"" 0.60

Is fa (b)

"' o.zo

~= p 0. 0

0.80 1.00

Figure 2.10 Typical de conversion ratio to switching frequency characteristics of a Buck ZVS-QRC. a) Half wave mode. b) Full wave mode. Notice the terminal points beyond which lhe ZVS property is lost.


(2.37c)

The ratio ~ clearly has a direct effect on the peak transistor voltage stress and our design goal

would be to minimize this ratio. However, as stated in Eq. (2.36) this ratio cannot be less than 1.0

if zero-voltage switching is to be maintained. We can thus identify the design constraint, C. , for

ZVS-QRCs as

'· = ~ ' '· ~ 1.0 (2.38)

Substituting this value into Eq. (2.37) yields the normalized stresses for the transistor voltage in

ZVS-QRCs. These expressions are for a single input voltage and single load application. Variations

in line and load are dealt with next.

2.5.2 Effects of Line and Load Variations

As stated in Eq. 2.17, the variations in line and load are specified and can be formulated as

A/min:::;; Jv[:::;; Mmax

Rmin :::;; R :::;; Rmax (2.39)

A proper design ( with c.~ 1.0) would result in defming a region of operation on the de conversion

characteristics ( Fig. 2.11 ) such that the value of QP max is at most equal to M min • When

QP max = Mmin then the converter will operate at the border point of zero- and nonzero-voltage

switching. Thus we would shift QP max slightly lower in order to guarantee ZVS in case of any

component drifts or variances. This would lead to defming the design constraint as

(2.40)


8

0 CD 0

0 <0

0

0 ... c:i

~ Mmin- c:i

~~ \

--

~ l\ ~ 1\ 1\.

\ "\

1\.

"' ---

f-· 0 0

'b.oo 0.20 I

"' ~ ~ ~

"'~ 2min ..... Q.,max

'~ -~ ... '~

0.60

~ ~

0.80 I

.£max

1--

--

1.00

Figure 2.11 The region of operation defined by Eq. (2.39) showing the corresponding minimum and maximum switching frequencies for a ZVS-QRC.


The peak voltage stress is a maximum when ! 0 =fa max ( full load ) as seen from Eq. (2.33). If

we denote the load variation by £1R where

A = fa max = Rmax A > 1 0 LJ.R I R ' LJ.R- •

o min min (2.41)

then we can readily write QP min in terms of(. as

(2.42)

The normalized stresses can now be derived as follows

a) Buck converter:

i) Transistor stresses

From Eq. (2.33) we have

Hence the peak maximum voltage stress will occur at full load (Qpmin) and high line (Mm;n)· Using

these facts in Eq. (2.37a) along with Eq. (2.42) we get

ii)Diode Stresses

=-1-(1 +(.£1R) Mmin

fpTmax = l /a max

V:,D max = _1_ V. A1min [pDrnax = 2 fa max


(2.43)

(2.44)

32

b)Boost converter:


From Eq. (2.33) we have

vpT = vo + IgZo

= V0 +M/02 0

Hence the maximum peak voltage stress will occur at low line (Mm.J and full load {Qpmin)· Using

Eqs. (2.37b) and (2.42) we arrive at

The maximum peak current stress also occurs at low line and thus,

ii)Diode stresses

c) Buck-Boost converter:

i) Transistor stresses

VpDmax = l vo

/pDmax =2M lomax max

The maximum peak voltage stress occurs at full load and is a function of M given by


(2.45)

(2.46)

(2.47)

(2.48)

33

w----------~--------~--------.---------, N

0 N

0

l1tJ. 00

M

0.60

(b) (a)

Figure 2.12 The peak transistor voltage as a function of M. Cases (a) and (b) for maximum peak stress are shown.


This equation is plotted in Fig. 2.12 and is parabolic in nature with a local minimum , ML given

by

It is clear that VP:r(M) has identical values at both M = Mmin and M = ~. The relativty position "'•dR

of Mmax with respect to r ~ determines where the maximum peak stress will occur which gives "'• R

rise to two cases:

1 Case a) M max > "'Y'"T "'• R

From Fig. 2.12 we can see that the maximum peak voltage stress will occur at Mmax and hence,

(2.49)

Case b) Mmax < r ~ "'• R

In this case the maximum peak voltage stress will occur at Mmin and hence,

v;.Tmax = (1 + _1_)(1 + (.d~ V. Mmin

(2.50)

The maximum current stress in both cases (a) and (b) is given by

~Tmax = (1 + Mmax) omax

(2.51)

ii) Diode stresses

1+-1-Mmin

(2.52)

Stress Analysis in PWM, ZCS and ZVS Converters 3S

and

I,v max. = 2(/. max. + I& max)

or I;vmax = 2(1 +Mmax) omax.

(2.53)

At this point it is important to notice the dependencies in the transistor voltage stress given

by Eqs. (2.43), (2.45), (2.49) and (2.50).

Firstly, all the transistor voltage stresses depend on the output load variation in an adverse

fashion, whereas such a dependency did not exist in ZCS·QRCs. lbis dependency imposes are·

striction on how wide a load range can be accommodated by the converter while still maintaining

zero-voltage switching. A compromise between load range and maximum peak stress could be

necessary since it is clear from these relations that the larger the load range the higher the switch

voltage becomes. lbis dependency is illustrated in Fig. 2.13 which shows how the normalized stress

can become exceedingly high for large load ranges. For low voltage applications these stresses could

be accommodated, however, for higher voltage applications such stresses would be impractical with

currently available devices. It is clear that a compromise between load range and maximum peak

stress could be necessary if the stresses are to become too high. It is always desirable to use low

voltage devices since they have lower on-state resistance. ZVS-QRCs can maintain their zero-

voltage switching property from full load down to some minimal load (/0 min) but cannot operate

at no load as seen from Fig. 2.11 ( the curve Q, = oo does not exist ). If the load is reduced beyond

I() min efficiency degradation occurs due to nonzero-voltage switching, which is the dual situation of

ZCS-Q R Cs. They can operate from no load up to their rated maximum load (/0 max> beyond which

the zero-current switching property is lost, (which is a more practical operational characteristic).

However, as shown before, the effect of load range variation did not exist in ZCS-QRCs. The cur-

rent stress is always proportional to the maximum desired load current.

Secondly, an input line dependency similar to that in the ZCS case is observed for dual net·

works, e.g. ZC-Buck and ZV-Boost , step down ZC-Buck·Boost and step up ZV-Buck-Boost

converters. Line variation is also shown to contribute to increased stresses in ZVS-QRCs along with


0 en

lJ)

CtJ .00 0.25 0.50 0.75 1.00

Line variation, b

Figure 2.13 The effects of line and load variations on the maximum peak transistor voltage stress in a Boost ZVS-QRC.


load variation. Hence wide load and line variations could result in very high voltage stresses in

ZVS-QRCs. However the effect of line variation is much less pronounced when compared to load

variation. The stress increases gradually with line variation while very rapidly with load variation.

2.6 Stress Conzparison

The various stress expressions obtained in the previous sections in their normalized form can

be used to compare stresses in converters of different topologies. Direct ratios of transistor and di-

ode stresses in one converter to another are readily obtained because the stress expressions do not

contain particulars of the given topology, but only design specifications. Converters within the same

family (Buck, Boost and Buck-Boost) will be compared to each other since usually a given set of

specifications will be suited to, and satisfied by one family.

In construction of these ratios the following notation will be used:

and similarly,

/pT (Zcs> maximum peak transistor current in a ZCS-Q R C --'--'---'-=----_..:._ ____________ ....:;___

/pT (Zvs) maximum peak transistor current in a ZVS-QRC

Vpo (ZVSl

VpT(PWM)

maximum peak diode voltage in a ZVS-QRC =------~-----~---------maximum peak diode voltage in a PWM converter

1- Buck Converters

a) Transistor Stresses:

From Eqs. (2.8), (2.9), (2.21) and (2.43) we obtain


and

I pT <zvs> ~ 1.0 Cc~o.o

/pT (PWM)

/pT (ZCS) ,...., _2_ I - 1- J pT (ZVS or PWM)

VpT (ZCS) = l.O VpT(PWM)

vpT (ZCS or PWM) = 1 + C • .1.R

(2.54)

(2.55)

Figure 2.14 shows the effect of load variation on the voltage stress when Buck ZVS-QRCs are

compared to Buck ZCS or PWM converters.

b) Diode Stresses:

and

2- Boost Converters


Ipo (Zcs) "'- 1.0 0 Cc~ .0 fpD(PWM)

Ipo (ZVS) - 2.0 fpD (ZCS or PWM)

vpD (ZVS) = l.Q VpD (PWM)

VpD (ZCS) = 2_0 VpD (ZVS or PWM)

/pT (ZVS) ~ l.O Cc ~ l /pT (PWM)

I pT (ZCS) = 1 + c.~2.Q

fpT (ZVS or PWM)


(2.56)

(2.57)

(2.58)

39

VpT (ZVS)

VpT (PWM or ZCS)

0 0 00~--------~--------,---------~--------.

0 0

CD

0 0 .

8 N

8 -~--~----~-------+---------r------~ 0

2 3 4 5

Load range, ~R

Figure 2.14 Comparison of transistor voltage stresses in Buck ZVS, ZCS and PWM converters.


and

VpT {ZCS) = l.O VpT(PWM)

VpT {ZVS) 1 + 0 V = l+(v~R~

pT (ZCS or PWM)

(~R +1) + (~R -1)0 ----------------1-o

(2.59)

Figure 2.15 shows the relative voltage stress on the transistor in a Boost ZVS-QRC when compared

to a ZCS or PWM converter. It is evident that a Boost ZVS-QRC will always have higher voltage

stresses when compared to ZCS or PWM converters for the same application.

b) Diode Stresses:

and

3- Buck-Boost Converters


For Mmin < (.

lpo <ZCs) ~ l.O /pD(PWM)

lpo (ZVS> ~ 2.0 lpo (ZCS or PWM)

Vpo (ZVSJ = l.O VpD(PWM)

VpD (ZCS) = 2.0 vpD (ZCS or PWM)

/pT (ZVS) --l.O O (.~ .0 /pT(PWM)


(2.60)

(2.61)

(2.62)

41

VpT(ZVS)

VpT (PWM or ZCS)

0 en

I.{)

9J.oo

fl.R= 16

0.25

2

0.50 0.75 1.00

Line variation, 1J

Figure 2.15 Comparison of transistor voltage stresses in Boost ZVS, ZCS and PWM converters.


and

/pT (ZCS) -:---'---'----'-- = /pT (ZVS or PWM)

1 + 1\4min 2 l+Mmax 1-o

2 ~ ------="------

1- 0 1-Mmin 1 +Mmin

/pT (ZCS) ~ 2_0 /pT (ZVS or PWM)

v pT (ZCS) = l.O VpT(PWM)

v pT (ZVS) = l + (_~R

f/pT (ZCS or PWM)

VpT(ZVS) ---_...:.__:____;__ = VpT (ZCS or PWM)

(2.63)

(2.64)

(2.65)

(2.66)

(2.67)

Figure 2.16 shows the current stress in a Buck-Boost ZCS-QRC when compared to a ZVS

or PWM converter as a function of line variation and minimum conversion ratio, Mmtn. Notice that

as the maximum input voltage increases, the ZCS-QRC becomes more stressed while the ZVS and

PWM converters are unaffected.


VpT (PWM or ZCS)

(b)

Line variation, ~

/pi (I'WM or ZVS)

Mrrun = 0.2

(a)

ctJ.oo 1.00

Line variation, o

Figure 2.16 Transistor stresses in Buck-Boost converters. a) Comparison of current stress. b) Com· paris on of voltage stress.


Equation (2.66) is identical to Eq. (2.55) since in this case (Mmax. < ~) the Buck-Boost ... LlR

converter is performing a step-down operation similar to the Buck converter. Equation (2.67) is

shown in Fig. 2.16 for two values of M max. • The load variation is seen to increase the stresses in

ZVS-QRCs when compared to ZCS or PWM converters.

b) Diode Stresses:

and

/pD (ZCS) ~ J.O /pD (PWM)

/pD (ZVS) ~ 2_0 /pD (ZCS or PWM)

Vpo (ZVS) = l.O VpD(PWM)

VpD(ZCS)

VpD (ZVS or PWM) 2.0

(2.68)

(2.69)

At this point we can make the following conclusions. For properly designed converters (i.e.,

with minimal values of(), it is clear that quasi-resonant-converters will always have stresses greater

than or equal to those of of PWM converters. In particular it is noticed that ZCS-QRCs always

have higher transistor current stresses, whereas ZVS-QRCs always have higher transistor voltage

stresses. On the other hand, ZCS-QRCs always have double the diode voltage stress, whereas

ZVS-QRCs always have double the diode current stress when compared to other converters (a dual

situation). It is also clear that the diode stresses are much lower than the transistor stresses (except

in flyback converters where the diode experience either elevated current or voltage levels ). More

attention during design should thus be given to the choice of the transistor since it is the most highly

stressed component in the circuit. The curves in Figs. 2.14, 15 and 16 can be used to determine

beforehand the relative stresses that would be incurred in PWM ZCS- and ZVS-QRCs for a given

set of specifications.


2. 7 Conclusions

The analysis of this chapter is performed in a normalized fashion to facilitate the comparison

of stresses in different converters without actually performing a detailed design procedure. As a re-

sult, several factors have been identified that affect the voltage and current stresses.

In ZCS-QRCs it is shown that the percent line variation is the major factor affecting the cur-

rent stresses. Voltage stresses are unaffected and are the same as their PWM counterparts. In

ZVS-QRCs it is shown that both the line and load variations have adverse effects on the voltage

stresses while the current stresses are the same as their PWM counterparts. In particular, the effect

of load range is shown to be severe and very critical in the design of ZVS-QRCs.

As a result of this analysis, proper design guidelines must be derived in order to ensure that the

stresses are as low as possible while still maintaining the beneficial properties of low loss switching.

Such a task is undertaken in the following chapter.


Chapter 3

Design Guidelines for Quasi-Resonant Converters

In this chapter, the design equations for ZCS- and ZVS-QRCs are derived with the objective

of minimal stresses. Results presented in the previous chapter are utilized to arrive at these

equations. Our objective is to design the values of the tank and ftlter elements so that the current

and voltage stresses are as low as possible for the specified input line and output load ranges. An-

other approach would be to make this design, but with the extra constraint of a maximum per-

missible voltage or current stress (this could be particularly important in ZVS-QRCs where the

voltage stress can become much higher than the available device ratings). This could require cal-

culating a more restricted range of operation if the original design exceeds the maximum ratings.

The following specifications are assumed to be known apriori.

b) /omin:::;; fo:::;; lomax

c) Vo specified

Design Guidelines for Quasi-Resonant Converters 47

d) Maximum specified switching frequency,.fsmax

e) Maximum percent ripple, e1 , in ftlter inductor, L1 , where

(3.1)

f) Maximum allowable switch current, /,max and voltage V.max.

3.1 Design Procedure for ZCS-QRCs

3.1.1 Design of Resonant Tank Elements

We ftrst determine z. followed by w. and consequently the resonant elements L. and C., .

From the specifications, Rmin = 1 v. and by using Eq. (2.18) we can determine the corresponding omax

value of the characteristic impedance.

(3.2)

which is the proper value of impedance that guarantees minimal switch current stress. Next we

determine the resonant frequency w. ( or fo ). From the de conversion characteristics of any

ZCS-QRC we observe that the maximum switching frequency occurs at QP = Qpmin and M = Mmax

These characteristics are expressed analytically by use of the quasi-resonant function F( ~, n) [5]

which is given by


ivf n . -t M ~t1 Qp nJ Qp 2 F(-,n) = mr- ( -1) sm (-) +-'-+-- ( -1) (-) -1 Qp Qp 2Qp M A1 (3.3)

n = 1 for half-wave (HW) mode n = 2 for full-wave (FW) mode

The conversion ratios are expressed as [5]

Buck:

Boost: (3.4)

Buck-Boost:

Substituting M = Mmax, QP = Qpmin (i.e. ~:min =C.) and f.= !.max into Eq. (2.55) we can obtain lVlmax

the value of the resonant frequency by solving the resulting equation. However, further simplifi-

cation can be made if we use the following property ofF( ~ , n) :

F ( 1.\ , n) = 6.29549::::: 211' , with an error of less than 0.2 % (3.5)

Thus we may approximate F(l/(., n) by 21r since C.::::::l.O. We thus arrive at a simplified solution for

Buck:

Boost: (3.6)

Buck-Boost:

Since f. = Jcc: and Z, = Jf , then L, and C, are readily found as: 21r L.c. •

i) Buck ZCS-QRC:


ii) Boost ZCS-QRC:

iii) Buck-Boost ZCS-QRC:

(Mmax -1) 2

1Vfmax

1

(3.7)

(3.8)

(3.9)

Equations (3.7) , (3.8) and (3.9) provide the design for the tank with guaranteed minimal stresses.

This equation is valid for all the topological variations utilizing a zero-current resonant switch (L,

T and Pi sections [ 5]).

3.1.2 Evaluation of the Low-Pass Filter Inductor

Knowing the value of L. it is now possible to determine the relative size of L1 with respect to

L. for the specified percent ripple ~/. An accurate approach to this problem is presented in [8,9}

by solving the topological modes ofthe ZCS-QRC with the assumption that L1 isfinite. This gen-

erally complicates the solution because of introducing an extra state, iJJ). The results of this ap-

proach are presented for the ZCS-QRC case. However, an approximate, but simpler approach will

be used for the ZVS-QRC.


As given in [9], the ripple current in L1

is found to be (for a ZCS-Buck QRC)

2V8 -1 L ~ 11/Lt= , L L) [(1- M)(1t- cos ,8) + (1 + Af-L" )'-.jl- ,8 ]

(I) o( o + 'f 'f

where

For sufficiently small ripple in L1 we require that L1 > > L. and by noting that maximum ripple

current occurs at high line (Mmin), then by utilizing defmitions of Eqs. (2.18) and (3.1) we may

simplify this equation to become

4 '· 1 + c5 -1 T.~ !;/ ~[(1- Mmin)(1t'- COS (1- Mmin)) (3.10)

+ .}(2- Mmin)Mmin]

Using the same approach the following expressions can be evaluated for the Boost and Buck-Boost

cases.

Boost converter:

(3.11)

Buck-Boost converter:


Lr Cc -1 1 -~- [n- cos (-____::. __ Lo e1 1 + ivfmax 1 + Mmax (3.12)

+ J-M-max_(_2 -+-iV.-1 m-.J-J

It is shown in [1] that smaller filters can be used in the square wave variation of the ZCS-QRC

(discussed in [ 5} ) for the same current ripple in L1 .

3.1.3 Effect of Transformer Turns Ratio on Stresses

A fmal design aspect that we will consider is the effect of the turns ratio, n of the transformer

in a flyback (Buck-Boost) ZCS-QRC on the stresses. The circuit in Fig. 3.1 shows the flyback

ZCS-QRC with secondary side resonance [10]. The stresses in this converter can be analyzed ex-

actly like a non-isolated Buck-Boost converter by simply reflecting the secondary side to the pri-n

mary. In order to gain insight into the effect of the choice of the turns ratio, n = _P on the peak n, stresses they are obtained with n as an explicit factor.

Let M = ~o (as previously defmed ). The characteristic impedance Zo is assumed to be cal-& .

culated on the primary side and thus for the circuit in Fig. 3.1

(3.13)

where a primed quantity indicates an impedance reflection from the secondary to the primary. We

thus defme Q'P = ~ = ; since Q{J is also calculated on one side of the transformer, i.e., 0

(3.14)

Starting with Eq. (2.11) we can show that

I Q'n _!!_. = (j_ +M)(l + _P_)

lo n M (3.15)


_______ L_k,L~rn--~~~------~--~

RL VG • Co

Figure 3.1 The Flyback ZCS-QRC with secondary side resonance.


The maximum peak current stress occurs at full load (QP min) giving rise to

(3.16)

Equation (3.16) has a local minimum ML at

(3.17)

with identical values at both M = M;ax and M =C •. The two cases (a) and (b) discussed in section

2.4.2 thus arise.

Case a) Mmin >C.

Case b) Mmin <C.

Transistor Voltage Stress:

Diode Stresses:

I;rmax = ( ~ + Mmax)(l +C.) omax

/pTmax ( 1 M 2 ~n+ min)~

omax

VpTmax = n + _1_ V0 lvfmin

I pDmax = 1 + Ll / niYlmax omax

1+!5 =l+nMmin~

~D mu = 2( l + _1_) V. n.A1min


(3.18)

(3.19)

(3.20)

(3.21)

(3.22)

54

It is clear that a large turns ratio will reduce the transistor current stress but increase the diode

current stress which would comprise a trade-off in choosing n. This is basically because the tran-

sistor is on the primary side while the diode is on the secondary. Opposite reasoning is true for the

transistor and diode voltage stresses. If we wish to have equal current stresses in both the transistor

and diode, then the necessary turns ratio, n. can be found by solving Eqs. (3.19) and (3.21) which

yields (for Mmin < 1)

n = 2 M <1 • ' m~ (1- !5)(1- Mm;0 ) (3.23)

Figure 3.2a shows the normalized transistor and diode current stresses as a function of n. The ratio

of diode to transistor maximum peak current stress denoted by A. can be shown to be

[ 1 l IpD max n n- Mmin A.=-~--=2 1-<5 1 ' Mm;n< 1

pTmax -+M. n mm

(3.24)

which is plotted in Fig. 3.2b as a function of n.

3.2 Design Procedure for ZVS-QRCs

3.2.1 Design of Resonant Tank Elements

A similar procedure is derived for the family of ZVS-QRCs assuming that the same set of

specifications is provided. From the specifications we have

R V. R =~ min = -1-- • max f omax omln

(3.25)


li'r,o:r

lomax

(a)

(b)

li)

~ C\1

0 0 0

0 lJ)

['

20 •;;,

10%

turns ratio, n

turns ratio, n

Figure 3.2 a) The effect of the transformer turns-ratio on the transistor and diode current stresses in a flyback ZCS-QRC. b)The ratio of peak diode to transistor currents as a function of the turns-ratio.


and

(3.26)

First we determine z. by using the defmition of( •. Thus from Eq. (2.40) we have

(3.27)

Again this impedance will guarantee the lowest possible voltage stresses for the desired load range.

Next the resonant frequency is determined by utilizing the de conversion characteristics of

ZVS-QRCs. From these we can see that the maximum switching frequency l.rnu occurs at light load

(Qpmu) and high line (Mrnin) . Analytical expressions for the characteristics are obtained by using the

dual quasi-resonant function F( ~ ,n) given by

Qp II • -1 Qp Qp M "J M 2 F(-,n)=mr-(-1) sm (-)+-+--(-1) (-) -1 M 1vl 2M QP Qp (3.28)

n = lfor HW mode n = 2 for FW mode

and thus the conversion ratios are given by ( 5]

Buck:

Boost: (3.29)

BuckBoost:

Substituting 1vl = Mrnin , QP = Qpmu (i.e. QMmin =C.) and f.= hmu into Eq. (3.29) and using the pmiX

approximation


we arrive at

F(-1-,n) ~ 21r , error less than 0.2 %

'·

Buck:

Boost:

Using/.= 1 and z. =.If we readily obtain L. and C. as 21rJL.c.

i) Buck ZVS-QRC:

ii) Boost ZVS-QRC:

iii) Buck-Boost ZVS-QRC:

L = (.Rma:x 1 - M min 0 21rJ; ma:x M min

Co= 1 Mmin(l- Mm;n) 27r/. ma:x( vRma:x

1 2

Mmin

C= 1 o 21r/. ma:x(vRma:x

(3.30)

(3.31)

(3.32)

(3.33)

(3.34)

Equations (3.32)-(3.34) provide the resonant tank design for guaranteed lowest voltage stresses on

the devices. These results are valid for all the zero-voltage topological variations [5], namely L, T

and Pi sections.


3.2.2 Evaluation of the Low-Pass Filter Inductor

As opposed to the procedure to determine L1 presented in the previous section for ZCS-QRCs

in this section formulae are derived for L1 assuming topological solutions with an infinite inductor.

The volt-second balance is then applied to the circuit with fmite L1 using solutions from the ideal

circuit. If the ripple in L1 is to be small (a reasonable and desirable assumption), then we fmd this

approach to be quite simpler while still maintaining reasonable accuracy.

First we need to defme the topological modes any ZVS-QRC goes through. We will concen-

trate on the ZVS- Buck Q R C followed by results for the other converters. Let T; , i = 1 ,2,3,4 denote

the duration of the i1" topological mode. These modes are shown in Fig. 3.3a where L1 is considered

as a constant current source (i.e. L1= oo ). Later on this current source will be replaced by an actual

inductor L1 (Fig. 3.3b). The circuit is readily solved [4] and the intervals T; can be written in the

form

Qp woTl = M

n , -1 Qp ro0 T2 = mr- ( -1) sm (M)

M n j M 2 ro,T3 = QP - ( -1) '\) ( QP) -1

ro 0 T4 = w0(T,- T1 - T2 - T3)

n= 1 HWmode n=2 FW mode

(3.35)

where T, = j_ = switching period. Using the sub-circuits of Fig. 3.3a we derive the voltage and Is

current waveforms of L1 present in the circuit of Fig. 3.3b. These waveforms are shown in Fig. 3.3c.

Applying the volt-second balance to L1 we have

(3.36)

or


Co

Lf Vg

Cf R

lo {b)

Co Lo '<.t

Vg~:J I Lo Vo time

. ~ 1j ~ } ---11---T-- T4 ~

lu . . . . ' slope (V~Vo)/(LO+Lf)

\,

{a) (c) ~ time

Figure 3.3 a) The topological modes of an ideal ZVS-QRC. b) The actual ZVS-QRC circuit. c) The voltage and current waveforms of the filter inductor in (b).


tmax

/).fL = /Lmax -/Lmin = + f VL/t) dt r tmin

tmin

= ~1 f VL/t) dt r tmax

(3.37)

We can evaluate either of the integrals in Eq. (3.37), but noting that vL/t) =- v. in the interval

[ tmax• tm;n] , it is simpler to use the second integral. Hence,

(3.38)

In normalized terms,

d!L R [ 11 • -1 QP M 11 J M 2 ] -=-- mr-(-1) SID (-)+--(-1) (-) -1 I. w.L1 M QP QP

(3.39)

or

L, Q [ 11 • -I Qp M 11 J M 2 ] -=-- nn-(-1) SID (-)+--(-1) (-) -1 L. t).Lfl. M Qp Qp

(3.40)

(3.41)

At this point we need to point out that there are two different criteria for calculating L1 ,

a) Find Lfl for a specified maximum absolute ripple, /)./Lmax.

b) Find L12 for a specified maximum percent ripple,

~~L X 100% = ~fmax 0


If criterion (a) is used then the value of L1 obtained cannot guarantee continuous inductor con-

duction mode (CCM) , a condition that may be necessary for some control schemes (e.g. some

forms of current mode control). Criterion (b) however, can be used to guarantee (CCM) by taking

into account the fact that the ripple is a function of the de load current and thus L1 can be calculated

so as to prevent discontinuous conduction mode (DCM).

a) Value of Lfl for D..h max :

Equation (3.41) can be written as

AlL= L~~.[F( ~ ,n)- ! ] =~[(1 -M) 2nf. _ QP ]

Lflw• f. 2A1 (3.42)

= .!i.1 Q [(1-M) 2-rrf. - __g_] L • P r 2M 1 Js

It is apparent that the ripple is largest at the lowest frequency of operation, which from Fig. 2.11

ocurs at low line (Mmax) and full load (Qpmin) . Substituting these values into Eq. (3.42) we get

(3.43)

Defme

(3.44)

(3.45)

Thus the calculated value of Lfl will guarantee a ripple no more than the specified D..I Lmax over the

whole range of operation.

i


b) Value of L12 for a specified ripple ~1 :

Suppose the specifications call for CCM operation for iLJ for the whole range of operation with

a percent ripple not to exceed a specified quantity, ~1 defmed as

(3.46)

Notice that ~1 = fiJL) and thus the condition for maximum ~1 is considerably different than that for

maximum d!L. It is still apparent from Eq. (3.42) that maximum ripple would occur at lower fre-

quency, however at minimum load rather than full load. Again from Fig. 2.11 this condition occurs

at M = Mmax but at QP = Qpmax instead. Inserting these conditions into Eq. (3.42) and manipulating

we get

(3.47)

or

(3.48)

The value of L1 obtained from this equation is guaranteed to satisfy the percent ripple ~1 . If ~1 is

specified to be less than 100 % then, in addition CCM operation is also guaranteed for the whole

range of operation. If the percent ripple at light load is satisfied, then its value at full load will be

lower. The absolute ripple will be higher and can be calculated from Eq. (3.43).

The filter inductor in the Boost and Buck-Boost converters can be found by going through a

similar procedure as in the Buck case. Using the same ripple criteria presented earlier we can reach

the following results.

Boost ZVS-QRC:

a) Value of Lfl for d[Lmax:


Af _ Lo / QP [ 2nfo QP ( l)n . -1( QP )] uL-- - -----nn+ - sm -4 OM Is M M (3.49)

Lfl lomax [li ~( ) ( ln.-1] L = .:l/ a 1v1min.r' a, n -a-nn+ - ) sm oc o L max

(3.50)

b) Value of Lf2 for a specified ripple, ~~:

(3.51)

(3.52)

(3.53)

Buck-Boost ZVS-QRC:

a) Value of Lfl for .:l/Lmax

(3.54)

Lfl fo max M [ ~( ) (J. ] L= I maxa .r,a,n -2 o Ll Lmax

(3.55)

b) Value of Lf2 for a specified ripple, '':

~!max= ( t~/~ )max < 1.0 for CCM (3.56)

(3.57)


(3.58)

3.2.3 Effect of Transformer Turns Ratio on Stresses

Finally, the effect of the transformer turns ratio, n in a flyback (Buck-Boost) ZVS-QRC is

considered. A typical circuit is shown in Fig. 3.4. It is interesting to point out that c. and L. will

absorb the output capacitance (CDs) of the FET and the leakage inductance (L1*) of the transformer nP respectively. The stresses are obtained with n =- as an explicit factor. The characteristic n,

impedance, z. is calculated on the primary side and thus

and QP is calculated on the primary as

z = rz: 0 ~c:

Q R' y = Afmin ~ 1.0 p=-z , "'· Q a pmax

where R' is the reflected value of the load to the primary side. Let M = ~ . g

Starting with Eq. (2.33) we can show that

vpT 1 M -= (n+-)(1 +-)

V. M Qp

The maximum peak voltage stress will occur at full load and we thus obtain

Equation (3.61) has a local minimum ML given by


(3.59)

(3.60)

(3.61)

65

_______ L~k,L~m~--~N-------~--~

VG + CF RL

Figure 3.4 Grcuit diagram of a flyback ZVS-QRC.


(3.62)

and has identical values at both M = Mmin and M = - 1-. Hence two cases arise from Eq. (3.61). lZ C.LlR

Case a) Mmax. > ~ "'•LlR

1 Case b) Mmax. < C.AR

Transistor current stresses:

Diode stresses:

(3.63)

(3.64)

(3.65)

~Dmax. = 1 + __ 1_ V. nMmin

(3.66)

[pDmax. = 2(1 + nM . ~) lomax. mm 1- <)

(3.67)

It is clear that a large turns-ratio, n, will increase the transistor voltage stress and decrease the

diode voltage stress and vice versa. The transistor voltage stress should be given priority over the

diode voltage stress since it can become extremely high due to the effects of line and load variations.

The proper design approach would be to make n as small as possible as· the application (step-up

or step-down) will permit. From Eq. (3.67) it is also clear that smaller n will reduce the diode cur-

rent stress. Fig. 3.5a shows the normalized maximum peak transistor and diode voltage stress as a


(a)

0 Vpr ...... vP_" 0 Peak Transistor Voltage 0 Peak Diode Voltage 0 v. ~ v. ~ 0

8 0 Ill II! I' I'

0 ~ 0 0 ~ Ill Ill

0 ~ 0 Ill II! (\1 (\1

8 8 9:J.oo 2.50 5.00 7.50 10 9:J.oo 2.50 5.00 7.50 10.00

Load range, ~R turns ratio, n

v 0 ..t. = Tran'iittCII' 0 v Diode

0 ~ lJ) I'

0 ~

(b) 0 lJ)

0 ~ lJ) (\1

8 9:J.oo 2.50 5.00 7.50 10.00

turns ratio, n

Figure 3.5 a) Effect of transformer turns-ratio on the transistor and diode voltage stresses. b) The ratio of transistor to diode peak voltage stresses as a function of the turns-ratio.


function of n. The ratio of maximum peak transistor to diode voltage, ..t. can be shown to be given 1 by (Mmax>~)

'>v R

(3.68)

which is plotted in Fig. 3.5b as a function of n.

3.3 Conclusions

The main aspects of the design procedure of quasi-resonant converters is the design of the

resonant tank and the low-pass fllter inductor. The transformer turns-ratio in the flyback converter

is also another design parameter. The design of the resonant tank is shown to be very critical in

terms of stresses. It is found that minimal stresses can be achieved only by proper selection of the

tank characteristic impedance. The specific guidelines for both ZCS-QRCs and ZVS-QRCs are

presented and are shown to be quite simple. It is shown that a trade-off exists between current and

voltage stresses and the transformer turns-ratio since increasing voltage stress will result in decreas-

ing current stress. A turns-ratio can be found that results in reasonable current and voltage stress.

The load range of a ZVS-QRC is shown to be a restrictive factor since a design for a wide load

range will result in excessively high voltage stresses if zero-voltage-switching is to be achieved for

the whole load range. The design approach should consider the limitation of the characteristic

impedance to some maximum value to avoid very high voltage peaks, while considering the possi-

bility of operating light loads with non-zero-voltage-switching to an acceptable limit. The load

range factor, ~R , is recognized as one of the most important considerations in designing

ZVS-QRCs. It is apparent that this class of converters is not suitable for applications with wide

load variation requirements. On the other hand, ZVS-QRCs are a very good choice for applications

;


that do not have very large load variations. In this case the peak voltages are no longer a major

problem.


Chapter 4

Analysis of Loss Mechanisms in PWM, ZCS and

ZVS Converters

4.1 Introduction

Various forms of power dissipation and losses exist in any converter topology. The causes and

sources of power dissipation are enumerous and cover a wide range of mechanisms that involve

semiconductor switching, magnetic losses and losses in passive components. The main objective

of this analysis is to provide analytical expressions that would provide estimates for the power loss

in QRCs and PWM converters. This analysis parallels the previous stress analysis providing an

another design tool that would help in estimating the major losses for a given design. A basis for

comparing losses in various converters is established by normalizing these expressions by utilizing

the concept of the design constraint, ( as illustrated in the case of the stress analysis. Other nor-

malized parameters would be subsequently defmed and a broad comparison of the merits and de-

merits of different converters could be more easiy viewed. Theoretical normalized effeciency figures

Analysis of Loss Mechanisms in PWM, ZCS and ZVS Converters 71

corresponding to various losses can be derived and compared for different topologies without hav-

ing to deal with specific numerical designs.

The approach adopted in this analysis is to use the ideal solutions of the circuit (with no losses)

to obtain extensions to the dissipative cases. Since minimizing the losses is always a prime concern

and every effort is made to use the most efficient components, this approach is reasonable for

practical purposes. The following loss mechanisms will be specifically dealt with; the conduction

loss in the MOSFET, the switching loss in the MOSFET and the freewheeling diode conduction

and tum-off losses. For PWM converters MOSFET parasitic impedance losses are accounted for

whereas for QRCs losses due to equivalent series resistance (esr) of the tank elements are included.

Computer simulation is used to to verify the validaty of the obtained expressions by computing the

power losses in representative circuits. Two experimental circuits were designed and built for ex-

perimental verification of the analytical results.

Section 2 deals with the losses cited for the PWM converter, while section 3 deals with losses

in ZCS-QRCs and section 4 for ZVS-QRCs. In section 5 the normalized results are compared to

provide some insight into the crucial loss mechanisms of each topology.


4.2 Loss Analysis in PfVM Converters

The mechanisms analyzed in PWM converetrs are the MOSFET conduction losses, switching

losses, the loss associated with the parasitic capacitance and inductance of the MOSFET and its

leads. Finally the conduction loss in the freewheeling diode is obtained.

Figure 4.1 shows the basic circuits of the PWM topologies with the MOSFET parasistics in-

eluded. In analyzing various loss mechanisms, each one is analyzed separately while setting the

others to zero. Thus every circuit component is idealized except for those affecting the loss mech-

anism under investigation. Finally these individual losses are summed to give the total loss.

4.2.1 MOSFET Conduction Losses in PWM Converters

In all PWM converters, the MOSFET carries the charging current of the f11ter inductor, L1

during the on-period, DT, . Figure 4.2 shows the MOSFET current in any PWM converter. The

following analysis is performed for Buck converters followed by Boost and Buck-Boost cases.

The current waveform is obtained assuming an ideal switch and a fmite value of f11ter

inductance, L1 . Using the design constraint of a PWM converter,(. and defming the on-time slope

y as

y=

and

/min = Jo( 1 - (.)


Lf

Vg R

Lf {a)

R

{b) Cds

Vg

Lf R

{c) Figure 4.1 Basic PWM topologies; a) Buck b) Boost c) Buck-Boost. Parasitic Elements are also shown.


I max

---{- -- --- ----lm1n

" DTs DTs time

Figure 4.211le MOSFET current waveform in a PWM converter.


then we may readily obtain the r.m.s. value of the current through the MOSFET and eventually

the conduction loss, Pcand ,

2 pcond = Irms rDS(on)

where rvs(an) is the on-state resistance of the MOSFET and

DTs 2 1 r 2

frms = T J. (/min+ yt) dt s 0

(4.1)

This integral can be evaluated in a normalized form by utilizing the normalized time constant of the

circuit T , where

RT, •=--= , L, (4.2)

and hence it is possible to reach an expression of the form

2

!,~, = f{M, Cc) /0

Performing the actual integration and normalization process it can be shown that:

2

/,~, = M( 1 + -tc~) /0

(4.3)

The conduction loss is thus

for which we can calculate the normalized conduction loss, Pc

P pcond M( 1 _l_y2) c =-p = Pvs +3"'c out

(4.4)


where P~s =normalized MOSFET resistance. The maximum conduction loss will occur at full

load (Rmin) and low line (Mmax) and hence

(4.5a)

Notice that this loss is reduced as (.is reduced. Hence the minimization of the design constraint

will, in addition to reducing the stress, reduce the switch conduction loss. A similar derivation can

be followed to obtain the corressponding results for the Boost and Buck-Boost converters.

- PWM Boost Converters

- PWM Buck-Boost Converters

1 2 P. = PvsM(M -1)(1 + J'•)

1 2 P. = PvsM(M +1)(1 + J'•)

with the maximum losses ocurring at full load and low line Mmax.

4.2.2 MOSFET Switching Loss in PWM Converters

(4.5b)

(4.5c)

Switching losses arise in PWM converters because of the nonzero switching times o[s.witching

transistors. The transistor is thus forced to experience overlaps of high level simultaneous voltages

and currents every time it is switched on or off. This corresponds to a switching trajectory shown

in Fig. 4.3a. The trajectory travels through a high loss region when switching between points (a)

and (b). A fixed amount of energy is lost in the switch every time a transition is made and hence

the power loss will increase linearly with frequency. This increase in loss will impose a limit on the

maximum frequency of operation of the converter while maintaining high efficiency and was one

of the main motivations for introducing zero-current and zero-voltage switching techniques. Fig.


(a)

(b)

I

-------, SOA '

" " " I I nroMnt I

OFF

Vds

Figure 4.3 a) Switching trajectory of a PWM switch. The switch travels through a high loss region. b) Switching waveforms of the transistor.


4.3b shows the switching waveforms in a Buck PWM converter. No ringing is shown since the as-

sociated loss is accounted for by the parasitic inductances and capacitances in the circuit. For

purposes of mathematical computation all rising and falling waveforms are asssumed to be linear.

Notice that because the switch is effectively loaded by a current source (the fllter inductor), then

when it is turned off the current remains approximately constant while the drain to source voltage

rises. The inductor current must continue to flow until Vvs is high enough to turn on the free-

wheeling diode, after which the FET current starts to to drop. This total transitional period is Toft

. A similar reasoning can be applied in order to explain the transitional waveforms during Ton .

The power loss due to the switching of the MOSFET, P,w can be calculated using the following

assumptions:

During turn-off:

During turn -on:

. I t lvs= minr on

where T' ott+ T" ott= Tott and T' on + T" on = Ton .

Hence,

Using Eqs. (4.6) to evaluate this integral we arrive at

Analysis of Loss Mechanisms in PWM, ZCS and ZVS Converters

(4.6a)

(4.6b)

(4.7)

79

Introducing the design constraint, 'c = !1!/2 and using 10

/max= fo(l +C)

/min = fo(l -'c)

we may obtain the normalized switching loss P, = ~, ... Thus, out

(4.8)

where ()off= 211:/sToff= normalized turn-off angle of the MOSFET in radians and ()on= 211:/sTon = normalized turn-on angle. This loss is seen to increase at high line (Mmin) and hence,

(4.9a)

As frequency increases both ()on and ()off increase linearly and accordingly the switching loss will in-

crease in a linear fashion.

A similar deivation can be performed for the Boost and Buck-Boost converters and results

follow.

-Boost PWM converter:

(4.9b)

-Buck-Boost PWM converter:

Assume a transformer turns ratio of n and M = ~ g

Two cases exist depending on the relative position of (Mmax) with respect to Mx = Ml. , (i.e. mm

whether Mmax is at point (a) or (b) in Fig. 4.4).

(4.9c)


(I+ M)(l + ~)

w~--------~--------~--------~---------, N

0 N

0

lJ)

(a) (b)

Figure 4.4 The function (1/n + M)(n + 1/M) for determining the maximum power loss in a Buck-Boost PWM converter.


Effect of Non-Zero Parasitic Inductance on Switching Loss

Notice that this switching loss has been evaluated assuming that the parasitic lead inductance,

LP was zero. If LP is incorporated then the loss at tum-on would be modified to

tum-on loss = !sV:T"on 24Lp

and the total switching loss would become

p fsV, [l T V,T"on] sw = -2- max off+ 12LP (4.10)

where T" on is the rise time of the current in LP • (This switching time and other switching times

are discussed in more detail in chapter 5.)

4.2.3 MOSFET Parasitic Impedance Loss

MOSFET Output Capacitance Loss

The circuit diagram of Fig. 4.5 shows the different parasitic elements that contribute to

switching losses at tum-on and tum-off in a PWM converter. When the MOSFET is off, the

voltage across it it essentially equal to the input voltage (buck) and hence the output capacitance

Cns is charged up to Vg and thus it has certian amount of energy stored in it. Every time the

MOSFET is turned on this energy is released from Cvs into the switch and is dissipated as heat. In

order to flnd the corressponding power loss we have

Vg

E = i Cns(v) v dv (4.11)

where Cns(v) is the non-linear output capacitance of the MOSFET given by [12]


Lf

Vg R

Figure 4.5 Circuit diagram of a PWM converter with parasitics accounting for losses at turn-on and turn-off.


where

Cvso =zero voltage capacitance

Cvs(v) = Cvso (1 + Vvs/

4>

4> = junction potential, ~ 1 volt for Si.

n = exponent between j and ;

Assuming n = ; and performong the integration of Eq. (4.11) we obtain

Ifvvs > > 1 volt (i.e. the supply is much larger than 4> ), we may approximate Eq. (4.11) by

(4.12)

where Cso is the ouwut capacitance at Vvs =~'and Eq. (4.12) may be simplified to the form

The power loss incurred would be

(4.13)

Noting that maximum dissipation will occur at high line Mmtn and normalizing we obtain

P P'cvs 2 CDS max = -p-- = --2 - Tvs

out 3Mmln (4.14)


where <vs is the normalized time constant, CsoRmax Ts

- B()ost Converter

For a Boost converter P'cvs can be found to be for (V. > > cf>)

-Buck-Boost Converter

2 Pcvsmax = 3'vs

2 1 2 Pcvsmax=-3 (1 +~) <vs Jvlmm

MOSFET Parasitic Lead Inductance

(4.15)

(4.16)

When the MOSFET is turned off the current in LP cannot collapse instantaneously, and the

energy stored in LP will be dissipated. The amount of energy stored in LP is given by

Ts

E = i Lp(z) i di (4.17)

Assuming LP is a linear inductor then the power loss is found to be

(4.18)

Deftning the characteristic impedance, ZP and the resonant frequency, wP of the parasitic resonant

tank (LP , Cvs) as

then we have

Z= f4 p -J c;;;

w= I P JLpCvs

p P' LP 1 f. LPmax=p--=2 2 .rzP

out TCj p


(4.19)

85

z where zP = normalized impedance of the parasitic tank = _P_

Rmin

4.2.4 Freewheeling Diode Losses in P\VM Converters

The freewheeling diode in any DC-DC converter contributes a major portion of the overall

losses. the two main loss mechanisms include conduction loss and tum-off ( reverse recovery ) loss.

Conduction Loss of the Diode

The conduction loss, P' Dcond in any diode can be generally expressed as

where lva•g and Vvon are the average forward current and voltage of the diode respectively. lv_.8 can

be shown to be given by

-Buck PWM

-Boost PWM

- Buck-Boost

Which are valid for any value of( •. Hence this power loss will always depend the magnitude of

the load current and not the circuit design. The normalized loss is thus :

-Buck PWM


p P' Dcond = V ( 1 _ M . ) Dcond max = p DN rom

out (4.20a)

-Boost PWM

(4.20b)

-Buck-Boost PWM

(4.20c)

v where VDN = ;on = normalized forward voltage of the diode.

0

Reverse Recovery (Turn-off) Loss of the Diode

Whenever a conducting diode is turned off, reverse current flows momentarily under the in-

fluence of the reverse voltage until all electron-hole pairs in the junction have recombined. The

power loss incurred in this process can be readily found from

Ts

P' Dm = + i V,.. iDRR(t) dt s 0 (4.21)

= f.V, •• QRR

where V,.. is the reverse volatge applied to the diode and QRR is the reverse charge recovered from

the junction.

- Buck Converter:

- Boost Converter:

P' -~ QRR Dm- M T s

Pt v QRR Dr••= oT

s


(4.22a)

(4.22b)

87

- Buck-Boost Converter:

• aliz d fi p P' Dre• or m norm e orm, Dr•• = -p--out

P' Dre• = V.(l + ~ ) ~R s

Buck: PD,..max=~qRR lYl min

Boost: PDrevmax = qRR

Buck-Boost: PDre•max = (1 + Ml. )qRR mm

where qRR is the normalized reverse recovery charge = QRR TJomin

(4.22c)

(4.23)

The semiconductor losses accounted for in PWM converters may be added up to provide an

estimate for semiconductor efficiency and hence

where P,.m = p;•m is the normalized semiconductor loss. Thus an efficiency figure , l1som 0

corressponding to these losses can be found.

P. .. - __ ...;;....._ = ----"---"ISem - p P' 1 p

o+ sem + sem (4.24)


4.3 Loss Analysis in ZCS-QRCs

The loss mechanisms in ZCS-QRCs include the conduction and the tum-on losses in the

MOSFET ( tum-off is at zero current and thus tum-off loss is eliminated ). As for the freewheeling

diode, conduction and reverse recovery losses are obtained. The resonant elements introduced to

achieve the zero-current switching property contribute to the losses by their esr's.

4.3.1 MOSFET Conduction Losses in ZCS-QRCs

Figure 4.6 shows the essential switch waveform for any full-wave (FW) ZCS-QRC. In case

of half-wave (HW) operation the current is not allowed to reverse. The time function of this current

is shown to be [4]

These time functions can be normalized to obtain

(4.25)

and the mode intervals T1 = t1 , T2 = t2 - t1 are given by


VIs -lr-------.

Transistor current

Transistor voltage

Figure 4.6 The various waveforms of the ZCS-QRC. Top to bottom: Gate drive, switch current and switch voltage.


n = 1 for HW mode and 2 for FW mode. Having defmed the switch current in a normalized form

we now fmd the conduction loss, Pcond in the MOSFET. This can be generally found from

2 pcond = f DSrmsr DS(on) (4.26)

where lnsrms is the rms current through the MOSFET given by

(4.27)

This integral can be evaluated using Eq. (4.25) in its norrnlaized form. Equation (4.27) can be

shown to be

(4.27a)

If we incorporate the analytic expressions of the de conversion characteristics ( Eq. 3.56) we arrive

at

- Buck ZCS-QRC

(4.28a)

- Boost ZCS-QRC

2

lns;ms = M(M- l)Gzc( MQ ,n) ~ p

(4.28b)

- Buck-Boost ZCS-QRC:

2

lns;ms = M(M + l)Gzc( ~ ,n) ~ p

(4.28c)

where G2 c is given by


G2 c( 1Q11 ,n) = 1 + ~! x P F( QP ,n)

[ Q: n • -1M QP M ( -1)n ~P 2 ] - 2 [mr-(-1) sm -]+----- (-) -1 2M Qp M 6Qp 2 M

(4.29)

Since maximum conduction loss will occur at full load, Eq. ( 4.29) is evaluated at QP min • If we de-

fi Qpmin me QC =~we get

(4.30)

Effect of Line Variations

The maximum rms current is a function of M and may occur at high or low lines. In order to

investigate the effect of line variation on rms current we use the defmitions of line variation

M max = 1...±i_ = L\ = line range Mmin 1- b

along with the ZCS design constraint, (c .

a) Full-wave operation

1- Low line operation, M = Mmax:

S. y QP min 1 0 h mce '>c=--~ . t en, lVfmax

G { 1 2) 1 + 91t' +lO "'1.5 ZC\yc' = .. 18()'( + 1)

and thus


(4.31)

(4.32)

92

2- High line operation, M = Mmin : _

Since a= ~~min = 'c~g~~8 , then by using the approximations sin- 1 1/~8~1/~8 and)~; -1 ~~8 ivlmin

we have

(4.33)

which gives a relative error of 0.1 % ( at ~8 = 2 ) compared with the exact relation of Eq. ( 4.30).

Since ~8 > 1 then Eq. ( 4.33) always has a value larger than 1.5, and comparing with the low line

case (Eq. 4.31) we reach the conclusion that G2c(l/~8,2) is maximized at high line. Hence we may

make the following conclusions about the rms current.

- Buck ZCS-QRC

which clearly shows that the rms current is higher at high line, i.e.

( ~~:= )-= (I + <\!2)M.,, FW-Buck ZCS-QRC (4.34)

- Boost ZCS-QRC

from which we can clearly see that the maximum rms current occurs at low line (Mm.J . Hence,

( l;t )-= l.SM.u(Mmu -I) FW-Boost ZCS-QRC (4.35)

-Buck-Boost ZCS-QRC


at low line

at high line

which also shows that the maximum rms current occurs at low line (Mm.J· Hence,

( /~;:., ).u ~ !.SM.uCMmu +I) FW-Buck-Boost ZCS-QRC (4.36)

Notice that FW, low line operation is associated with more reverse current being returned to the

source.

b) Half Wave Operation

1- Low line operation, M = Mmax:

From Eq. (4.31) we can see that G2 c(1/Cc) has identical values for n = 1 or 2 . Hence we still

have

2- High line operation, M = Mmin:

27n + 28 Gzc0/Cc,1) = 18n + 18 = 1.5

In this case we evaluate Eq. ( 4.30) with n = 1 and M = Mmin or oc = .1.8 • Using similar approx-

imations for the FW case we have

(4.37)

Notice that with dg = 1, G2c(1,1) = 1.69 and thus Gzc is higher at Mmin than at Mmax. We can thus

fmd the maximum values of the rms currents as follows.

- Buck ZCS-QRC:


rrns current at low line rrns current at high line

... "' .,

8 ID

"'

--~ 8

~

f.,.. v v f:__ l---~

/'

/

vv v v

---l---l--"' l---

0 1.00 1.63 2.25 2.88 3.50 •.13 •• 75 5.38

ll,J( = 1.25 6.

8 ~t----i-----t----+-----~---+----~~~+---~

8

00

1.63 2.25 :z.ea 3.50 •. 13 •.75 5.38 6.00

Figure 4.7 The rms current vs. line range, ag at low and high lines for half wave ZCS-QRCs; a) Buck b) Buck-Boost


/ DSrms -~-2-=

0

(4.38)

which is plotted in Fig. 4.7a. We can see that the two expressions intersect at ~8x , which can be

found by equating both expressions to be

Notice that ~8 = 1.25 corresponds to a percent line variation of 11.1 % and thus for situations

with c5 larger than 11 % the maximwn rms current will be at low line ( which is a more practical

situation ) and thus we have

DSrms (/ ) T max= 1.5Mmax , c5 > 10% HW-Buck ZCS-QRC (4.39)

- Boost ZCS-QRC:

It is clear that the rms current is always higher at low line and hence

(4.40)

- Buck-Boost ZCS-QRC:

At low line


and at high line,

which is plotted in Fig. 4.7b for various values of Mmin • It is clear that the rms current is higher

at low line for values of ~g above 1.1 ( about 5 % line variation ). Below 5 % line variation the

values at high and low lines are very close to each other. We can thus conclude that

( I;t )-- !.SM.uCM- + l) HW-Buck-Boost ZCS-QRC (4.41)

Notice that for the Boost and Buck-Boost cases, the maximum rms current occurs at low line

(FW and HW) because the resonant current in these cases is determined primarily by the input

current which is always higher at low line. However for the Buck case, the resonant current is de-

termined by the output current, but the efficiency usually deteriorates at low line due to increased

input current. The rms current for a flyback converter may be obtained directly form Eq. (4.41)

by reflecting the v. to the primary.

Maximum Conduction Loss

Now that the maximum rms currents have been obtained, it is possible to compute the maxi-

mum conduction loss as

l r p = pcond DSrrrzs DS(on)

c Poutmax = -~-2- Rmin 0

and the corressponding power losses are found

- Buck:


-Boost:

- Buck-Boost:

rDSon where PDs =-R .

max min

1.5MmaxPDs HW P _ max c- 2

( 1 + ~g/2)M minP DSmax FW

4.3.2 MOSFET Switching Losses in ZCS-QRCs

(4.42a)

(4.42b)

(4.42c)

Switching losses generally comprise turn-on and tum-off losses. Since a ZCS-QRC is designed

to turn-off at zero-current, the turn-off losses are eliminated (or substantially reduced for a practical

circuit). In other words

p turn-off= 0

The ZCS technique however fails to eliminate the turn-on loss. Figure 4.8a shows the equivalent

circuit of the MOSFET at turn-on in a ZCS circuit. Two loss mechanisms occur at turn-on and

will be accounted for separately. The first is the loss associated with the discharge of the drain-to-

source capacitance CDs, and the current circulating from the gate to to the drain through CoD. The

second mechanism is due to the finite rise time of the current through the resonant inductor L.

which overlaps with the drain-to-source voltage.

a) Capacitive Discharge Losses at Turn-on


Vds Cds

Ids IL

LP+LO Vg l

{a)

Ton

{b)

Figure 4.8 The equivalent circuit of the switch in a ZCS-QRC at turn-on. b) The corresponding waveforms.


The collapsing drain-to-source voltage is of a linear nature due to the charging of the drain-

to-gate capacitance from the gate drive with a constant current. If the voltage completes its fall in

a time Ton ( Fig. 4.8b ) then we may write,

t Vvs(t) = Vx(l- -) Ton

Assuming Cvs and CGD are linear capacitors we have

The channel current ic~, 1 , due to these two currents is thus,

ichl = (Cvs + CGD) ;• on

This current flows against a collapsing voltage VDs(t) and hence the power dissipation is

Ts

P1 = + i Vvs(t)ichl(t) dt s 0

Ts

= +i v.(l - ; )(Cvs + CGD) ;· dt s 0 on on

(4.43)

(4.44)

(4.44)

(4.46)

(4.47)

which is the source power dissipation due to the dissipation of energy stored in CDs and the gate

dissipation due to supplying CGD with energy. If Cvs and CGD were non-linear capacitors then by

virtue of the integration of Eq. ( 4.10)


(4.48)

where Cvs and CGD are evaluated at Vx . 0 0

b) Losses Due to the Current Rise in the Resonant Inductor

The presence of L 0 in series with the MOSFET is beneficial at tum-on since it forces the cur-

rent to rise slower and hence less voltage-current overlap is encountered. In order to determine this

loss, the terminal current of the device (or the current in L0 ) is derived under the same circuit con-

ditions shown in Fig. 4.8. Also notice that the terminal current of the FET, ivs(t) is that current

in Lo , whereas the capacitive currents are all internal to the FET. Since Vvs( t) collapses linearly then

A_iL (t) =A_ ivs(t) = - 1-(V -Vvs(t)) dt 0 dt Lo X (4.49)

from which

2 . () Vxt lvs t = 2L T

o on (4.50)

Notice that the linear charging region of Lo is preceeded by a short parabolic rise of ivs(t) and can

be quite small at lower frequencies. The power dissipated due to this current-voltage product is

given by

(4.51)

where eon = w o Ton = normalized rise time in radians.

The total switching loss, P,w can now be evaluated as


2

~ h ( 2 w c + eon ) watts = x 2nf. 3 ° DSO 24Z0

(4.52)

In order to investigate the effect of line and load variation on P,.,. we will consider the quantity

K = V: ~r since the rest of Eq. (4.52) is constant for a given design. 2n1 •

- Buck ZCS-QRC:

Buck ZCS-QRC

It is clear that K is maximized at the highest operating frequencies (i.e. at full load). However, it is

necessary to determine the condition at which it is higher:

i) High line, full load or,

ii) Low line, full load

For the FW case it is immediately evident that K is higher at high line since

K~~ 2nM

FW

For the HW case we must consider cases (i) and (ii) separately as follows:

KH = ---~-::-,• :---~ V: High Line M . R( Mmin 1) Mmin(n +2.6-g)

Thus,

mm Q . ' pmm


Low Line

102

We thus conclude that K is always higher at high line for the Buck converter. Hence,

pswmax = V: (]_woCDs + -0-~n-) M . Fi( Mmin ) 3 o 24Z.

mm Q . ,n pmm

The normalized switching loss, P, = P,w/Poutmax is found using Qpmin = Rmin = C)vlmax z. 2

p ,..., 1 (]_ + !!on y ~;( \ smax- Fl\1min 3 w;r 24"'c'"maxJ

where F= 2n for FW mode and (n +2.1g) for HW mode and'= RminCns0 •

-Boost ZCS-QRC:

Boost ZCS-QRC

(4.53)

It is clear that K is a maximum at maximum switching frequency (at Qpmin and Mmax), which cor-

responds to full load and low line. Making use of F(1fCc,n) ~ 2n we have for both FW and HW

(4.54)

-Buck-Boost ZCS-QRC:

K = (V. + V/___f__ = V: (1 + 1/M) 2nfo F( ~ ,n)

(4.55)

K is maximized at higher switching frequencies (i.e. at full load). The effect of M is yet to be de-

termined as in the Buck case. For a FW converter F( ~) ~ 2n and K is highest at high line

(Mmin)· For the HW case we have


and

Low Line

Thus,

Hence the maximum switching frequency can be considered to occur at high line. (This is not a

general statement, but it is true for practical values of ~8 and Mmax , since for very large values of

~8 and Mmax, the ratio KHIKL becomes less than 1.0 and eventually reduces to zero.) In other words,

Hence,

2

Psmax ~ ~ (1 + Ml )(; w;r + ~~ '.Mmax) mm

(4.56)

where,

{2tr FW

F-tr +2~8 HW

and for


1.0 ::; Llg ::; oo step-down 1.0::; Llg::; 3.2 step-up

The upper limit on Llg can be obtained by assuming a step-up operation (Mmin ~ 1.0) and equating

KHfKL to 1.0 and setting Mmin to 1.0. For a step-up converter with Llg > 3.2, the maximum switching

loss will occur at low line rather than at high line. The specific circuit at hand can be always ana-

lyzed using the general formula of Eq. (4.52).

Switching and Capacitive Discharge Loss Factors

Finally, we can introduce the switching and capacitive discharge loss factors, K{;.,cs and K~fs

respectively to facilitate the comparison with other converters.

i) Switching Loss:

02 The factor 24 'Nmax can be expressed as

11:2 2[ f. ]2 M zcs 'c(; ktr r-- Mmax = F(-Q . ,n)Ksw Jsmax p mtn

(4.57)

where k1, is the normalized turn-on time given by

k -[~] tr- Tsmin

(4.58)

and the ratio !./!.max is defmed in Eq. (3.6). Hence we can summarize the switching losses as

a) Buck ZCS-QRC:

(4.59a)

b) Boost ZCS-QRC


c) Buck-Boost ZCS-QRC

ii) Capacitive Discharge Loss

1 zcs psmax ~ (1-u-) Ksw (Mm.J

iVlmax

1 zcs psmax ~ (1 + u-) Ksw (Mmin)

ivlmin

The quantity ~ w o-r can be used to defme the ZCS capacitive loss factor as follows

2 zcs M 3WoT =Kens F(-Q . ,n)

pmm

and the losses would become

1 zcs Buck: p CDS= M Kens at j1,1 = M min

1 zcs Boost: Pens= (1 ""'"'M)Kcns at M = Mmax

1 zcs Buck-Boost: Pens = ( 1 + M)Kcns at M = M min

4.3.3 Freewheeling Diode Losses in ZCS-Q RCs

(4.59b)

(4.59c)

(4.60)

(4.61)

The freewheeling diode has coduction losses due to the fmite forward voltage drop. Figure 4.9

shows the current waveform through the freewheeling diode of a ZCS-QRC. The current level, lx

is as defmed previously. The average value of this waveform is readily obtained as

Ts

[Davg =+I in(t) dt s 0


Ts time

mode Intervals T1 T2 T3 T4

Figure 4.9 The current waveform in the freewheeling diode of any ZCS-QRC.


JDavg 1 [ Tl J - 1-=T 2+T,-T1 -T2 -T3 X S

= 1 - fs[ ~~ + T2 + T3]

= 1-_.L_F(M n) 2n:fo Qp'

Using Eq. (3.56) to eliminate fs we have:

a) Buck ZCS-QRC

and hence,

JDavg = (l _ M) I.

b) Boost and Buck-Boost ZCS-QRCs

JDavg - 1 - = 1 ' PDcond= VDN

D

(4.62)

(4.63)

(4.64)

These results are identical to the PWM case and could be obtained immediately since the average

current in the diode is always directly related to the average output current.

4.3.4 Losses in the Resonant Tank

Resonant Inductor Loss

In all ZCS-QRCs, the resonant inductor is always situated in series with the transistor switch.

Thus it carries the same current and the loss within L. is simply,


(4.65)

where RL is the esr of Lo and IDs is the rms drain-to-source current given by Eq. (4.28). Maxi" o rms

mum loss occurs at the same conditions cited for the transistor conduction loss and thus Eq. (4.42)

holds with p DS replaced by p L = RL I Rmin = normalized esr of the resonant inductor. max omax o

Resonant Capacitor Loss

The current through Co is shown in Fig.4.10 and is given by

(4.66)

Obtaining the mean of the sqaure of ic (t) we arrive at 0

(4.67)

Maximum loss will occuer at full load and maximum frequency and the normalized maximum

power loss is ( P c = P' c I Poutmax ) 0 0

Buck: Pc = Pc MH2 c( QM ,n) o omax . p mm

M Boost: Pc = Pc M(M -1)H2c(-Q ,n) o omax . pmm

(4.68)

M Buck-Boost: Pc = Pc M(M + l)H2 c(-Q--,n) o omax . pmon

with p c = Rc I Rmin and omax o

2 M M Qp n • -tM

H2 c(-Q ,n)F(-Q ,n) =--2 [n1r- ( -1) sm -Q] P P 2M P nn;: +~-1.::!2_ Qp -1

M 2 M2

(4.69)


~~ 0

0

Figure 4.10 Current waveform in the resonant capacitor of a ZCS-QRC.


Notice that the complicated form of H2 c can be simplified by the following approximations.

1- Full-Wave case, n = 2:

2- Half-Wave case, n = 1:


4.4 Loss Analysis in ZVS-QRCs

Loss mechanisms in ZVS-QRCs include the conduction loss of the switch, its inherent turn-off

loss. losses in the rectifying diode, and losses in the resonant tank. The switch is designed to tum-on

at zero-voltage therby eliminating losses associated with Cvs. A ljmiting tum-off loss is encountered

due to the fmite fall time of the channel current resulting in a voltage-current overlap. This loss

factor is shown to be of more pronounced effect at higher frequencies of operation.

4.4.1 Transistor Conduction Losses

The transistor (PET) current in a ZVS-QRC is shown in Fig. 4.11 The waveforms for the HW

and FW cases are substantially different and will be treated separatly.

During the interval T', the reverse diode conducts reverse current and this time can be found

as follows.

The normalized time modes of a ZVS-QRC can be shown to be given by

(4.70)

The time function of the current in HW mode is

setting ivs(t) = 0 we get


Ids lx

tO

Ids lx -

tO

t2 I I -'

I ,' t I I t I I

~· T 13-T

(a) Half Wave mode

t3

t2 t3 (b) Full Wave mode

Ts

Figure 4.11 MOSFET current in ZVS-QRCs, (a) Half-wave mode (b) Full-wave mode.


and hence,

It can be shown that the rms current is given by

Half-Wave Mode:

(4.7la)

Full-Wave Mode:

(4.71b)

We may thus obtain the nornalized rms drain-to-source current by using the analytic expressions

of the switching frequency given by Eq. (3.66) which yields

Half-Wave Mode:

I HW 2 M + (1-M)Gzv

I DSrms HW --2 - = M[(M- 1) +Gzv]

I. HW (M + l)(M + Gzv)

(4.72)

Full-Wave Mode:

Analysis of Loss Mechanisms in PWM, ZCS and ZVS Converters ll4

I FW -2 1 - ( 1 - M)Gzv

fvs ~ = M(M c- o;;)

I. FW (M + 1)(M + 1- Gzv)

(4.73)

where

(4.74)

and

• -1 Qp Qp Q 27r-Sill -+-

G FW( p)- M M zv--M F(~ ,2)

(4.75)

The maximum conduction loss occurs at full load and low line since the switch is turned on

for a longer period of time (constant off-time). The maximum normalized conduction loss

PC= pcondfPoutmax is obtained by evaluating the factor Gzv( ~min) • max

HW Mode:

(4.76)

FW Mode:

(4.77)

These approximations are obatained by making use of the fact that


Notice that from Eqs. (4.72) and (4.73), with Gflf being larger than G¥,:', losses for the HW mode

are higher than those for the FW mode. In fact, with approximations we can see that the losses in

a FW ZVS-QRC are the same as those in a PWM converter.

The normalized power losses are thus,

HW Mode:

FW Mode:

HW Boost: P. = Pns [Mmax{(Mmax -1) + Gzv }] max

HW Buck-Boost: P. = Pns (Mmax +l)(Mmax + Gzv) max

Buck: P. ~ P DSmaxM max Boost: P, ~ p DSmaxM max(M max -1)

Buck-Boost: P. ~ p DSmaxMmax(Mmax + 1)

(4.78)

(4.79)

Notice that this equation is identical to the conduction loss derived for a PWM converter, (Eq. 2.8).

4.4.2 MOSFET Switching Losses in ZVS-QRCs

The ZVS-QRC is designed such that the drain-to-source voltage resonates back to zero so that

at the turn-on instant no energy is stored in Cns (zero-voltage-switching). Thus the turn-on loss

of the FET is eliminated. However, at tum-off the current in the MOSFET channel is diverted into

the resonant capacitor in a fmite time and it is this time that causes a current-voltage overlap in the

device giving rise to a certain power loss. This situation is depicted in Fig. 4.12. This tum-off time,


Cds lcds

IL

LO+Lp

j {a)

lx

Toft

{b)

Figure 4.12 a) Equivalent circuit of the switch at turn-off in a ZVS-QRC. b) Corresponding waveforms in the MOSFET.


Toft, is primarily determined by the gate time constant, -ras = Rcas and is discussed in more detail

in chapter 5. The channel current is essentially linear in this period and is expressed as

(4.80)

If c. is > > Can (i.e. i, > > ia) then Vns(t) in the interval [0, Torr] can be obtained by using

(4.81)

By solving Eq. (4.81) we obtain

2

( ) . fxt Vns t ~ 2C T

o off (4.82)

The switching loss P,,. due to the overlap of ich and Vns is obtained by evaluating the integral

which yields

(4.83)

The switching power loss depends directly on the speed of the gate drive (T.rr) and the operating

frequency, W 0 •

Note that for fast gate drives (with Torr in the order of 10 ns or less) such a switching loss would

be of more significance at higher switching frequencies (e.g. 10 MHz. or above).

Finally the switching loss is normalized using


a) Buck ZVS-QRC

Psw _ p _ h rr 2 (.AR ( /, )2k2 - -------- --poutma:x: s 2-rr/, 6 M min lsmax tr

with k1, = TottfTsmin . Using Eqs. (3.66 a,b) we obtain

At full load, maximum loss occurs at the highest frequency of operation, i.e. at Mmin. Thus

1 zvs psmax = (l _ M . ) Ksw (Mmin) mm

Buck-ZVS-QRC (4.84)

where

b) Boost ZVS-QRC

(4.86)

The quantity MJF in Eq. (4.86) is always larger at low line (Mm.J since for FW F(Qpmin/M,2)

!::::::2-rr. For the HW case, F(Qpmin/Mmin•l) !::::::2-rr while F(Qpmin/Mmax•l) !:::::: rr + 2AR + 3/(2AR) . Since

AR is at least equal to 1, then Mmax/F(Qpmin/Mmax) is always larger than Mmin/F(Qpmin/Mmin). Hence,

(4.87)

c) Buck-Boost ZVS-QRC


The maximum loss occurs at low line (Mm.,.) following the same reasoning for the Boost case.

Hence,

2 zvs Psmax = (1 + Mmax)(l + Mmin) Ksw (Mm.,.) Buck-Boost ZVS-QRC (4.88)

Notice that this loss machanism becomes more significant at higher switching frequencies. If

we assume a typical converter operating at 10 MHz. with a tum-off angle of about 15 °, then using

Eq. (4.83) the switching loss is in the order of 1 watt, and is higher for higher switching frequencies.

For lower switching frequencies with fast gate drives this loss is insignificant.

4.4.3 Rectifier Diode Losses in ZVS-QRCs

The conduction losses in the diode are one of the major losses in any low voltage converter.

The current in the freewheeling diode is given by

. ( ) { 1 -cos W 0 t ln t -= Q

fx 1 - _P ()) (- COS ()) T2 M o o

(4.89)

Computing the average current, I Da•g using

yields


Buck: I Davg = Io( 1 - lvf) Boost: Ivavg = Io

Buck-Boost: Ivavg = Io

from which the normalized conduction loss P D = : Dcond is given by outmax

Buck: Pv = (1- Mm;n) VDN Boost: PD = VDN

Buck-Boost: PD = VDN

(4.90)

(4.91)

Equation (4.91) is identical to Eqs. (4.20) and (4.64) since the average diode current in any topology

is the same even though the time waveforms are different.

4.4.4 Resonant Tank Losses

Resonant Inductor Losses

The resonant inductor in a ZVS-QRC carries current in all four modes of operation of the

circuit. Figure 4.13 shows the time waveform of the resonant inductor. This current is given ana-

lytically by

cos mot

i~: ~ ~{w,t+(-l)) ~ -l} 0 ~ t ~ t, t, ~ t ~ (2

t2 ~ t ~ t3 t3 ~t~T.

Notice that for Boost converters the time function of iL0 is shifted by Ig , in other words

· I (1 isuck) lsoost = g --y;-

Carrying out the integration of the square of iL ( t) it can be shown that 0


(4.92)

121

lx 1---....--,.

\ \ .to t

~T T2 T3

\ t3

T4

\ Ts

Figure 4.13 The current waveform of the resonant inductor of a ZVS-QRC


Maximum loss in L 0 occurs at full load and at the corresponding lowest frequency,

M = Mmax. Since ~~pmin = lf'.LlRLlg, then Eq. (4.93) can be simplified further by using h max

~o for FW ~ 2(.LlRLlz for HW

Thus for HW we have

(4.93)

i.e. at

(4.94)

(4.95)

where the switching frequency was evaluated at full load low line using the approximation Qpmin 2 3

F(~,l) ~ 7r + '·LlRLlg + 21' Ll Ll max "'• R g

For the FW case we have

(4.96)

PL. The normalized power loss 0 can thus be found as

poutmax

Buck: PL = PL [ 1- (1- Mmax)Lzv] 0 0

Boost: PLo = PLi.Jmax(Mmax- Lzv) (4.97)

Buck-Boost: PL = PL (1 + Mmax)(l + Mmax- Lzv) 0 0

where,


Resonant Capacitor Loss

1 4

= 4 rr/2 + 3"-'A·R~g +2/(,,~R~g) 1r + 2,,~R~g +3j(2,,~R~g)

FW

(4.98) HW

The resonant capacitor ( composed of CDs and an external capacitor) basically has a sinusoidal

current waveform gievn by

ic (t) {1 --t- = cos w.t (4.99)

The rms current can be shown to be given by

(4.100)

The loss associated with Ic is maximum at maxunum frequency and full load (i.e. at orms

Q d i\1 ) U . QP min 1 ~ p min an j min • smg ~ = y g we get

mm ~:~.,

HW

FW

P' The normalized power loss P c0 = p co is thus

outmax

Buck: Pc = Pc (I- Mmin)Hzv 0 0

where

Boost: Pc = Pc -M1 Hzv 0 0 . m1n

Buck-Boost: Pc0 = Pc0 1 ~ . Hzv + mm


(4.101)

(4.102)

124

11: + 2(.L\ +3f(2(v~g)

11:- l/(2(.~g) "'j_ 211: - 2

HW (4.103)

FW

Notice that the resonant potential across the drain-to-source of the MOSFET will induce a

similar current through CGv . The series resistance in the gate circuit will act as the esr of CGv .

Hence power is lost from the source circuit in the gate drive which is easily found from

(4.104)

If CGv is large, high resonant current flowing in the gate drive may develop a potential high enough

to keep the gate on (above Vr) for the mode interval T1 thereby increasing the conduction losses

significantly.


4.5 Co1nparison of Losses

4.5.1 Conduction Losses in the Switch

The maximum conduction loss was obtained for PWM, ZCS and ZVS converters. The nor-

malized forms of Eqs. (4.7), (4.42) and (4.78) permit a direct comparison for a given set of specifi-

cations.

For example, let us assume an application where a Buck-Boost converter is used. A FW

ZCS-QRC and HW ZVS-QRC are to be used with Mmax = 5/6, Mmin = 5/12, ~8 = 2 and ~R = 4. Then we have

which shows that

and

e PWM: Pc = PDs(l + f)Mmax(Mmax +1)

ZCS: Pc= l.5pDsMmax.(Mmax.+1)

ZVS: Pc = PDs(Mmax. +1)[ Mmax + 6 + 3n'/~(.~R~g)]

Pzcs ,...., 1.5 ~ 1.5 PPWM - 1 ~,..2

+~c

Pzvs --~

PPWM


which shows that for the same device, the ZCS-QRC will have the highest conduction loss.

4.5.2 Losses in the Resonant Tank of QRCs

Both ZCS- and ZVS-QRCs have a resonant tank in which part of the losses are incurred. If

we wish to compare the maximum losses in the tank for a given set of specifications we need only

refer to the normalized loss expressions. We continue with the same specifications used in the pre-

vious section.

a) Comparison of Losses in the Resonant Inductor

Using Eqs. (4.65) and (4.97) we have

Pzcs PLoc 1.5Mmax Pzvs = PLov 1 +JW.max-Lzv

= 1.05 PLoc PLov

If the two converters were to use resonant inductors of the same esr, then the maximum losses in

the ZCS-QRC would be slightly higher than those in the ZVS-QRC.

b) Comparison of Losses in the Resonant Capacitor

or

Using Eqs. (4.68) and (4.102) we have

Pzcs = 4.65 Pcoc Pzvs Pcov


which shows that if the resonant capacitors in both circuits have the same esr, .the ZCS-QRC will

have 4.65 times the maximum power loss of the ZVS-QRC.

4.5.3 Comparison of Switching Losses

The switching losses in PWM, ZCS and ZVS converters can be compared using the ex-

pressions for the conduction loss, the switching loss, the capacitive discharge loss and the parasitic

inductance loss. These losses are a function of frequency and hence the frequency dependency can

be observed by plotting them against different switching frequencies. A switch efficiency, Jlsw , is

defmed as

The plot in Fig. 4.14 shows the switch efficiency of PWM, ZCS and ZVS Buck converters operating

at a load of lOA at SV. The comparison was made with the same switching devices in order to show

a possible comparison of performance vs. frequency along with an estimate of the relative break

frequencies. Notice that at low frequencies PWM switches are more efficient while ZCS are the least

efficient (due to higher rms currents). As frequency increases, the PWM switch loses its efficiency

rapidly while ZCS and ZVS switches extend well beyond the PWM switch. The ZCS switch then

starts to lose efficiency at higher frequnecies and fmally ZVS switches degrade at the highest fre-

quencies. The exact value of the switch efficiency depends on the specific parameters of the circuits

under investigation.


0 0

0 L/)

fD

0 L/)

N (D

0 L/)

~

8

-+. 11 r--.. t\zvs

""' 1\ I' ·,

zcs\ PWMI\_ 1\ 1\ 1\

\ ~ \

\ I\

\ 1\

\

1\. ~

l.E+3 l.E+S l.E+S l.E+7 J .E+8

frequency

Figure 4.14 The relative switch efficiency of PWM, ZCS and ZVS converters as a function of switching frequency. The roll-offs give an indication of the relative frequency ranges of each switch.


Chapter 5

Analysis of Transistor Switching Times

5.1 Introduction

In this chapter an analysis of the turn-on and turn-off processes in the MOSFET switch is

performed. Analytical expressions to predict these times are derived. Previous studies [14,15] have

neglected some of the various effects of the parasitic capacitances CGD and CDs . For the purpose

of low frequency switching such an assumption is justified. However, in order to predict the be-

havior of switching converters at higher switching frequencies (MHz and above), an effort should

be made to explain the switching behavior including the effects of the switch parasitics. The analysis

presented in this chapter is performed for MOSFETs in PWM, ZCS and ZVS configurations. The

analytical expressions derived are used to predict the switching times in some representative con-

verters and are compared to results obtained from IGSPICE simulation to assess the accuracy of

the formulas and to show the predicted effects of the parasitic elements on the switching waveforms

and consequently the switching times.

Analysis of Transistor Switching Times 130

The first section deals with the tum-off of the switching FET in PWM, ZCS and ZVS circuits.

The second section deals with the tum-on of the FET in the same topologies. Theoretical ex-

pressions are obtained to predict the tum-on time. Each section is followed by examples and ver-

ifications against SPICE simulations.

5.2 MOSFET Switclzillg Turll-off Time

5.2.1 Turn-off in PWM Circuits

The equivalent circuit of any switching MOSFET consists of a non-linear current source, lvs

and three parasitic capacitances, Cns , Cr.n and Cr..:: (Fig. 5.1). These parasitics along with external

circuit components and parasitics are of significant importance in determining the transitional

switching times.

The capacitor Cvs is assumed to be non-linear of the form given in Eq. (3.11) while CGD is assumed

to be a constant capac;itor. The external current ivs at the drain terminal comprises the channel

current, lch and currents through the parasitic capacitances Cvs and CGD.

The circuit in Fig. 5.2 shows a MOSFET at tum-off in a PWM converter. Prior to tum-off,

a static condition exists and the channel conducts a de current, t , dictated by the lo_ad an~ line

conditions in the converter. whlch lS represented bv a constant current source. Across this source

(though not shown in the figure) is a freewheeling diocle to condur.t I. once the MOSFET has

completed its tum off.

The inductance, LP represents the series drain lead inductance. The resistor, Ra represents the

equivalent resistance of the gate drive circuitry. Assume that the gate drive provides a step voltage

of on-level of V2 and off-level V1 (or ground). Thus, prior to tum-off the gate-to-source capacitance


Cgd

Gate

Rs

Source

Figure 5.1 Equivalent circuit of a switching MOSFET.

Analysis of Transistor Switching Times

Cds

132

Vdd

Rg

Figure 5.2 Tum-off of a MOSFET in a PWM converter.


is charged at V2 and LP carries a constant cun-ent I. , which establishes the initial conditions of the

circuit before tum-off. The total tum-off time, T.11 is divided into three intervals: the delay time

Tdoff , the drain voltage rise time, T, , and the cun-ent fall time, T" off' It is the time T, that partly

determines the overlapping switching loss at tum-off. Hence,

(5.1)

Each of these times will be found separately as follows.

1) The Delay Time, Tdoff

The instant when the gate drive VOltage drops from V2 to V1 the gate-tO-SOUrce VOltage Will be

at V2 and cannot follow the drive instantaneously due to the gate R -C time constant, RGCGs = 1' Gs

. The voltage VGs takes a ft.nite time to drop. The channel current is related to VGs (in the pinch-off

region) by

(5.2)

where Vr is the gate threshold voltage and K is the intrinsic transconductance parameter of the de-

vice. In the foregoing discussion the channel length modulation parameter, A. is assumed to be zero,

or in other words the device characteristics are horizontal in the pinch-off region. Figure 5.3 shows

the equivalent circuit during the delay interval.

As vGs falls, the device will move from the pinch-off region to the ohmic region. The gate-to-

source volta~re corresponding to the transition from the p~ch-off to ohmic region is called v •. The

channel will continue to conduct a constant current in this interval and no changes occur until VGs

has reached V, . This voltage level v. is the lowest gate-source voltage that will still sustam the

output current in the channel. The simple R-C network of Fig. 5.3 is used to determine Tdoff. Tllis

interval ends when vGs drops to the level v. (which is determined later in the analysis).


Rg

v1 V1 IT

Figure 5.3 Equivalent circuit during the turn-off delay time, T doff.


(5.3)

Thus,

(5.4)

2) The Rise Time, T

The equivalent circuit of this interval is shown m Fig. 5.4. Once Vas drops to Vc it remains

constant at that level until the drain-to-source voltage rises to the potential of the supply voltage

so that the freewheeling diode is allowed to conduct the load current. It is important to note here

that even though I. is still being conducted in L0 , not all of it flows in the channel but is split among

the channel, Cvs and Cav . the actual channel current is less than I •. In other words,

(5.5)

This occurs because a dvfdt exists across both Cvs and Cav and the current source at the drain

terminal still forces the total current to be constant. Notice that the voltage at the gate remains fairly

constant at Vc . Hence icGs ~ 0 and the current in R, is fair~v constant. The gate drive thus draws

a fairly constant current from the drain through Cav . This in tum forces the drain potential to rise

linearly and thus a constant current flows in Cns as well. In order to determine the rise time T, we

must fmd the components ich , icDs and icGD .

a) The gate-to-drain capacitor current, icGD :-

This current component is constant and can be determined from

(5.6)


Vdd

lo.

Cgd

Rg

Cds

Cgs

Figure 5.4 Equivalent circuit during the rise time, Tr .


where ~ is the slope of the rising drain potential, and d Vis the differential rise in the drain po-'

tential = VDD- vDS(on) (see Fig. 5.5).

b) The drain-to-source capacitor current, icns( t) :-

This current component could be considered as a constant current due to the linearly rising

drain potential if CDs were a constant capacitor. However, CDs is a non-linear capacitor and as

presented in chapter 4 has the form:

(5.7)

The current in CDs is thus,

(5.8)

Since the drain-to-source voltage rises quite linearly during this interval then

(5.9)

Hence

(5.10)

Therefore

(5.11)


Vds

Vdd

6V

~s~ time ~========~--------L-------~·

{a) Vgs

Vc ·······························;:'"---------!_~

I

time

I

' T doff' Tr {b)

Figure 5.5 Voltage waveforms, (a) drain-source (b) gate-source


The current in Cns becomes

Cns icns(t) = ,1. V 0 t 112

(1+--) 4> T,

(5.12)

and at the end of the interval, T,

ic (T,) = Cns .1-V 1 [1- _l .1-Vfcf> ] DS o T, (1 + .1. Vfcf> )''2 2 1 + .1. Vfcf>

,...., Cnso .1-V 1 - 2 J1 + .1-Vfcf> T,

(5.13)

for .1. V/4> > > 1

If we defme C.q as the "equivalent linear capacitor" of Cns then icns can be found immediately from

the expression of a linear capacitor rather than a non-linear one. Let

Cns /2 c = 0 (5.14) eq J1 + .1-V/cf>

then

icns(T,) = c.q ~ (5.15) r

Now that both capacitor current components icns and icGD have been found we may evaluate

the channel current given by Eq. (5.2) and (5.5) as follows.

(5.16)

The gate-to-source voltage is approximately constant during this interval and is given by the level .1-V Vc = V1 + RaCany . Let us assume that V1 = 0 for simplicity (i.e. the gate drive low is at

r

ground). Then

(5.17)


Equation (5.17) is readily solved forT,. Once obtained, T, can be used to compute the value of the

constant gate level, Vc .

(5.18)

This level Vc has a slight time variation and can be found if the instantaneous value of Cvs(t) is used

in Eq. (5.16) rather than its linear equivalent value. This yields

I _ CGv.1.V _ CDS0 { 1 1 .1.Vt/T, } • T, )1+.1.Vt/T, 2 1+.1.Vt/T,

(5.19)

Equation (5.19) provides a reasonable prediction for the time dependence of the flat level Vc during

the rise period of Vvs .

3) The Current Turn-off Period, T" •11

Mter the period T, has elapsed, Vvs completes its rise to the supply voltage, Vvv . At this point

the diode begins to turn on and the load cur;rent can start to flow through it. The terminal drain

current, ivs will thus /start to drop from its full value I. down towards zerc Since this current is

flowing in Lp , it will ring with the capacitances Cn~ and CGD and oscillatory, rather than linear

waveforms are expected. In particular, the current will fall in a cosinusoidal fashion and the drain-

to-source voltage will oscillate in a sinusoidal manner. Since we are mainly concerned with esti-

mating the time T" off defmed as

ivs(T" off) = 0 (5.20)

(see Fig. 5.6) then we may make the following approximations for 0 ~ t~ T".11

vLP(t) =- Vvv sin w.t ~ - .1. V; r

O~t~T"off (5.21)

by using the well known approximations


Since

then

2 (wt)

coswt~ 1---2

sinwt~ wt

divs t VL =L --=-LlV-

'P P dt T,

2

iL (t) = ivs(t) =I - LlV-t-'P • 2LPT,

Setting ivs(T".11) = 0 we obtain

T''•tt= J 2I.Lp :v

(5.22)

(5.23)

(5.24)

(5.25)

The total tum-off switching time T.11 is thus obtained by solving Eqs. (5.4), (5.17) and (5.25). hence,

(5.26)

Note that the switching loss is encountered in the period T, .

SPICE Simulation and Theoretical Results

IGSPICE was used to to simulate the tum-off several PWM switches and the various tum-off

times were measured from the simulation and compared to the analytical solutions of Eqs. (5.4)

(5.17) and (5.25).

In solving Eq. (5.17) forT, it is necessary to rearrange its terms as

(5.27a)

where,


time

Td+Tr

Figure 5.6 Current turn-off time, T" off


X= LlV -r:GD T,

ctot = CGD + c.q

Equation ( 5.17) is solved for x rather than T, to avoid numerical inaccuracies. This quadratic yields

two solutions for T, . The proper solution must satisfy the following conditions: ilV 1) lo- (CGD + C.q)T > 0

LlV r 2) RGCGDy > Vr

r

Notice that Eq. (5.27) can be normalized in terms of the application and device parameters

by defining Rr as the effective switching resistance of the MOSFET during T, . r

with

1 c.q Rr =--(1+-) r KVr CGD

c = _1_(1 + DSo ) KVr 2CGDJ;i;

2 Rr z +z(-r -2) +1- 171 = 0

Ra

where

z = LlV -r:GD Vr T,

'11v = ~: = blocking capability of the MOSFET. I

'1'/r = - 0 = current parameter of the MOSFET. lx

The effective switching resistance, Rr is a function of the device at hand and the required applica-r

tion (il V). An explicit solution for T, is thus obtained in terms of these normalized parameters.

(5.27b)


Simulation 1

The IRF330 device was used as the basic device. The circuit conditions and capacitances were

varied.

CGD = 100 pf ' CDS = 250 pf 0

Vr = 3.6V , K = 6.72

I. = 3A , L1 V = 58V

Ra = 2 n , Lp = 15 nH

Solving Eq. (5.27) results in

T, = 3.6 ns

while the simulated time in Fig. 5.7 is T, = 3.4 ns. Furthermore, solving Eq. (5.25) yields

T" •ff = 2.12 ns

while the simulated time is T" off = 2.34 ns.

Simulation 2

CGD = 350 pf ' CDS = 750 pf 0

VT = 3.6V ' K = 6.72

I. = 3A , L1 V = 27V

Ra = 2 Q , Lp = 15 nH

In this case T, = 5.9 ns and T"•ff = 4.44 ns. The simulation shown in Fig. (5.8) gives T, = 5.63

ns and T" off = 4.4 ns. showing close agreement.


, __ a) D-S Current .......

J.eaaa

z.eaaa

1.eeaa

e.eaaa

-·--· -z.aeaa

-J.IIIA

~.aau

_,_, ... I.IMS S.MhS ....... IS.II•S za.ea.s U.II.S

III.IU

b) D-S Voltage ,. ... u

..... u

71.11U

"·"u

se.aau

ce .. eeu

JI.18U

ze.uu

IIDIQU

...... ., ••••• s .S.~IIoS1 li.II•S ''·'""s Zl.llt~~$ 2'$.1thS

't 21.11U I I

c) G-S Voltage I I 17.,_U trl 'J.w' T,.. I

IS.IIU I I I

12.51U

II.IIU

1. 588U

5.188U

2.581U

•-•••u -z.:seau _,_, . ..,

•·••as S.MhS JS .... s ZI.II•S l, .••• ,

Figure 5.7 Tum-off of a PWM switch, simulation (1)


J .....

a) D-S Current I.'HIA

, ...... 1.~ ...... ').H ..... ......

... ,.. .. _..

......... -··~ .,., ....

1.1115 ,_ ..... "·""' U.llaS lt.ll•' !, .... \

H. Mil

b) D-S Voltage 4'J.Herl

41.,HV

l5 ... ~

M.l-.,

n .....

ZI.MII

n.NU

....... 1.111V

1.411V ...... ...... , "· II•S ,._ .... , !, ..... \

ZI.IIV

c) G-S Voltage "·51~

n.MII

IZ.H~ ... ...., l.H-.,

'·-I. Hill I I ··- ~If I rr' '---.,.,.... ...... ~ ...... '·-·· ....... "····· ll.u.s ~~- ... ,

Figure 5.8 Turn-off of a PWM switch, simulation (2)


5.2.2 Turn-off in Q RCs

a) Turn-off in ZCS-QRCs

A ZCS-QRC is designed to tum-off with no current flowing in the switch. Hence no over-

lapping current and voltage is encountered and no switching losses at tum-off occur. No switching

times are involved.

b) Turn-off in ZVS-QRCs

In a ZVS-QRC, the MOSFET is under very similar conditions at turn-off as in a PWM con-

verter. Figure 5.9 shows the switching waveforms for associated with a ZVS-QRC at tum-off.

Notice that the constant current I. in L. will continue to flow but is merely switched from the

MOSFET chanriel over to the resonant capacitor. A fmite time, T.ff is necessary to complete this

transition, resulting in a tum-off switching loss discussed in chapter 4. Therefore, the switching time

of major importance in a ZVS-QRC is the current fall time, T.ff.

In order to determine this time analytically we recognize the fact that VGs will fall to its fairly

constant level, Vc while the channel current will drop to zero with c. and CGD taking over the cur-

rent in L •. As icAt) drops in a linear fashion, VDs will rise parabolically as shown in Eq. (4.82). Since

both CGs and CGD were charged at V2 prior to tum-off, an exponential function will govern the decay

of VGs during the period 0 ~ t ~ T.11 . Hence

and

-TofT

vc = VGs(Toll) = v2 e TG"

(5.28)

(5.29)

where TG = RG(CGs + CGv) . To determine T.11 we need to fmd the constant level Vc . Let

LlVDs = Vv5 (T.11) or from Eq. (4.82)


Vgs

time

lo ILp 1-----....."\:-----------------

Vds

time

Toft

Figure 5.9 Waveforms of a ZVS-QRC at tum-off.


I.T•tt LlVvs=--2Cvs

0

Then the non-linear capacitor Cvs(T.11) will be

(5.30)

(5.31)

Since I. is now split between Cav , Cvs and c. then the portion flowing in Cav and consequently

in Ra is given by

(5.32)

Then the voltage drop across Ra = -Vas(t) is

(5.33)

Inserting Eq. (5.33) into Eq. (5.29) gives

(5.34)

This equation can only be solved numerically, since it involves T.11 implicitly. However for pur-

poses of estimation of T.11 , Eqs. (5.33) and (5.29) can be solved iteratively by starting with

Cvs(T.11) = Cvs0 and proceeding to obtain Vc and T.11 • Further improvements are obtained by cor-

recting Cvs using Eq. (5.31) and so on. Notice that if the external capacitance c. is much larger than

Cvs , then one could neglect its non-linear effect.

Another approximation that can be used to simplify the calculations of T.11 would be to cal-

culate the time required for the gate potential to collapse to the threshold voltage based on an ex-

ponential decay, since no appreciable current flows therein after that point. This leads to


(5.35)

It is more preferable to use this approximation for lower values of CGD , since the gate potential

v. is expected to be lower than Vr and hence the FET has been fully turned off.


Simulation 1

A ZVS-QRC was simulated and switching waveforms were used to measure the tum-off time,

T.11 and was compared to the theoretical predictions.

The IRF330 was also used in these simulations.

CGD = 40 pf , Cvs = 0 , C. = 300 pf , CGs = 660 pf . 0

VT = 3.6V ' K = 6.72

I. = 3A , V2 = 15V .

RG = 20

Ifwe solve Eq. (5.35) for T.11 we obtain

while the simulated value for T.11 is 2.1 ns. The waveforms are shown in Fig. 5.1 0. Notice that due

to the low value of CGD in this simulation, the gate potential v. is quite close to zero ( V1). In fact

from Eq. (5.33), Vc = 0.71V, while that level as obtained from the simulation is 0.7V showing very

close agreement.

Simulation 2

Analysis of Transistor Switching Times lSI

.. ,_ a) D-S Current 4 •••••

J .. S..a

J .....

l.3-N.

Z.H8A

l .. s. ••

I.HIA

........ I.Hta

•H41.1"'"'

'"·'"" ., ••• "$ '''·'"' JZt .. laS ,,, .•• s ,.,. .... s

,._.., b) D-S Voltage U5.llrl

He.tu

11"3 .. •v .,. .. ., 123.1U

UI.IV

11.teu

~.teu

l, .•• ..,

l.tllv en.•.s "'·'"' '"· '"'' Ut.I•S ,],.hi :t1•.h•S

I:J.o!,J••

T c) G-S Voltage li.tlf]••

r ... ~ .. -~ 1!' ... .,u t 14 ...... ,

!l.•ol•u

4.f't"V

...... ~t,J

1 .........

l.te•v

···-1:"1 ... , ....... ,., .... '"···· ,,_ .. , ,.,. .....

Figure 5.10 Tum-off in a buck ZVS-QRC. case (1)


·--a) D-S Current l.IHA

l.~··· l .....

l.lHo&

l.IIHio

l .. d ....

.. , ....

.......... I.ZIIA

··"'" --1---l~-•-••n ••·••·~ ~-•••s JO.II•'li AI.OoJ•S '!t ....... i

ISI.ev b) D-S Voltage

2:2'.1U

ZH.tv . ..,_..,

.,._.., an. tv ... ., .., __ ,. __ n.eev

........ ..... , U.tht lt.lh.l Jt.ll•l ..... "'' 51.Ha!

zt.o•u

c) G-S Voltage U.Mv

"·"" 14.11U

U.IIU

II.IIU

t.tttu

,_ ... ., 4.IIIV

'·'''" ·-- ....... "·""' lt.M•'I ,. ..... 4 ..... ,

,. __ ,

Figure 5.11 Turn-off in a buck ZVS-QRC case (2)


CGD = 350pf , Cvs = 450 pf C. = Opf , CGs = 660 pf. 0

VT = 3.6Y ' K = 6.72

I. = 3A , V2 = 15Y

RG = 2 ,Q

The gate-to-drain capacitance is much higher in this case (Cvs = 135 pf at lOY) so VGs ~ 4.3Y (Eq.

5.33) and using Eq. (5.34) T.11 ~ 2.5 ns. From the waveforms of Fig. 5.11 T.11 = 2.5 ns. at VGs = 4.3Y.

Simulation 3

CGD = 350pf , Cvs = 300pf , C. = lOOpf, CGs = 660 pf. 0

VT = 3.6Y ' K = 6.72

I. = 3A , V2 = 15V

RG = 2 ,Q

The simulated waveforms are shown in Fig. 5.12. Using a value of Cvs at lOY = 90 pf in Eq. (5.33)

we obtain v. ~ 3.88. (From the simulation v. = 3.9Y). Hence

whereas the simulated time is 2.8 ns.

Notice that for a ZYS-QRC the effect of CGD• as seen from the simulation, can be critical. If

CGD is too high, then the level V. remains above Vr and the gate is kept "on" during an intended

"off" period resulting in very high dissipation due to the rapidly rising drain-to-source voltage.

When the gate voltage resonates (following the drain voltage) and goes below Vn it may ring back


........ a) D-S Current J.IIIA

,_,.,_ J ......

J • .ZIIA

J.IIIA

.Z.IIIA

,_, ... z ...... z.ZIIA , __

on.o-s . ., .... , ItS. laS "'·'aS tiS. laS ,.~, ... , *·""

b) D-S Voltage ....... . , ..... ........ IH.IV ....... H.IIU

, •••• u

.... ~ ze.eeu

..... u .:, ... , .. , ••• s ., .... , ,., .•. , ,,., .... ll.ttu

c) G-S Voltage II.IIU

IC.IIu

14.11U

IZ.IIU ..... ., ..... ., '·"'" ...... u

Z.HIV ...... .... - -·- IH.IoS ,., .... tn.••• ,., ....

Figure 5.12 Tum-off in a buck ZVS-QRC case (3)


again over Vr causing an undesirable turn-on. Figure 5.13 shows the MOSFET power dissipation

curves for the three simulations (1), (2) and (3).

Notice how the dissipation was much higher in cases 2,3 ( CGD = 350 pf) compared to case 1 (

CGD = 40 pf). In cases 2,3 Vc was above the threshold and the switch was left on for a longer period

than in case ( 1) where the switch was fully turned off.

Even though the Miller effect is eliminated in ZVS-QRCs at turn-on (zero-voltage), the reverse

feedback capacitance CGD can cause serious problems if too much current is fed back through it.

This could happen if CGD is too high or if dvfdt at the drain is very rapid (high frequency operation).

Such problems could be alleviated by a more negative drive in the gate circuit rather than using

ground potential.

5.3 MOSFET Switchillg Turll-oll Tinze

When a MOSFET is switched from the off-state to the on-state, parasitic capacitances and

inductances determine the exact nature of the turn-on process. It is interesting to note that both

ZCS and PWM converters would have a very similar turn-on process with variances in the actual

amount of drain lead inductance (either parasitic or resonant). A ZVS-QRC will turn-on with

zero-voltage and hence no turn-on loss is encountered. Therefore the ZVS-QRC will not be con-

sidered any further since there is no V-1 overlap.

The equivalent circuit of a FET in a PWM or ZCS converter is shown in Fig. 5.14 The

inductor, LP represents the parasitic inductance in the PWM case and the resonant inductor in the

ZCS-QRC case. In order to turn on the device, a delay period ,Tdon must pass so that VGs rises to

the threshold followed by an interval Ton during which the drain voltage collapses drawing current

from both CGD and CDs.


Figure 5.13 MOSFET power dissipation in a ZVS-QRC, (simulations 1, 2 and 3)


Vdd

lo

Lp

Rg Cds

JV2

Cgs

V1

Vgs

V2

time

Figure 5.14 Turn-on circuit of a MOSFET in a PWM or ZCS-QRC


1) The Turn-on Delay Time, Tdon

The initial state of the circuit prior to turn-on is determined by the static voltages on Cvs•

CGv and CGs . Initially, CGs is at the low gate level of V1 (or ground), while Cvs and CGv are both

charged at the supply potential, Vvv . To turn on the device completly, Cvs and CGv must be dis-

charged at least to ground while CGv must reverse its charge to + V2 • No current flows in the

channel until VGs has risen to the threshold Vr. The voltage build up is that of an R-C circuit given

by

(5.36)

where -rGs = RGCGs . Notice that no power loss is involved in this interval since no current has

started to flow.

2) The Turn-on Time, Ton

Once v Gs reaches V r the channel can start to conduct current and the drain potential starts to

drop. This in turn will cause currents to flow in both cGv and Cvs . During Ton the gate voltage

will remain at a fairly fixed value VGsi which can be obtained by solving

(5.37)

or

(5.38)

The current in CGv is the same as in RG so

(5.39)

Substituting Eq. (5.38) into (5.39)


(5.40)

which can be readily solved for Ton . The value of CDs is taken at VDs = VDD . The rising current

component in LP was neglected in this formulation for simplicity ( since iL will generally rise slowly p

compared to icDs or iceD). However, we can incorporate this current as follows. Since

then,

diD.', vL = VDD- VDs(t) = L --P P dt

iDs(t) = -t-J [VDD- VDs(t)] dt p

Using VDs(t) = VDD- tlV j we get on

Now Eq. (5.38) is modified to include iL and this yields p

(C C ) tlV tlVTon GD+ DS KT + 2L on p

(5.41)

(5.42)

(5.43)

(5.44)

which is a more complete equation for determining Ton. Notice that as in Eq. (5.27) it is necessary

to rearrange Eq. (5.40) to avoid numerical inaccuracies while solving as follows

(5.45)

or

(5.46)


where

X= ~V TGD

TOTI

'GD = gate-to-drain time constant = RGCGD


A Buck PWM converter was simulated using IGSPICE with the following parameters.

CGs = 660pf , CDs = 750pf , CGD = 350pf 0

VT = 3.6V ' K = 6.72

V2 = 15V , VDD = 30V

RG = 8 n ' LP = 400 nH

a) Tum-on Time, T0TI

Solving for T0 TI in Eq. (5.46) we have

T0TI = 7.73 ns.

Using the simulated switching waveforms shown in Fig. 5.15, T0 TI is found to be 7.87 ns.

b) Drain-to-Source Current (iDs or iL) p

Equation (5.43) is used to predict the rise in ivs (iL ) after the interval T011 • p

iDs(T0TI) = VDD ~Tl = 0.3A p

From the waveforms of Fig. 5.15, we find this rise time to be


51.HU

45.18U

41.18U

J5.88U

JI.88U

25.18U

28.18U

J5.88U

Jl.lliU

5.11111U

5 ... hS

Figure 5.15 Turn-on of a PWM switch with a parasitic inductance of 400 nH.


showing close agreement with theory.

Notice that for lower values of parasitic inductance, this current rise will be much faster and

could even complete its full rise to the load current when, or before, Vns falls to zero. In fact, the

limiting case with LP = 0 would force the current to rise first before Vns starts to collapse. It is clear

that larger LP will allow for lower tum-on loss (however aggravating the tum-on losses as discussed

in chapter 4). This effect is shown in the simulation of Fig. 5.16 which is the same circuit of Fig.

5.15 but with less inductance (Lp = 15 nH) and RG = 2 n.

5.4 Conclusions

The MOSFET switching times were analyzed including the effects of the parasitics. The vari-

ous tum-on and tum-off intervals were derived analytically and closed form solutions for these

times and voltage and current waveforms were obtained.

The effect of the reverse transfer capacitance, CGD is shown to have profound effect on all the

switching waveforms. In particular a larger value of CGD can result in unwanted tum-on of the

switching device in ZVS-QRCs due to the high dvfdt during the off period. This effect becomes

more pronounced at very high frequencies. A remedy for this problem would be to use a negative

tum-off gate voltage rather than ground. The effective gate drive resistance is a major limiting factor

in all switching times. The drain inductance is shown to decrease the tum-on switching losses in

PWM and ZCS converters, but will cause more loss at tum-off in PWM converters. The theore-

tical derivations are shown to be in very close agreement with computer simulation for the cases

investigated providing a reasonable theoretical estimation of switching times for determining the

switching losses.


4$.H

41.11

n ...

31.81

2:1 •••

21.81

., ... 11.81

'·"' 1.881

... ~.eat ,. .... s 511.hS

Figure 5.16 Turn-on of a PWM switch with low parasitic inductance (15 nH)


The effect of the non-linearity of Cvs has been incorporated into the analysis, a necessary step

for improved accuracy since the drain-to-source voltage experiences wide excursions. The analysis,

however, adopted a constant value for CGD. This capacitor is also non-linear, and further refmement

would have to include this effect. Notice that SPICE does not model this effect and some discrep-

ancies may be observed in practical circuits.


Chapter 6

Experimental Results and Verification

6.1 A SOJtV Full-Wave Zero-Current-Switched Flyhack

Quasi-Resonant Converter

6.1.1 Circuit Description

A SOW FW Flyback ZCS-QRC was built in the laboratory to meet the following specifications

maximum input voltage:

minimum input voltage:

0utput voltage:

maximum load current:

minimum load current:

output noise:


60V

30V

sv lOA

IA

50 m V p-p (maximum)

166

maximum switching frequency 1 MHz.

The power stage circuit diagram is shown in Fig. 6.1. The detailed design procedure is described

in [16]. The major design steps using the guidelines derived in Chapter 3 follow.

a) The transformer turns-ratio

The turns-ratio of the transformer affects both the current and voltage stresses of the switch. The

current stress is given by

(6.1)

Where M is defmed as

(6.2)

Table 6.1 shows the effect of the turns-ratio on the current and voltage stresses. As we can see, a

turns-ratio of 5:1 will give both reasonable current and voltage stress and thus was chosen. (For

practical purposes this was modified to 4.67:1.) Hence,

Mmin = 25j60 = 0.42 , Mmax = 0.83

Rmin = 0.5Q , Rmax = SQ

b) Characteristic Impedance, z. The characteristic impedance on the primary side is readily found since

2

Z = n Rmin = 13Q (primary side) o (,/vlmax

Experimental Results and Verification 167

va so-eov

La ~.e: 1 R8ec

L.1 SOCTQO~S 100 nH

Figure 6.1 The complete circuit diagram of the power stage of the SOW FW ZCS flyback converter.


FL S.- iOA

168

Table 6.1

Effect of Turns Ratio on Voltage and Current Stresses

Turns-ratio Peak Voltage (V) Peak Current (A)

6 96 8.0

5

4

3

Experimental Results and Veri(tcation

90

84

78

9.0

10.6

13.3

169

c) Resonant Frequency, w • .

The tank resonant frequency is tound from the maximum switching frequency, hmax· Hence

_h_ma_x = _l_~..::.m:.::ax:....__ = 0.45 J. 1 + Mmax

For a desired maximum switching frequency of 1 MHz. this yields

J.= 2.2MHz

The resonant elements can thus be found

L = z. = l,u.H (primary side) 0 w.

2

c. = _n_ = 0.14,u.F (secondary side) z.w.

The resonant inductor was completely formed by the leakage inductance of the transformer.

d) The low-pass filter inductor, L1

The low-pass ft.lter inductor is designed using the formula

L, 1 1 [ -t( 1 ) .J ] -L ~' 1 ~. 1t'-COS 1 M. + Mm;n(2+Mm;n) o f + 1 mm + mm

With '' = 0.1 (i.e. a ripple in the inductor of about 10 % ) we obtain

L1 ~ 20L. ~ 20,u.H (primary side)

which concludes the basic design procedure of the power stage.


(6.3)

170

6.1.2 Experimental Results

a) Verification of Stress Analysis

The waveforms in Fig. 6.2 show the switch current and voltage operating at full load at both low

and high lines. The peak stresses are obtained from oscillograms and are compared with the the-

oretical predictions in Table 6.2. The switch voltage reaches the predicted steady state value after

ringing due to the interaction of CDs with Lo . The theoretical predictions are shown to be in close

agreement with experiment.

b) Verification of Loss Analysis

The circuit was tested under various operating conditions, varying from light to full load ( lA

to lOA) and low to high line ( 30V to 60V ). Different MOSFET devices were also used ( IRF 540

and IRF 630 ). The efficiency was recorded for comparison with theoretical predictions. Table 6.3

presents a summary of these operating conditions.

The results of Chapter 4 were used to estimate the various RMS currents and losses in the

power stage for these three operating conditions. The results are shown in Table 6.4. The increased

difference between predicted and measured losses at light load is due to reduced accuracy in for-

mulas for the mode times, T1 •• T4 , which were derived assuming an efficiency of 100 %. (A

full-wave ZCS-QRC has poorer efficiency at lighter loads due to the large circulating resonant

current.) The loss in the snubber circuit was simulated on IGSPICE. The core loss was estimated

using experimental data for the core material (TDK H7C4) given in [22].


(a)

(b)

Figure 6.2 Waveforms of the experimental ZCS converter at full load operation. a) Low line, b) High line. Waveforms top to bottom: Gate drive (20Vfdiv.), primary current (4A/div) and drain-to-source voltage (SOV/div). Time scale 500 ns/div.


Table 6.2

Comparison of Theoreritcal and Experimental Results

Experiment Theory

Operating

Condition

Low line, 30V

High line, 60V

Current

Stress

(A)

8.0

9.6

Voltage Current

Stress Stress

(V) (A)

60 8.3

90 9.0

Table 6.3

Operating Conditions for Loss Analysis

Operating Input Output Switching MOSFET Condition Voltage Current Frequency Type

(V) (A) (KHz.)

(i) 50 10.6 600 IRF540

(ii) 30 8.5 850 IRF630

(iii) 30 1.0 750 IRF540


Voltage

Stress

(V)

53.8

83.8

Efficiency %

75.4

67.2

39.8

173

Table 6.4

Predicted and Measured Efficiencies of the Flyback ZCS-QRC

Operating Condition

Secondary Resistance, 1.4 m!l

Resonant Capacitor ESR, 10m!l

Primary Resistance, 120 m!l

MOSFET Resistance,

Capacitive Discharge Loss

Rectifier Diode (0.6V i,iii 0.7V ii)

Filter Capacitor, 20 mn

Second Filter Inductor

Snubber Loss

Core Loss

Total Predicted Losses

Measured Losses

Predicted Efficiency

Measured Efficiency


(i)

0.5

1.88

1.74

1.24

0.58

6.4

2.17

0.1

2.0

0.4

17.2

17.6

75.9%

75.4%

(ii)

0.64

1.41

1.48

6.2

0.56

5.95

1.65

0.1

1.5

0.5

19.6

21.2

68.9%

67.2%

(iii)

0.164

1.131

0.733

0.52

0.427

0.606

0.022

0.1

1.33

0.45

5.53

7.7

47.9%

39.8%

174

6.2 A 50JtV Half- Wave Zero- Voltage-Switched Fly back ·

Quasi-Resonant Conve1Mte1A

6.2.1 Effect of Load Range on Circuit Design

The HW-ZVS flyback converter was designed to the same specifications of the ZCS flyback

converter discussed in the previous section. However, the specified load range had to be reduced

from lO:lA to approximately 10:4.5A as a trade-off in peak voltage stress across the MOSFET.

The peak voltage stress for different load ranges is (turns-ratio, n = 5)

for ~R = 10 VpTmax ~ lOOOV

for ~R = 2.5 V,rmax ~ 297V

It is clear that if a large load variation (10:1) is to be accommodated, the MOSFET would have to

take a reverse voltage of lOOOV. For lower voltage stress it is necessary to restrict the load range to

a smaller value. This does not mean that the circuit will not operate at lighter loads, but zero-

voltage-switching will not be achieved at those loads and losses will increase. The circuit built in

the laboratory was designed to switch at zero-voltage for a load range of approximately ~R = 2.2

to avoid extremely high voltage stress on the MOSFET. The waveforms in Fig. 6.3 are for a circuit

designed for a load range of 5:1. The peak stress at full load low line is predicted at 510V and 383V

at low line (Fig. 6.3a). The device breakdown was at 400V and low line operation was not possible.

However, the converter was able to maintain ZVS down to about 2A, showing the dependency of

ZVS-QRCs on the desired load range.

6.2.2 Circuit Design


(a)

(b)

Figure 6.3 Operational waveforms of the ZVS-QRC designed for a load range of 5: l. a) Full load (9.5A) high line b) Light load (2A) high line. Notice that the peak stress approaches 400V at full load. The switch breakdown is at 400V. Top to bottom: Gate drive (20V/div), resonant current (4A/div) and switch voltage (SOV/div).


Vg 30-eo v

Rpr L.o

L.i-

Raec 30CTQ0 ... !5 100 nH !5: 1

~------~----~~~lf~~-~_P£_._u_~ __ jf~1-;_: __ u_F~}~~OA Co 1.!5 nF

Figure 6.4 Orcuit diagram of the experimental 50 watt, Half Wave ZVS Flyback QRC (load range 2.2).


The design procedures provided in chapter 2 were used to design the elements of the resonant

tank and low-pass ftlter. The choice of the transformer turns-ratio of 5:1 was to provide practical

values of the conversion ratio, M = nV.JV8 • The circuit diagram is shown in Fig. 6.4.

List of Components :

MOSFET

Freewheeling Diode

Transformer:

Core

Primary

Secondary

Leakage

Magnetizing inductance

Resonant Cap., c. Filter Cap., C1

Filter Cap.,C2

Filter Ind., L1

IRF 740

30CTQ045

TDK H7C4 material, LP 22/18

20 turns # 22 Litz wire

4 turns # 16 Litz wire

4 ,uH, primary side

25 ,uH, primary side

1.5 nF, 600V.

four 4. 7 ,uF and four 22 ,uF, tantalum

five 22 ,uF tantalum

100 nH, 1 turn, MPP core 636H 55280 A2

6.2.3 Prediction of Peak Stresses

The maximum peak transistor voltage stress occurs at low line and full load. The circuit was

operated at V8 = 30V and 60V with I. = 9.3A. The operating waveforms for these conditions are

shown in Fig. 6.5.

Using Eqs. (2. ) and (2. ) and with z. = 53 n the predicted value of the peak stress is 9.35nV.

= 234V. The measured stress is 270V. The difference is due to the non-ideal efficiency of the con-

verter (75 - 85 %). The theoretical equations were derived under the assumption of 100 % effi-

ciency. However if we incorporate the efficiency into the derivation we obtain a more accurate

prediction.


(a)

(b)

Figure 6.5 Circuit waveforms at a) full load and low line (30V) and b) light load (4.5A) high line (60V). Top to bottom: gate drive (20V/div), resonant inductor current (4A/div) and switch voltage (SOV/div). Time scale is 200 ns/div.


(6.4)

where 17 is the efficiency of the converter. Using this equation VpT = 10.43nV. = 261V, using an

efficiency estimate, 11 = 75% which gives a much closer prediction of the peak stress. Other meas-

urements were taken and compared to the theoretical predictions (Table 6.5, with 11 = 75% ).

6.2.4 Estimation of Losses in the Power Stage

The HW flyback ZVS-QRC was built to the same specifications of the FW flyback ZCS-QRC.

The power stage had the following particulars and parasitic resistances:

z. = 53 n (primary side) , ro. = 13.36 Mr/sec.

n = 5 : 1 , Rprim = 57 m n , R,.c = 8 m n

The expressions of chapter 4 were used to estimate the losses in the power stage and to compare

them to the measured losses. Three cases were considered at full load (I. = 9.3A) and various input

line voltages of 30, 50 and 60 volts. The MOSFET used was the IRF740 with rns(on) = 0.55 ohms.

The operating conditions for these cases are:

i) J"& = 30V , V. = S.OV , I. = 9.27A , f. = 567 KHz.

ii) J"& = 50V, V. = 5.0V, I. = 9.31A ,J. = 1.02 MHz.

iii) Vg = 60V , V. = 5.0V , I. = 9.33A , f. = 1.15MHz.

The core loss was determined using the data in [22]. The theoretical predictions give a reason-

able estimate of the losses and efficiency, thus providing a tool for determining major loss factors


Table 6.5

Comparison of Theoretical and Experimental Stresses

Input Voltage Output Current Stress, Theory Experiment

30V 4.2A 149V 160V

50V 7.3A 204V 220V

30V 9.3A 261V 270V


Table 6.6

Esitimated Losses in the SOW HW Flyback ZVS-QRC

Operating Condition

Secondary Resistance

Primary Resistance

MOSFET On-Resistance

Resonant Capacitor

Filter Capacitor

Rectifier Diode

Core Loss

Total Predicted Losses

Measured Losses

Predicted Efficiency

Measured Efficiency


(i)

1.35

0.5

3.94

0.15

0.94

5.58

0.4

13.15

14.9

78.0%

75.8%

(ii)

1.27

0.3

1.93

0.2

1.08

5.58

1.0

11.36

10.7

80.4%

81.3%

(iii)

1.24

0.27

1.56

0.23

1.3

5.58

1.0

11.18

10.6

80.7%

81.5%

182

in a circuit design to help in efficiency improvement. The switching loss at this frequency was very

low (in the order of milliwatts) and was therefore neglected.


Chapter 7

Conclusions

A thorough stress analysis has been performed for PWM and quasi-resonant converters. A

normalization technique has been employed to transform stress expressions from a converter de-

pendant form into a specification dependant form. These normalized forms permit a direct com-

parison between different converters with the mere knowledge of the external specifications and

without performing any detailed design. As a result, it is shown that when compared to PWM

converters, QRCs will always have higher current and voltage stresses. In fact, ZCS-QRCs will

always have at least double the transistor current stresses of its PWM or ZVS-QRC counterpart for

the simplest application (i.e. single input voltage and single load application). On the other hand,

a ZVS-QRC will always have at least double the transistor voltage stress of its PWM or ZCS-QRC

counterpart for the simplest application. Stress dependencies are outlined. The stresses in a PWM

converter are shown to be fixed, only depending on the power level of the application. The maxi-

mum peak transistor current stress in a ZCS-QRC is shown to depend on the percent line variation,

increasing as the desired range of input line voltage is increased. The maximum peak transistor

voltage stress in a ZVS-QRC is shown to depend strongly on the desired load range along with the

input line variation. It is shown that the maximum peak voltage stress increases very rapidly with

Conclusions 184

increasing the desired load range of operation. This load range factor is a severe limitation of

ZVS-QRCs that are to supply widely varying loads. Voltage stresses may reach 5 - 10 times the

input voltage prohibiting operation from a high voltage supply. A design should be made that

comprises a trade-off between voltage stress and efficiency at light load. Reduced stress is possible

by allowing for non-zero voltage switching at lighter loads of operation. However, for applications

with fixed or small load variations, a ZVS-QRC could be optimally designed for efficient operation

off medium voltage supplies.

As a result of the normalized stress analysis, a design procedure for QRCs is derived that would

strictly minimize the current and voltage stresses on the devices for a given set of specifications.

The procedure provides a basis for determining the characteristic impedance, resonant frequency,

resonant inductance, resonant capacitance and low-pass ft.lter inductance. The procedure derived is

shown to be very simple and straight forward. In fact, it is shown that QRCs are very simple in their

design.

An investigation of various loss mechanisms in PWM and quasi-resonant converters has been

presented. Switching and conduction losses in semiconductors and passive elements have been

evaluated and normalized using the same technique used in the stress analysis. Simple, approximate

comparisons are thus possible giving important results. It is found that for converters using the

same switching device and designed to the same specifications, a ZCS-QRC will have transistor

conduction losses approximately 50 % higher than its PWM or ZVS-QRC counterpart. The

tum-on and tum-off losses existing in PWM converters pose a serious limit on higher switching

frequencies. Next in line is the ZCS-QRC which suffers from tum-on switching losses. Finally, a

ZVS-QRC will have the lowest tum-off switching loss, thereby permitting the highest frequency

operation. At lower switching frequencies, it is shown that PWM converters will operate more ef-

ficiently due to the lower rms currents and eliminated losses in extra tank elements. The PWM

switching loss however dominates as the frequency is increased. Increased lead parasitic inductance

reduces the tum-on loss in the FET, but aggravates the tum-off loss, since l/2Li: is always lost.

Conclusions 185

The loss expressions are used to estimate, theoretically, the losses in the power stages of two

experimental circuits, namely a ZCS and ZVS quasi-resonant flyback converter. The total estimated

losses and the measured losses are shown to be in close agreement.

The analysis of the MOSFET switching times presented here provides an analytical method

of determining the various tum-on and tum-off times. It is shown that the gate drive resistance is

the most important factor in determining the device switching speed. The reverse transfer

capacitance, CGD is also responsible for further delays in transistor switching action. It is shown that

excessively large values of CGD could cause very high losses in ZVS-QRCs at tum-off since it could

cause an undesirable tum-on of the device in its high voltage state. Even though the Miller effect

is eliminated in ZVS-QRCs this undesirable tum-on could occur at very high frequencies causing

very high loss. The theoretical expressions are all verified against SPICE simulations showing very

close agreement and accuracy. The effects of CGD and the non-linearity of CDs along with the current

splitting action among the channel and parasitic capacitances previously neglected are taken into

account and provide further improvement in the accuracy of the solution.

Future Research

Future research directions could include an extended look into more loss mechanisms such as

magnetic losses and dynamic impedance loss of the rectifying diodes (more significant in

ZVS-QRCs). A transformation from losses to a normalized efficiency domain coupled with a

volume and weight analysis can provide a very broad and general basis for the comparison of con-

verters on more universal grounds. Further studies of switching times should include effects of the

finite rise time of the supply, the parasitic gate inductance and the non-linear nature of the reverse

transfer capacitance. Finally, a similar effort to analyze stresses and losses in the new extension of

quasi-resonant converters, the multi-resonant converter should be attempted.

Conclusions 186

References

[1] V. Vorperian, "Design and Analysis of DC-to-DC Resonant Converters." Final report for The International Business Machines Corporation, Owego, NY, under contract no. 85-0513-10 to VPI&SU, June, 1986.

[2] K.Liu and F.C. Lee, "Zero-Voltage Switching Technique in DC/DC Converters." IEEE Power Electronics Specialists Conference Record, pp. 58-70, IEEE Publication no. 86CH2207-9, 1986.

[3] K. Liu, R. Oruganti and F.C. Lee, "Resonant Switches: Topologies and Characteristics." IEEE Power Electronics Specialists Conference Record, IEEE Publication no. 85CH2117-0, pp. 106-116, 1985.

[4] K. Liu, "High Frequency Quasi-Resonant Converter Techniques." Ph.D. Dissertation, Virginia Polytechnic Institute and State University, Blacksburg, Virginia, 24061, Oct., 1986.

[5] V. Vorperian, R. Tymerski, K.H. Liu and F.C. Lee, "Generalized Resonant Switches Part 2: Analysis and Circuit Models." VPEC Power Electronics Seminar, Virginia Polytechnic Insti-tute and State University, Blacksburg, Virginia, 24061, Conference Proceedings, pp. 124-131, Nov. 1986.

[6] T. Zeng, D.Y. Chen and F.C. Lee, "Variations of Quasi-Resonant DC/DC Converters." IEEE Power Electronics Specialists Conference Record, IEEE Publication no. 86CH2310-1, pp. 381-392, 1986.

[7] W.A. Tabisz, P. Gradzki and F.C. Lee, "Zero-Voltage-Switched Quasi-Resonant Buck and Fly back Converters -- Experimental Results at 10 MHz." IEEE Power Electronics Specialists Conference Record, pp. 404-413, 1987.

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[21] M. Kazimierczuk, "Effects of the Collector Current Fall Time on the Class E Tuned Power Amplifier", IEEE Journal of Solid-State Circuits, Vol. SC-18, No.2, April 1983.

[22] R. Lewis, "Measurements of High-Frequency Magnetic Core Loss (Square-Wave Voltage Excitation)." VPEC Internal Weekly Seminar, VPI&SU, Jan. 21, 1988.

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