flipkarmadepartment acceptance the project entitled “automatic digital examiner” submitted by...

TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING

PULCHOWK CAMPUS

DEPARTMENT OF ELECTRONICS AND COMPUTER ENGINEERING

A FINAL YEAR PROJECT REPORT

ON

AUTOMATIC DIGITAL EXAMINER

(CODE: EG 777EX)

SUBMITTED BY:

AJAD CHHATKULI (16103) BIKRAM KUMAR KC (16111)

JEEVAN NEPAL (16120) KIRAN THAPA (16121)

MARCH 31, 2009

TRIBHUVAN UNIVERSITY INSTITUTE OF ENGINEERING

PULCHOWK CAMPUS

DEPARTMENT OF ELECTRONICS AND COMPUTER ENGINEERING

A FINAL YEAR PROJECT REPORT

ON

AUTOMATIC DIGITAL EXAMINER

(CODE: EG 777EX)

A PROJECT WORK SUBMITTED TO THE DEPARTMENT OF ELECTRONICS AND COMPUTER

ENGINEERING IN PARTIAL FULFILLMENT OF THE REQUIRENMENT FOR THE BACHELOR OF ENGINEERING IN ELECTRONICS AND

COMMUNICATION ENGINNERING

SUBMITTED BY:

AJAD CHHATKULI (16103) BIKRAM KUMAR KC (16111)

JEEVAN NEPAL (16120) KIRAN THAPA (16121)

MARCH 31, 2009

Department Acceptance

The project entitled “Automatic Digital Examiner” submitted by Ajad Chhatkuli, Bikram Kumar K.C., Jeevan Nepal and Kiran Thapa in the partial fulfillment of the requirements for the award of Bachelor in Electronics and Communication Engineering has been accepted as a bona fide record of work carried out by them in our department.

Head of Department Prof. Dr. Shashidhar Ram Joshi DOECE, IOE Pulchowk Campus

CERTIFICATE

This is to certify that the final year project work entitled “Automatic Digital Examiner”, in partial requirement of the degree of Bachelor in Electronics and Communication Engineering has been successfully accomplished by Ajad Chhatkuli, Bikram Kumar K.C., Jeevan Nepal and Kiran Thapa.

Supervisor Associate Prof. Dr. Jyoti Tandukar DOECE, IOE Pulchowk Campus

Internal Examiner Lecturer Deel Mani Baral DOECE, IOE Pulchowk Campus Head of Department Prof. Dr. Shashidhar Ram Joshi DOECE, IOE Pulchowk Campus

Supervisor Lecturer Prabhat Baniya DOECE, IOE Pulchowk Campus External Examiner Mr. Bhesh Raj Kanel Chairman, NTA Project Coordinator Asst. Prof. Mr. Surendra Shrestha DOECE, IOE Pulchowk Campus

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ACKNOWLEDGEMENT

We are highly indebted to the Department of Electronics and Computer Engineering for

providing us the technical support and the essential equipments in accomplishing this project.

We are very grateful to our project coordinator Assistant Professor Surendra Shrestha and

our project supervisors Dr. Jyoti Tandukar and Mr, Prabhat Baniya for their valuable

suggestions, genuine guidance and much needed encouragement. The constructive criticism

is very much appreciated.

Our sincere appreciation is extended to all the staff of the department for the genuine

cooperation.

Finally, we express our earnest gratitude towards all the colleagues and teachers for

encouragement through discussions and suggestions.

Project Members: Ajad Chhatkuli (061BEX403) Bikram Kumar KC (061BEX413) Jeevan Nepal (061BEX423) Kiran Thapa (061BEX424)

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ABSTRACT

The project “Automatic Digital Examiner” is basically an effort of digital design using

VHDL and prototyping in FPGA. The project aims to build an optical mark reader which will

be used to check the multiple answer answers sheets. As the manual checking of the huge

number of multiple answer sheets is tedious, inefficient and time consuming a demand of

device exists which can fulfill the purpose efficiently, reliably and promptly.

The project is built as an alternative to commonly used scanning – image processing

method of objective answer sheet checking. Apart from the trivial part of comparison of

actual processing results and correct results, the project is completely realized in hardware by

synthesizing digital circuits in Spartan 3E FPGA. A sensor module is used to get analog

voltages corresponding to dark/light marks or no mark in the answer sheet. Before they are

compared directly, certain algorithms of processing are implemented in FPGA after

digitization. A major effort was made in this project also to generate simple and effective

algorithms to attain the best results after processing. Finally attempts have also been made to

store the processed results in a computer and construct a GUI to manage the stored outputs

systematically.

The basic elements integrated in the system are optical sensor array, ADC, FPGA,

including RS232C interface with computer.

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LIST OF ABBREVIATIONS

ADC : Analog to Digital Converter

ASIC : Application Specific Integrated Circuit

ASM : Algorithmic State Machine

CMOS : Complementary Metal Oxide Semiconductor

DAC : Digital to Analog Converter

DIP : Dual Inline Package

FPGA : Field Programmable Gate Array

FSM : Finite State Machine

LED : Light Emitting Diode

SMD : State Machine Diagram

SPI : Serial Peripheral Interface

TTL : Transistor to Transistor Logic

UCF : User Constraint File

VHDL : Very High Speed Integrated Circuit Hardware Descriptive Language

DBMS : Database Management System

RDBMS : Relational Database Management System

API : Application Programming Interface

SQL : Structured Query Language

DML : Data Manipulation Language

GUI : Graphical User Interface

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LIST OF FIGURES Figure 1.1: Answer sheet design…………………………………………………………….......3 Figure.1.2: Outline block Diagram of the project……...…………………………………...…...5 Figure 2.1: Phototransistor equivalent circuit…………………...…………………………....…7 Figure 2.2: Fundamental Phototransistor Circuit (I)………………………………………...…..8 Figure 2.3: Fundamental Phototransistor Circuit (II)…………….……………………..…..…..8 Figure 2.4: Pin out of ADC0808CCN………………….……………………………………...10 Figure 2.5: Timing diagram of ADC0808CCN……………………………………………......10 Figure 2.6: Functional Diagram of buffer HEF4050B……………………………………..…..11 Figure 2.7: Logic diagram one gate….………………………...…………………………........12 Figure 2.8: Pin out diagram of buffer….………………………………………………..…......12 Figure 2.9: VHDL entity with an entity declaration and an architectural description….….......15 Figure 2.10: Typical logic block of FPGA………………………………………………….....18 Figure 2.11: Switchbox connection...................................................................................….....20 Figure 2.12: Serial Data Format…………………………………………...……….………......23 Figure 2.13: RS232 DB9 pin out…………………………...….…………………….…….…..24 Figure 2.14: Figure showing basic terminology used in the relational database model…....….29 Figure 3.1: Basic block diagram of the project...........................................................................34 Figure 3.2: Simplified FSM for project implementation............................................................35 Figure 3.3: ASM for interfacing ADC0808 with FPGA.............................................................39 Figure 3.4: Simplified state machine for acquisition of all 4 input sensor data..........................40 Figure 3.5: Flowchart for data processing..................................................................................42 Figure 3.6: Basic block diagram of the UART transmitting subsystem.....................................45 Figure 3.7: State flow chart of the UART Transmitter...............................................................47 Figure 3.8: E-R diagram for ADE database................................................................................49 Figure 3.9: Implementation of project…………………………………………………...….....51 Figure 4.1: Sample answer sheet used to collect sensor analog data……..................................52 Figure 4.2: Sample answer sheet used to test the device………………………………...…….57 Figure 4.3: Simulation result of processing………………………………………………........58 Figure 4.4: Basic block of the top level VHDL module.............................................................59 Figure 4.5: RTL schematic of ADC_interface module...............................................................59 Figure 4.6: RTL schematic of data_acquisition module.............................................................60 Figure 4.7: Simulation result of serial transmission………………………………...................60

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TABLE OF CONTENTS

ACKNOWLEDGEMENT..……………………...…………………………………………….……i ABSTRACT………………………………………..………………………………………………....ii LIST OF ABBREVIATIONS……..……………….…………………….……………..………..…iii LIST OF FIGURES……………………….………....……………………………….……….....…iv TABLE OF CONTENTS…...………………………..………………………………….….…..…...v

1. INTRODUCTION 1

1.1BACKGROUND……………………...……….........…………………………...1 1.2ORIGIN OF IDEAS…………...………………………….....…………………...1

1.3OBJECTIVES.......................................................................................................2 1.4 OUTLINE OF THE PROJECT……..……..……………………………….…….…………..2

2. COMPONENTS AND RELATED THEORY 6

2.1 LEDS..……………………………...………………………………...………6 2.2 PHOTOTRANSISTORS…………...……………………………….….….…......6

2.3 ADC……………………………..……………………………….…………...9 2.4 HEX NON INVERTING BUFFER…...……………………………………..…...11 2.5 VHDL ……………………………...……………………….…….…….…...13 2.6 FPGA………………………………..…………………………….…….…...17 2.7 SERIAL INTERFACE…………………......…….…………………..……........21 2.8 DATA STORAGE AND THE GRPAPHICAL USER INTERFACE…..….……….....28

3. PROJECT DESIGN AND IMPLEMENTATION 34 3.1 PROJECT OVERVIEW...…………….…….…………………………….….....34

3.2 FINITE STATE MACHINE…………..……...……………….……............…...35 3.3 INPUT SENSOR MODULE………………….…………………...……….……36 3.4 DATA ACQUISITION IN FPGA………………………………………………..37 3.5 DATA PROCESSING……………………….………………......…..…………40

3.6 COMPUTATION OF CALIBRATION CONSTANTS..…...……………….…..…..43 3.7 RESULT STORAGE AND MANAGEMENT…….……….………………....……45 3.8 DATABASE DESIGN…………………………………..………………...……48 3.9 IMPLEMENTATION OF THE PROJECT…………………..………………........51

4. RESULT AND ANALYSIS 52 4.1 SAMPLE ANSWER SHEET….………………………...………………………………....52 4.2 DATA ANALYSIS.…………………..………………….........…………..………….…….53 4.3 RESULTS…………………………………………………….…………..…..57

4.4 TOOLS AND SOFTWARE USED FOR THE IMPLEMENTATION….……………..58

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4.5 ECONOMIC ANALYSIS……………………………………………………....61

5. EPILOGUE 62

5.1 CONCLUSION...………………………………………......……….………....62 5.2 LIMITATIONS…………………………………………………………….….…………...63 5.3 RECOMMENDATIONS FOR FUTURE ENHANCEMENT………….………….....63

6. BIBLIOGRAPHY 64

ANNEX 65

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1.1 BACKGROUND

Digital electronics is a field where human creativity and knowledge can be

merged to create applications and solutions unimaginable with the aid of traditional

methods. Today with the aid of digital devices it has been possible to think of

efficient, reliable and prompt operations. The advancement in digital and

reconfigurable electronics has proved to bring the life of the purposes which in past

was thought to be impossible. It is fair to say that today the world has been

revolutionized by use of digital electronics.

The basic requirement for creation of any purposeful piece of equipment is the

knowledge and skills acquired. With the related study for the period of four years it is

a good opportunity to implement the knowledge acquired for some meaningful

purpose. Being related to the electronics field HDL, digital designs in FPGA, and the

use of basic electronic components have been a matter of interest. Here, an

“Automatic Digital Examiner” is designed as an optical mark reader, which is

supposed to find its application in real field.

1.2 ORIGIN OF IDEAS

Objective question sets have nowadays become a standard practice in order to

select students and assess their performances. These questions are usually provided

with multiple choice answer sheets where the students can choose the correct answer

by making a mark (e.g. a dark spot). Objective answer sheet checking is a common

problem, yet when done manually it’s a tricky task, considering the accuracy

required. Because the human errors are often intolerable in this matter, computer

checking is being increasingly used in most institutions. Besides as the number of

answer sheets increases human checking will be tedious, time-consuming and so

proves to be an efficient system. The computer usually scans the answer sheet by a

scanner, and then feeds the data to image processing software to decode the marks

made by examinees. This mechanism works fairly well and is usually reliable. The

1. INTRODUCTION

2

drawbacks come from the slow speed of scanning and image processing using a

general-purpose computer. The overall cost of such system can sometimes become

overwhelmingly large if we add up cost of all the software needed for its development

and use.

An alternative approach is to develop a dedicated hardware module that can

achieve the same function in a simpler way. Equipped with knowledge of electronics,

software and electronics components, we opted to go for the design of our own

“Automatic Digital Examiner” which would fulfill the above desired purpose.

1.3 OBJECTIVES

1. To conceive an answer sheets checking machine as a completely

independent hardware module in order to develop a cheaper, faster alternative for PC

systems used for the same purpose.

2. To dig into the aspects of digital design using HDL and FPGA

1.4 OUTLINE OF THE PROJECT

On the functional basis the project can be divided into 4 parts.

1. Input

2. ADC and data acquisition in FPGA

3. Data processing

4. Result storage and management.

3

The input section is a board which consists of the array of LEDs and optical

sensors. The optical sensors are the photo transistors which detects the light reflected

from the answer sheets. Here, the answer sheet is placed directly above the sensors

when the device is being used. The input section produces the different analog

voltages from the photo transistors which are given to the FPGA board.

The analog voltage form the input section is digitized and multiplexed by the

8 channel multiplexer using 0808CCN ADC and given to the FPGA board.

Here, Spartan 3 FPGA board is used. The board is interfaced with the ADC

using VHDL codes.

For the data processing three basic operations are done:

• Answer sheet design

• Decision making logics

• Calibration of sensor output levels

In answer sheet design a desired pattern suitable is designed as below:

Fig 1.1 Answer sheet design

In decision making various logics are made to detect the desired mark.

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For the calibration of sensor output levels the environmental factors are

considered, real time output levels are defined and the threshold values are defined.

In result storage and management RS232 interface is done between the FPGA

and the computer. Finally, the operation database entry, GUI and display is carried.

The basic block diagram for the outline of the project is shown in Fig1.1.

The above mentioned overview is discussed in detail later in the PROJECT

DESIGN AND IMPLEMENTATION part of the report.

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Answer sheet

Control logic

Computer

Display

FPGA

Digitizing MUX

Input optical scanner

Serial interface

BASIC BLOCK DIAGRAM

Fig 1.2 Basic Block Diagram of project

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2.1 LEDs

LEDs are solid state p-n junction devices which emit light when forward

biased. An LED is a Light Emitting Diode, a generic term. Unlike incandescent lamps

which emit light over a very broad range of wavelengths, LEDs emit light over such a

narrow bandwidth that they appear to be emitting a single “color”. Their small size,

long operating lifetimes, low power consumption, compatibility with solid state drive

circuitry, and relatively low cost, make LEDs the preferred light source in many

applications.

LEDs are made from a wide range of semiconductor materials. The emitted

peak wavelength depends on the semiconductor material visible or near infrared part

of the spectrum.

The P-N junction is formed by doping one region of the material with donor

atoms and the adjacent region with acceptor atoms. Like all P-N junction devices,

LEDs exhibit the familiar diode current-voltage characteristics. LEDs emit light only

when they are biased in the forward direction. Under forward biased conditions

carriers are given enough energy to overcome the potential barrier existing at the

junction. After crossing the junction these carriers will recombine. A percentage of

the carriers will recombine by a radiative process in which the hole-electron

recombination energy is released as a photon of light. The remaining carriers

recombine by a non radiative process and give up their energy in the form of heat.

The amount of light generated, or power output of the LED, varies almost linearly

with forward current. Doubling the forward current approximately doubles the power

output.

2.2 PHOTOTRANSISTORS

Phototransistors are photodiode-amplifier combinations integrated within a

single silicon chip. These combinations are put together in order to overcome the

major limitation of photodiodes: unity gain.

2. COMPONENTS AND RELATED THEORY

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The phototransistor can be viewed as a photodiode whose output photocurrent

is fed into the base of a conventional small signal transistor. While not required for

the operation of the device as a photo detector, a base connection is often provided

allowing the designers the option of using base current to bias the transistor. The

typical gain of a phototransistor can range from 100 to over 1500.

Figure below shows an equivalent phototransistor circuit:

Characteristics of phototransistors:

FUNDAMENTAL PHOTOTRANSISTOR CIRCUITS

Figures 2.2 and 2.3 show the fundamental phototransistor circuits. The circuit

shown in Figure 2.2 (A) is a common-emitter amplifier. Light input at the base causes

the output (VOUT) to decrease from high to low. The circuit shown in Figure 2.2 (B)

is a common-collector amplifier with an output (VOUT) increasing from low to high

in response to light input. For the circuits in Figure 2.2 to operate in the switching

mode, the load resistor (RL) should be set in relation with the collector current(IC) as

VCC < Rl * Ic

Fig 2.1 Phototransistor equivalent circuit

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The circuit in shown Figure 2.3 (A) uses a phototransistor with a base

terminal. A RBE resistor connected between the base and emitter alleviates the

influence of a dark current when operating at a high temperature. The circuit shown in

Figure 2.3 (B) features a cascade connection of the grounded-base transistor (Tr1) so

that the phototransistor is virtually less loaded, thereby improving the response.

Fig 2.2 Fundamental Phototransistor Circuit (I)

Fig 2.3 Fundamental Phototransistor Circuit (I I)

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2.3 ADC

ADC used in the project is ADC0808CCN.

Functional Description:

The device contains an 8-channel single-ended analog signal multiplexer. A

particular input channel is selected by using the address decoder. Table A shows the

input states for the address lines to select any channel. The address is latched into the

decoder on the low-to-high transition of the address latch enable signal.

The Converter

The heart of this single chip data acquisition system is its 8-bit analog-to-

digital converter. The converter is designed to give fast, accurate, and repeatable

conversions over a wide range of temperatures. The converter is partitioned into 3

major sections: the 256R ladder network, the successive approximation register, and

the comparator. The converter’s digital outputs are positive true.

The 256R ladder network approach was chosen over the conventional R/2R

ladder because of its inherent monotonicity, which guarantees no missing digital

codes. Monotonicity is particularly important in closed loop feedback control systems.

A non-monotonic relationship can cause oscillations that will be catastrophic for the

system. Additionally, the 256R network does not cause load variations on the

reference voltage

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Pin out diagram:

Timing diagram:

Fig 2.4 Pin out of ADC0808CCN

Fig 2.5 Timing diagram of ADC 0808CCN

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The operation of ADC0808 can be best described using the timing diagram

shown above. The timing diagram illustrates required time delays and sequence of

signals. Although, the ADC is built for easy interface with 8 bit microcontrollers such

as 8051, it can also be interfaced with FPGA by properly investigating the above

timing diagram.

2.4 HEX NON INVERTING BUFFERS

DESCRIPTION

The HEF4050B provides six non-inverting buffers with high current output

capability suitable for driving TTL or high capacitive loads. Since input voltages in

excess of the buffers’ supply voltage are permitted, the buffers may also be used to

convert logic levels of up to 15 V to standard TTL levels. Their guaranteed fan-out

into common bipolar logic elements is shown in the table below.

Fig 2.6 Functional Diagram of buffer HEF4050B

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Logic diagram:

Pinning Diagram:

APPLICATION INFORMATION

Some examples of applications for the HEF4050B are:

• TTL to LVCMOS converter

• LOCMOS to DTL/TTL converter

• HIGH sink current for driving 2 TTL loads

• HIGH-to-LOW level logic conversion

Among these applications, the first one, i.e. TTL to LVCMOS converter is

most relevant to the project as described in the project implementation part.

Fig 2.7 Logic diagram one gate

Fig 2.8 Pin out diagram of buffer

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2.4 VHDL

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware

Description language. The VHSIC Hardware Description Language is an industry

standard language used to describe hardware from the abstract to the concrete level.

VHDL resulted from work done in the ’70s and early ’80s by the U.S. Department of

Defense. A fundamental motivation to use VHDL is that VHDL is that VHDL is a

standard, technology independent language, and is therefore portable and reusable.

The other widely used hardware description languages are Verilog and ABEL

(Advanced Boolean Equation Language). ABEL is specially designed for

Programmable Logic Devices (PLD) and less powerful than the other two languages.

A hardware description language is inherently parallel, i.e. commands, which

correspond to logic gates, are executed in parallel, as soon as a new input arrives. A

HDL program mimics the behavior of a physical, usually digital, system. It also

allows incorporation of timing specification (gate delays) as well as to describe a

system as an interconnection of different components.

LEVEL OF REPRESENTATION AND ABSTRACTION

A digital system can be represented at different levels of abstraction. The

different levels of abstraction are Behavioral, Structural and Physical.

Behavioral level is the highest level of abstraction and describes a system in

terms of what it does rather than in terms of its components and interconnection

between them. This could be a Boolean expression or more abstract description.

Structural level describes a system as a collection of gates and components

that are interconnected to perform a desired function. It is a representation that is

usually closer to the physical realization of the system.

Physical level describes more about the circuit connections of the

components.

14

VHDL allows one to describe a digital system at the structural or the

behavioral level. The behavioral level can be further divided into two kinds: Dataflow

and Algorithmic.

The dataflow representation describes how data moves through the system.

This is done in terms of data flow between registers. The data flow model makes use

of concurrent statement that are executed in parallel as soon as data arrives in the

input. On the other hand, sequential statements are executed in sequence that they are

specified. VHDL allows both concurrent and sequential signal assignments.

VHDL terms:

Entity. All designs are expressed in terms of entities. An entity is the most

basic building block in a design. The uppermost level of the design is the top-level

entity. If the design is hierarchical, then the top-level description will have lower-

level descriptions contained in it. These lower-level descriptions will be lower-level

entities contained in the top-level entity description.

Architecture. All entities that can be simulated have an architecture

description. The architecture describes the behavior of the entity. A single entity can

have multiple architectures. One architecture might be behavioral while another

might be a structural description of the design.

Configuration. A configuration statement is used to bind a component

instance to an entity-architecture pair. A configuration can be considered like a parts

list for a design. It describes which behavior to use for each entity, much like a parts

list describes which part to use for each part in the design.

Driver. This is a source on a signal. If a signal is driven by two sources, then

when both sources are active, the signal will have two drivers.

15

Bus. The term “bus” usually brings to mind a group of signals or a particular

method of communication used in the design of hardware. In VHDL, a bus is a

special kind of signal that may have its drivers turned off.

Attribute. An attribute is data that are attached to VHDL objects or predefined

data about VHDL objects. Examples are the current drive capability of a buffer or the

maximum operating temperature of the device.

Process. A process is the basic unit of execution in VHDL. All operations that

are performed in a simulation of a VHDL description are broken into single or

multiple processes.

Basic structure of VHDL file:

A digital system in VHDL consists of a design entity that can contain other

entities that are then considered components of the top-level entity. Each entity is

modeled by an entity declaration and an architecture body. One can consider the

entity declaration as the interface to the outside world that defines the input and

output signals, while the architectural body contains the description of the entity and

is composed of interconnected entities, processes and components, all operating

concurrently, as shown in figure below:

Figure 2.9 VHDL entity with an entity declaration and an architectural description

VHDL Entity

INTERFACE (Entity declaration)

BODY (Architecture) Sequential Combinational processes

Ports

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VHDL uses reserved keywords that cannot be used as signal names or identifiers. Keywords

and user-defined identifiers are case sensitive. Lines with comments start with two adjacent

hyphens and will be ignored by the compiler. VHDL also ignores line breaks and extra

spaces. VHDL is a strong type language which implies that one has always to declare the

type of every object that can have a value, such as signals, constants and variables.

Benefits of using VHDL

The benefits of using VHDL can be listed as below:

• Executable specification

• Functionality separated from implementation

• Simulate early and fast

• Explore design alternatives

• Get feedback (Produce better designs)

• Automatic synthesis and test generation

• Increase productivity

• Technology and tool independence (though FPGA features may be

unexploited)

• Portable design data

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2.5 FPGA

A field-programmable gate array (FPGA) is a semiconductor device that

can be configured by the customer or designer after manufacturing—hence the name

"field-programmable". FPGAs are programmed using a logic circuit diagram or a

source code in a hardware description language (HDL) to specify how the chip will

work. They can be used to implement any logical function that an application-specific

integrated circuit (ASIC) could perform, but the ability to update the functionality

after shipping offers advantages for many applications

Historically, FPGAs have been slower, less energy efficient and generally

achieved less functionality than their fixed ASIC counterparts. A combination of

volume, fabrication improvements, research and development, and the I/O

capabilities of new supercomputers have largely closed the performance gap between

ASICs and FPGAs.

Advantages include a shorter time to market, ability to re-program in the field

to fix bugs, and lower non-recurring engineering costs. Vendors can also take a

middle road by developing their hardware on ordinary FPGAs, but manufacture their

final version so it can no longer be modified after the design has been committed.

FPGA are available with many logic families such as TTL, CMOS, I2L, etc.

Applications of FPGAs include digital signal processing, software-defined radio,

aerospace and defense systems, ASIC prototyping, medical imaging, computer vision,

speech recognition, cryptography, bioinformatics, computer hardware emulation and

a growing range of other areas.

http://en.wikipedia.org/wiki/Semiconductor

http://en.wikipedia.org/wiki/Field-programmable

http://en.wikipedia.org/wiki/Circuit_diagram

http://en.wikipedia.org/wiki/Source_code

http://en.wikipedia.org/wiki/Hardware_description_language

http://en.wikipedia.org/wiki/Application-specific_integrated_circuit


http://en.wikipedia.org/wiki/ASIC

http://en.wikipedia.org/wiki/Time_to_market

http://en.wikipedia.org/wiki/Non-recurring_engineering

http://en.wikipedia.org/wiki/Digital_signal_processing

http://en.wikipedia.org/wiki/Software-defined_radio

http://en.wikipedia.org/wiki/Aerospace

http://en.wikipedia.org/wiki/Defense_(military)


http://en.wikipedia.org/wiki/Medical_imaging

http://en.wikipedia.org/wiki/Computer_vision

http://en.wikipedia.org/wiki/Speech_recognition

http://en.wikipedia.org/wiki/Cryptography

http://en.wikipedia.org/wiki/Emulator

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Architecture

The most common FPGA architecture consists of an array of configurable

logic blocks (CLBs), I/O pads, and routing channels. Generally, all the routing

channels have the same width (number of wires). Multiple I/O pads may fit into the

height of one row or the width of one column in the array.

An application circuit must be mapped into an FPGA with adequate resources.

While the number of CLBs and I/Os required are easily determined from the design,

the amount of routing tracks needed may vary considerably even among designs with

the same amount of logic. (For example, a crossbar switch requires much more

routing than a systolic array with the same gate count.) Since unused routing tracks

increase the cost (and decrease the performance) of the part without providing any

benefit, FPGA manufacturers try to provide just enough tracks so that most designs

that will fit in terms of LUTs and IOs can be routed. This is determined by estimates

such as those derived from Rent's rule or by experiments with existing designs.

A classic FPGA logic block consists of a 4-input lookup table (LUT), and a

flip-flop, as shown below. In recent years, manufacturers have started moving to 6-

input LUTs in their high performance parts, claiming increased performance.

Fig 2.10 Typical logic block of FPGA

There is only one output, which can be either the registered or the unregistered

LUT output. The logic block has four inputs for the LUT and a clock input. Since

clock signals (and often other high-fan-out signals) are normally routed via special-

purpose dedicated routing networks in commercial FPGAs, they and other signals are

separately managed.

http://en.wikipedia.org/wiki/Crossbar_switch

http://en.wikipedia.org/wiki/Systolic_array

http://en.wikipedia.org/wiki/Rent%27s_rule

http://en.wikipedia.org/wiki/Lookup_table

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

http://en.wikipedia.org/wiki/File:Logic_block2.svg

19

For this example architecture, the locations of the FPGA logic block pins are

shown below.

Each input is accessible from one side of the logic block, while the output pin

can connect to routing wires in both the channel to the right and the channel below

the logic block.

Each logic block output pin can connect to any of the wiring segments in the

channels adjacent to it.

Similarly, an I/O pad can connect to any one of the wiring segments in the

channel adjacent to it. For example, an I/O pad at the top of the chip can connect to

any of the W wires (where W is the channel width) in the horizontal channel

immediately below it.

Generally, the FPGA routing is unsegmented. That is, each wiring segment

spans only one logic block before it terminates in a switch box. By turning on some

of the programmable switches within a switch box, longer paths can be constructed.

For higher speed interconnect, some FPGA architectures use longer routing lines that

span multiple logic blocks.

Whenever a vertical and a horizontal channel intersect, there is a switch box.

In this architecture, when a wire enters a switch box, there are three programmable

switches that allow it to connect to three other wires in adjacent channel segments.

The pattern, or topology, of switches used in this architecture is the planar or domain-

based switch box topology. In this switch box topology, a wire in track number one

connects only to wires in track number one in adjacent channel segments, wires in

http://en.wikipedia.org/wiki/File:Logic_block_pins.svg

20

track number 2 connect only to other wires in track number 2 and so on. The figure

below illustrates the connections in a switch box.

Switch box topology

Modern FPGA families expand upon the above capabilities to include higher

level functionality fixed into the silicon. Having these common functions embedded

into the silicon reduces the area required and gives those functions increased speed

compared to building them from primitives. Examples of these include multipliers,

generic DSP blocks, embedded processors, high speed IO logic and embedded

memories.

Fig 2.11 Switchbox connection

http://en.wikipedia.org/wiki/File:Switch_box.svg

21

FPGA design and programming

To define the behavior of the FPGA it is required to use a Hardware

Description Language or a schematic designed using an electronic design automation

tool. Either of these, when compiled, will generate a net list, that can be mapped to

the actual FPGA architecture. When done the binary file generated is used to

(re)configure the FPGA device. Common HDL’s are VHDL and Verilog.

2.5 Serial interface

Serial communication

Serial communication is the most common low level protocol for

communicating two or more devices. The sending and receiving bytes of information

takes place in serial fashion as the name suggests. These bytes are transmitted using

either a binary (numerical) format or a text format.

RS-232 Serial Ports in Spartan-3E FPGA board

Two RS-232 serial ports: a female DB9 DCE connector and a male DB9 DTE

connector are present in the Spartan-3E FPGA Starter Kit board. The DCE-style port

connects directly to the serial port connector available on most personal computers

and workstations via a standard straight-through serial cable. The null modem, gender

changers or the crossover cables are not required for the interface. The DTE-style

connector can be used to control other RS-232 peripherals such as modems or

printers, or perform simple loopback testing with the DCE connector. The figure 2.14

below shows the serial ports and their configuration in the Starter Kit.

22

Characteristics of RS232

• Uses a 9 pins connector "DB-9" (older PCs use 25 pins "DB-

25").

• Allows bidirectional full-duplex communication (the PC can

send and receive data at the same time).

• Can communicate at a maximum speed of roughly 10KBytes/s.

Rs232 Standards

Communication in the RS232 standard is an asynchronous serial

communication method. The word serial means, that the information is sent one bit at

a time. Asynchronous tells us that the information is not sent in predefined time slots.

Data transfer can start at any given time and it is the task of the receiver to detect

when a message starts and ends. With RS232, the line voltage level can have two

states. The on state is known as mark, the off state as space. When the line is idle, it is

kept in the mark state.

Start bit

RS232 defines an asynchronous type of communication. This means, that

sending of a data word can start on each moment. If starting at each moment is

possible, this can pose some problems for the receiver to know which the first bit to

receive is. To overcome this, each data word is started with an attention bit. This

attention bit, also known as the start bit is always identified in the space line level.

Because the line is in mark state when idle, the start bit is easily recognized by the

receiver.

Data bits

Directly following the start bit, the data bits are sent. A bit value 1 causes the

line to go in mark state; the bit value 0 is represented by a space. The least significant

bit is always the first bit sent.

23

Parity bit

For the error detecting purposes, it is possible to add an extra bit to the data

word automatically. The transmitter calculates the value of the bit depending on the

information sent. The receiver performs the same calculation and checks if the actual

parity bit value corresponds to the calculated value.

Stop bits

Consider that the receiver has missed the start bit because of noise in the

transmission line. It started on the first following data bit with a space value. This

causes garbled data to reach the receiver. A framing mechanism must be present to

resynchronize the communication. Framing means, that all the data bits is and parity

are contained in a frame of start and stop bits. This period of time lying between the

start and stop bit is a constant defined by the baud rate and number of data and parity

bits. The start bit has always space value, the stop bit always a mark value. The stop

bit identifying the end of a data frame can have different lengths. Actually, it is not a

real bit but a minimum period of time the line must be idle (mark state) at the end of

each word. On PC’s this period can have three lengths: the time equal to 1,1.5 or 2

bits is only used with data words of 5 bits length and 2 only for longer words. A stop

bit length of 1 bit is possible for all data word size

Serial Data Format

The serial data format includes one start bit, data bits, parity bits and stop bits.

The diagram below illustrates the serial data format.

Fig 2.12 Serial Data Format

START BIT DATA BITS PARITY BIT STOP BIT

24

Voltages

The signal level of the RS232 pins can have two states. A high bit, or mark

state is identified by a negative voltage and a low bit or space state uses a positive

value as shown in the table:

Table RS232 Voltage levels

Level Transmitter

capable V

Receiver capable

V

Space state (0) +5………+15 +3………….+25

Mark state (1) -5…….....-15 -3…………..-25

Undefined - -3…………..+3

Pin configuration

DB9:

Fig 2.13 RS232 DB9 pin out

25

Pin

No.

Name Dir Notes/Description

1 DCD IN Data Carrier Detect. Raised by DCE when

modem synchronized.

2 RD IN Receive Data (a.k.a RxD, Rx). Arriving data

from DCE.

3 TD OUT Transmit Data (a.k.a TxD, Tx). Sending data

from DTE.

4 DTR OUT Data Terminal Ready. Raised by DTE when

powered on. In auto-answer mode raised only when

RI arrives from DCE.

5 SGND - Ground

6 DSR IN Data Set Ready. Raised by DCE to indicate

ready.

7 RTS OUT Request To Send. Raised by DTE when it

wishes to send. Expects CTS from DCE.

8 CTS IN Clear To Send. Raised by DCE in response to

RTS from DTE.

9 RI IN Ring Indicator. Set when incoming ring

detected - used for auto-answer application. DTE

raised DTR to answer.

26

Here, serial interface RS232 is used to interface between computer and FPGA board.

Figure shows the connection between the FPGA and the two DB9 connectors. The

FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim

device, which in turn, converts the logic value to the appropriate RS-232 voltage

level. Likewise, the Maxim device converts the RS-232 serial input data to LVTTL

levels for the FPGA. A series resistor between the Maxim output pin and the FPGA’s

RXD pin protects against accidental logic conflicts. Hardware flow control is not

supported on the connector. The port’s DCD, DTR, and DSR (pin 1,4,6) signals

connect together, as shown in Figure . Similarly, the port’s RTS and CTS (pin 7and 8)

signals connect together. Ring indicator (pin 9) is not used. RXD, TXD and GND (pin

2,3 and 5) are dedicated signal lines for data receiving, sending and signal ground.

Asynchronous communication

This interface uses an "asynchronous" protocol. That means that no clock

signal is transmitted along the data. The receiver has to have a way to "time" itself to

the incoming data bits.

In the case of RS-232, that's done this way:

1. Both side of the cable agree in advance on the communication

parameters (speed, format...). That's done manually before communication

starts.

2. The transmitter sends a "1" when and as long as the line is idle.

3. The transmitter sends a "start" (a "0") before each byte

transmitted, so that the receiver can figure out that data is coming.

4. After the "start", data comes in the agreed speed and format, so

the receiver can interpret it.

5. The transmitter sends a "stop" (a "1") after each data byte.

27

Let's see how the byte 0x55 when transmitted looks:

Byte 0x55 is 01010101 in binary.

But since it is transmitted LSB (bit-0) first, the line toggles like that: 1-0-1-0-1-0-1-0.

Here's another example:

Here the data is 0xC4, the bits transitions are harder to see. That illustrates

how important it is for the receiver to know at which speed the data is sent.

28

2.8 DATA STORAGE AND THE GRAPHICAL USER INTERFACE

Database Management System (DBMS)

A database is a structured collection of records or data that is stored in a computer

system. The structure is achieved by organizing the data according to a database

model. The model in most common use today is the relational model. Other models

such as the hierarchical model and the network model use a more explicit

representation of relationships.

A database is a collection of information that is organized so that it can easily be

accessed, managed, and updated.

A DBMS is a set of software programs that controls the organization, storage,

management, and retrieval of data in a database. DBMS are categorized according to

their data structures or types. It is a set of prewritten programs that are used to store,

update and retrieve a Database. The DBMS accepts requests for data from the

application program and instructs the operating system to transfer the appropriate

data. When a DBMS is used, information systems can be changed much more easily.

New categories of data can be added to the database without disruption to the existing

system.

There is no separate and dedicated DBMS, it is just simple and integrated with the

GUI as the part of the project. The reason behind the inclusion of the DBMS is for the

optimization of the usability of data in other application and analysis.

Relational Database Model

A relational database is a database that group data using common attributes found

in the data set. The resulting "clumps" of organized data are much easier for people to

understand.

A relation is defined as a set of tuples that have the same attributes. A tuple

usually represents an object and information about that object. Objects are typically

physical objects or concepts. A relation is usually described as a table, which is

organized into rows and columns. All the data referenced by an attribute are in the

same domain and conform to the same constraints.

29

Fig 2.14: Figure showing basic terminology used in the relational database model.

MySQL:

MySQL is a multithreaded, multi-user SQL database management system.

MySQL is a relational database management system (RDBMS). MySQL is popular

for web applications and acts as the database component of the LAMP, BAMP,

MAMP, SAMP, and WAMP platforms(Linux/BSD/Mac/(Open)Solaris/Windows-

Apache-MySQL-PHP/Perl/Python), and for open-source bug tracking tools like

Bugzilla. Libraries for accessing MySQL databases are available in all major

programming languages with language-specific APIs. In addition, an ODBC interface

called MyODBC allows additional programming languages that support the ODBC

interface to communicate with a MySQL database, such as ASP or ColdFusion. The

MySQL server and official libraries are mostly implemented in ANSI C/ANSI C++.

Structured Query Language (SQL)

SQL is a programming language for querying and modifying data and managing

databases. SQL allows the retrieval, insertion, updating, and deletion of data. A

database management system also includes management and administrative

functions. Instead of using command-line interface (SQL/CLI) that allows for the

entry and execution of the language commands, here it is used as an application

programming interface (API) intended for access from a graphical user interface

(GUI).

30

Language elements

The SQL language is sub-divided into several language elements, including:

• Clauses, which are in some cases optional, constituent components of

statements and queries.

• Predicates which specify conditions that can be evaluated to SQL

three-valued logic (3VL) Boolean truth values and which are used to

limit the effects of statements and queries, or to change program flow.

• Queries which retrieve data based on specific criteria.

• Statements which may have a persistent effect on schemas and data, or

which may control transactions, program flow, connections, sessions,

or diagnostics.

• SQL statements also include the semicolon (";") statement terminator.

Though not required on every platform, it is defined as a standard part

of the SQL grammar.

Queries

The most common operation in SQL databases is the query, which is performed

with the declarative SELECT keyword. SELECT retrieves data from a specified

table, multiple related tables in a database or the result of an expression.

An SQL query includes a list of columns to be included in the final result

immediately following the SELECT keyword. An asterisk ("*") can also be used as a

"wildcard" indicator to specify that all available columns of a table (or multiple

tables) are to be returned. SELECT is the most complex statement in SQL, with

several optional keywords and clauses, including:

• The FROM clause which indicates the source table or tables from

which the data is to be retrieved. The FROM clause can include

optional JOIN clauses to join related tables to one another based on

user-specified criteria.

• The WHERE clause includes a comparison predicate, which is used to

restrict the number of rows returned by the query. The WHERE clause

is applied before the GROUP BY clause. The WHERE clause

eliminates all rows from the result set where the comparison predicate

does not evaluate to True.

31

• The GROUP BY clause is used to combine, or group, rows with

related values into elements of a smaller set of rows. GROUP BY is

often used in conjunction with SQL aggregate functions or to

eliminate duplicate rows from a result set.

• The HAVING clause includes a comparison predicate used to

eliminate rows after the GROUP BY clause is applied to the result

set. Because it acts on the results of the GROUP BY clause, aggregate

functions can be used in the HAVING clause predicate.

• The ORDER BY clause is used to identify which columns are used to

sort the resulting data, and in which order they should be sorted

(options are ascending or descending). The order of rows returned by

an SQL query is never guaranteed unless an ORDER BY clause is

specified.

Data manipulation

First, there are the standard Data Manipulation Language (DML) elements. DML

is the subset of the language used to add, update and delete data:

INSERT is used to add rows (formally tuples) to an existing table

eg: INSERT INTO My_table (field1, field2, field3) VALUES ('test', 'N',

NULL);

UPDATE is used to modify the values of a set of existing table rows.

eg: UPDATE My_table SET field1 = 'updated value' WHERE field2 = 'N';

DELETE removes zero or more existing rows from a table.

eg: DELETE FROM My_table WHERE field2 = 'N';

MERGE is used to combine the data of multiple tables. It is something

of a combination of the INSERT and UPDATE elements. It is defined

in the SQL:2003 standard; prior to that, some databases provided

similar functionality via different syntax, sometimes called an "upsert"

Graphical User Interface (GUI)

A graphical user interface (GUI) is a type of user interface which allows people to

interact with electronic devices such as computers; hand-held devices such as MP3

Players, Portable Media Players or Gaming devices; household appliances and office

32

equipment. A GUI offers graphical icons, and visual indicators, as opposed to text-

based interfaces, typed command labels or text navigation to fully represent the

information and actions available to a user. The actions are usually performed

through direct manipulation of the graphical elements.

Designing the visual composition and temporal behavior of GUI is an important

part of digital system designing. Its goal is to enhance the efficiency and ease of use

for the underlying logical design of a stored program, a design discipline known as

usability. Techniques of user-centered design are used to ensure that the visual

language introduced in the design is well tailored to the tasks it must perform.

Typically, the user interacts with information by manipulating visual widgets that

allow for interactions appropriate to the kind of data they hold. The widgets of a well-

designed interface are selected to support the actions necessary to achieve the goals of

the user.

MATLAB and the GUI toolbox

MATLAB is a numerical computing environment and programming language.

Maintained by The Math Works, MATLAB allows easy matrix manipulation,

plotting of functions and data, implementation of algorithms, creation of user

interfaces, and interfacing with programs in other languages. Although it is numeric

only, an optional toolbox uses the MuPAD symbolic engine, allowing access to

computer algebra capabilities. An additional package, Simulink, adds graphical

multidomain simulation and Model-Based Design for dynamic and embedded

systems.

MATLAB provides the genuine environment for the GUI development. The

creation of the user friendly GUI includes the following steps.

Designing the GUI.

Designing the GUI before actually creating it in GUIDE.

Laying Out the GUI.

Using the GUIDE Layout Editor to arrange the GUI

components, such as push buttons, pop-up menus, and axes.

Setting Properties for GUI Components.

Setting properties for each GUI component.

Programming the GUI

Using the M-file editor to program the GUI.

Saving and Running a GUI

33

Saving and running the GUI from the Layout Editor.

It is easy to use MATLAB for creation of GUI. User are provided with the different

components like pushbutton, edit text, static text, popup menu, panel and so on in the

layout editor. We can layout the component simply dragging and dropping according

to our required design. After saving the design the .fig as well as .m file created. In

the M file there are no of callback routine programming in appropriate callback the

desired output can be observed with different component event handles.

34

Computer

Display

FPGA

Digitizing

MUX

Input optical sensors

Serial interface

Answer sheet

Control logic

3.1 PROJECT OVERVIEW

To get an overview of the project design, we will first consider the intended

method of use of the project as a device. The project has been realized as a standalone

device which does all the computation and processing on the hardware, i.e. on the

Spartan 3E FPGA. Although, storage memory elements such as ROMs can be realized

in the hardware, for other purposes such as data analysis, printing, data

documentation, it is convenient to store the final results in a computer. For this

purpose, the serial interface is used to transmit result outputs to the computer. It is

worth to be noted that the computer is not involved in any kind of data processing,

whatsoever, in the implementation of the project.

The design of project is done on the basis of the simplified block diagram as

presented in the proposal. A slight modification of the block diagram is shown here

again.

Fig 3.1 Basic block diagram of the project

3 PROJECT DESIGN AND IMPLEMENTATION

35

3.2 FINITE STATE MACHINES

As implied by the block diagram, the project is completely realized in hardware,

i.e. the final product of the project wholly uses either analog or digital circuits rather

than computer programs even in realization of complicated algorithms. Apart from the

input sensor module and its interface with FPGA, the other parts of the project are

realized using digital circuits. The digital circuits are implemented by synthesis of

VHDL codes in FPGA. For this VHDL behavioral modeling has been used. The

behavioral modeling is a powerful tool in VHDL that can be used to synthesize digital

circuits by only describing its behavior. All of the codes are developed using Finite

State Machine (FSM) and Algorithmic State Machine (ASM) approach. Several

FSMs are used for different levels of operation forming hierarchies of FSMs. The

overall FSM description of the project can be described using the following simplified

FSM.

Fig 3.2 Simplified FSM for project implementation

Acquire new

digitized data

Process data

Take decision

Display result

Send result to PC

36

In the design of the project, the project has been subdivided into four parts:

1. Input sensor module

2. Data acquisition in FPGA

3. Data processing

4. Result storage and management in PC

These parts are explained in detail below.

3.3 INPUT SENSOR MODULE

The input module is an analog device that uses LED and phototransistor

combination to sense light and dark regions. The light from the LED is reflected to the

phototransistor by the answer sheet paper that is placed just above the input sensor

module. When there is no mark in the paper, large part of the light is reflected and

when there is a dark mark, smaller part of light is reflected. This produces different

voltages when such scan spot signals are used to scan the answer sheet. Different

marks will produce different voltages depending upon the darkness of marks and the

individual characteristics of the input sensors. The figure A shows the four input

sensors that are separated by a fixed distance.

The phototransistors in the sensor module have a specific region where they

operate giving best differences between light and dark paper regions. This is because

transistor responses are nonlinear and they have different regions, such as cutoff

region, saturation region and active region, each showing different behavior. For this

three important factors were varied: RC (collector series resistance of phototransistor),

RD (LED series resistance) and the angle at which the LEDs and phototransistors are

inclined.

These parameters were chosen by hit and trial method after a lot of testing and

analysis of the input module responses. The values are: RC = 56k, RD = 1k and angle

between phototransistor/LED and horizontal around 45o. With these values fixed, the

analog data for different mark types in an answer sheet were tabulated. The analysis

of these data was useful to determine some threshold values that have been used in

data processing to take decision on the final result of processing.

37

Apart from these parameters, there are other uncontrollable parameters that affect

the performance of the input module. These parameters include temperature, minute

variation of paper height, vibrations, ambient light, etc. Some of these factors can

seriously hamper the operation of input module by changing the region on which the

phototransistor operates on a fixed condition such as white paper. Therefore careful

considerations of these factors have to be done before the project as a device is used

on real situations.

3.4 DATA ACQUISITION IN FPGA

Before the data from input sensor module can be examined and processed, they

have to be converted to digital form. Although, the Spartan 3E Starter Kit includes an

Analog to Digital Converter that has an easier interface with Spartan 3E FPGA, this

includes only two analog channels and therefore doesn’t fit our purpose. To digitize

analog voltages from all four optical sensors, we need an ADC with at least 4 analog

channels. Thus, ADC0808CCN that is commonly available in the market was chosen

because of its 8 analog input channels. ADC0808CCN is built to provide easy

interfacing with 8 bit microcontrollers such as 8051 which have interrupts and 8 bit

I/O ports.

Need of Buffers:

Interfacing this ADC with FPGA is slightly more complicated compared with 8

bit microcontrollers. The first major problem is that ADC0808CCN has TTL I/O

standard that isn’t completely compatible with the LVCMOS33 I/O standard Spartan

3E uses. The logic high output from ADC 0808 is about 4.75 V but the same for

LVCMOS33 I/O is 3.3 V. It is mentioned in literatures that trying to force TTL logic

high into Spartan 3E I/O will result in high currents to flow through clamp diodes of

I/O protection circuit that will be greater than the specified 10 mA margin. Finally

this will render the I/O ports of FPGA unusable as the diodes are burned out. To

tackle this problem open collector buffers HEF4050BP has been used. This IC

effectively converts the TTL high logic output of about 4.75 V to VDD (here taken as

3.3V), thus connecting the two different I/O standards at the cost of small delays.

Since the system works in comparatively small frequency of about 1 MHz, the added

delay is not a threat to the system performance. Similarly, 74HC245 buffer IC can

effectively convert the input LVCMOS33 standard logic into TTL standard. Although

38

initially used in the circuit, it was later found unnecessary and taken out. The figure

below shows the actual circuit used to implement data acquisition in FPGA.

As these small problems were solved, the task of interfacing ADC 0808CCN with

Spartan 3E FPGA was completed easily by using State Machine design approach. The

acquisition of an 8 bit data corresponding to digitization of single channel of analog

input can be explained using the state diagram shown below.

39

Start

Address option

ALE ’1’

ALE ’1’ SC ’1’

ALE ’0’ SC ’1’

ALE ’0’

SC ’0’

EOC ’0’

EOC ’1’

OE ’1’

reg data option next_ address

T

F

F

T

Figure3.3 ASM for interfacing ADC0808 with FPGA

40

Similarly, the acquisition of data for all 4 analog inputs is performed using another

State Machine in the upper hierarchy as shown below.

Figure3.4 Simplified state machine for acquisition of all 4 input sensor data

3.5 DATA PROCESSING

The data processing is complex in implementation because of which it can be best

described by an algorithm and ASM.

Algorithm:

Step 1: Check if the device is in calibration mode. If not in calibration

mode, jump to Step 3.

Step 2: Calibrate for dark readings if input slide switches are set “01”.

If input slide switches are set “10”, calibrate for white sheet of

paper. Jump to Step 9.

Step 3: Adjust scanned readings using calibration constants computed

before.

Take Sensor I

data

Take Sensor II

data

Take Sensor III

data

Take Sensor IV

data

Send data to

processing module

Wait until next row is available

41

Step 4: Find the darkest reading corresponding to largest adjusted

reading.

Step 5: Find the differences of the darkest reading from other readings.

Step 6: Compare the darkest reading with Threshold1* (value below

this indicates no mark). If the threshold is not exceeded, take

decision for no mark and jump to step 8.

Step 7: Compare the calculated differences with Threshold2* (value

greater than this indicates single dark mark) and if the threshold

is exceeded take decision for a single dark mark. Otherwise,

take decision for invalid mark (e.g. more than one dark marks).

Step 8: Display the result and send it to a PC for storage.

Step 9: Wait until next row is available and after acquisition of data

jump to Step 1.

*Values of Threshold1 and Threshold2 are obtained by observing the response data of input sensors.

42

Fig3.5 Flowchart for data processing

Darkest reading> Threshold2

Result as valid dark mark

Send result to PC

Wait until the next row is available

Result as no valid mark

Result as no valid mark

Adjust reading using calibration

constants

Find the darkest reading

Darkest reading> Threshold1

Compute calibration constant for dark reading

Compute calibration constant for

white reading

START

Check device mode

Display result

Y

N

Y

N

“01” “10”

“00”

43

3.6 COMPUTATION OF CALIBRATION CONSTANTS

Since, the readings are taken from 4 points let us define them as A, B, C, D.

Switch status: “01” (calibration for dark readings)

Let the maximum value of A, B, C, D be defined as Amax, Bmax, Cmax, Dmax

respectively.

Calibration constant for dark readings:

The average value of the four maximum readings corresponding to dark

readings is computed as:

Avgmax = (Amax+ Bmax+ Cmax+ Dmax)/4

The offset (calibration constant) of each maximum reading from this value is

calculated as:

Aoffmax = Avgmax - Amax

Similarly, the calibration constants for other readings are calculated.

Switch status: “10” (calibration for white paper)

Let the minimum value of A, B, C, D be defined as Amin, Bmin, Cmin, Dmin respectively.

Calibration constant for white sheet of paper

The average value of the four minimum readings corresponding to

white paper is computed as:

Avgmin = (Amin+ Bmin+ Cmin+ Dmin)/4

The offset (calibration constant) of each maximum reading from this

value is calculated as:

Aoffmin = Avgmin - Amin

44

Similarly, the calibration constants for other readings are calculated.

Adjustment of readings using calibration constants:

When the actual answer sheet row is checked, the readings are adjusted as:

If A>= Amax-0.5 (in volts), the adjustment is done using constant Aoffmax as shown

below.

Aadjusted = A + Aoffmax

Similarly, the adjustment is done for other readings.

If A<Amax -0.5(in volts), the adjustment is done using constant Aoffmin as shown

below.

Aadjusted = A + Aoffmin

Similarly, the adjustment is done for other readings.

45

3.7 RESULT STORAGE AND MANAGEMENT

The result obtained from data processing has to be sent to the PC for further

analysis, printing and also for comparison with correct answer sheet data. In order to

achieve this, the serial UART of Spartan 3E kit is utilized in this project.

The conceptual block diagram of the UART transmitting subsystem that we

designed to transmit data from the FPGA serially to the computer is shown below. It

consists of three major components:

1. Interface Circuit(FIFO): the circuit that provides buffer and status

between the UART transmitter and the system

2. Baud rate generator: the circuit to generate the sampling ticks

3. UART transmitter: the circuit to serialize the parallel data from the

FPGA for transmission

Figure3.6 Basic block diagram of the UART transmitting subsystem

FIFO

tick BAUD RATE GENERATOR

TRANSMITTER

tx din

rd wr

Empty full

r_data w_data

w_data

wr_uart

tx_full

tx

rx_done_tick

tx_start

s_tick

clk

clk

reset

reset

46

The FIFO buffer provides buffering space and reduces the chances of data

overrun. We can adjust the desired number of words in FIFO to accommodate the

processing need of the main system. After the completion of word transmission

‘tx_done_tick’ is asserted by transmitter which is connected to the ‘rd’ signal of the

FIFO. Thus next data word is read from the FIFO for the further transmission.

The Baud rate generator produces the sampling ticks whose frequency is exactly

16 times the baud rate designed. As we have chosen the baud rate of 19200 (bits per

second), the sampling ticks produced by the baud rate generator has frequency

307200 (i.e. 19200*16). Since the system clock is of frequency 50MHZ the baud rate

generator can be implemented by a mode-163 (i.e. 50*1000000/307200=163) counter.

The UART transmitter uses the internal counter to keep track of the number of the

enable ticks produced by the baud rate generator. A bit is shifted out every 16 enable

ticks. The ASMD chart of the implemented UART transmitter is shown below. After

assertion of the tx-start signal, the FSMD loads the data word and then gradually

progresses through the start, data, and stop states to shift out the corresponding bits. It

signals completion by asserting the tx-done-tick signal for one clock cycle.

47

tx start=1

s 0

s_tick=1

s=7

s 0 n 0

s tick=1

s=15

S 0 b (0&b>>1)

n=D_BIT-1 n n+1

s s+1

s s+1

s_tick=1

s=SB_TICK-1

rx done tick<=1 s s+1

Fig3.7 State flow chart of the UART Transmitter

IDLE

START

STOP

DATA

F

F

F

F

F

F

F

F

T

48

This is the block diagram of four different states viz. ‘ideal’, ‘start’, ‘data’ and ‘stop’ which we have used in our project. As we have not used the parity bit in data transmission it is not shown in the state diagram above.

Here the finite state machine (FSM ) stays in the same state unless the ‘s_tick’ signal is asserted. There are two counters, represented by s and n registers. The ‘s’ register keeps track of the no of sampling ticks and counts to 15 in the start state,15 in the data state and to SB_TICK in the stop state. The ‘n’ register keeps track of the no of data bits received in the data state. The data bits to be transmitted is shifted with in a register’ b ’ concatenating zero and the LSB is send first and so on. A status signal ‘tx_done_tick’ is asserted one clock cycle after the data frame is transmitted.

3.8 DATABASE DESIGN

Data Storage and the Graphical User Interface

Though the main objective of project is to make the fully independent and

dedicated hardware module ,to establish the user interaction with the hardware

generated data and further analysis and long term storage of structured data, the great

importance of the GUI and Database Management System (DBMS) is perceived. So

the simple digital interface and relational database is created using the MATLAB and

WampServer environment.

Here the source of data is the FPGA which is serially interfaced with pc using the

RS232. FPGA is programmed to send primarily the roll no of the examinee and the

total obtained marks. It is also designed to send the each answer for individual

question. Based on these input data the database is designed.

The MySQL database is connected through the MATLAB using the MyODBC

driver. The relational database management system (RDBMS) is handled using

MATLAB API.

Database Design

The database named as ADE is designed based on the Relational database model.

It consists of two tables named ‘result’ and the ‘answer_ sheet’. The table result

consist of four attributes as follows,

Id INT, not null, auto_increment, primary key.

roll_no INT, not null.

Name VARCHAR(50),not null.

Marks FLOAT, not null.

49

And the table answer_sheet consist of attribute as follows

Id INT, not null, auto_increment, primary key.

QN INT, not null.

option_chosen ENUM(‘a’,’b’,’c’,’d’).

roll_no INT,not null.

Here the roll_no is foreign key derived from result.

E-R Diagram for ADE

Fig3.8: Figure showing the E-R diagram for ADE database.

GUI Design

Components used in the GUI design:

panels Push buttons Popup menu Static text

Result

Answer_sheet

Roll_No

Id name

Option_choosed

Marks

Roll_No

QN

Provides

Id

50

Edit text Menu Editor Uitable Error dialog

Features Included in GUI

There are two panels one for the database access and the other for the database entry. In the database entry panel there are two push buttons named read data and upload. The read data button handles the read operation from the serial port. The upload button connects the MySQL database and inserts the data into the corresponding table of database. Similarly there are two edit texts for the display of alternatively question no and option chosen and final obtained marks and roll no. There are three static texts for displaying the tag of data displayed in edit text and to give information about the data upload process.

Same way in the next panel there is search option. There is popup menu for searching the result by name and by roll no. The list of matched results is displayed in the uitable. If there is no match in database not found dialog will be displayed.

51

In the menu bar there are two option for displaying the whole merit list and alphabetical list.

3.9 IMPLEMENTATION OF THE PROJECT

The implementation of the project can be functionally described using the

following process diagram.

The above process diagram describes how the project as a device is to be used in

its implementation. Before the device can be used to check answer sheet marks, it has

to be calibrated in some way for both white sheet and dark mark. For this the scanning

by optical sensors is done before each calibration. Finally after the two calibrations

are performed the device becomes ready to accept answer sheet marks.

The calibration techniques are necessary because the analog responses of the

optical sensors vary from time to time due to temperature variations and other

external factors. Also different input sensors have different voltage characteristics.

For example, one of the input sensors may give 2.5V reading for dark mark while

another might gave 2V for the same mark. So a direct comparison of voltages surely

will not give correct results. The data processing algorithm and the calibration

techniques as described above are implemented to tackle the above mentioned

problems of input sensors.

Scanning by optical sensors

Calibration for white

paper


Calibration for dark readings

Answer sheet check


Fig3.9 Implementation of project

Figure A: Detailed circuit of input section interfaced with FPGA

From FPGA output port

To FPGA input port

+ 5V

+ 5V

From FPGA output port

52

4. RESULT AND ANALYSIS

In the implementation of the project, analog data from input sensor module were

taken for different answer sheet rows. Figure below shows a picture of the answer

sheet used to collect these analog voltage data.

Fig 4.1 Sample answer sheet used to obtain the above presented data

4.1 SAMPLE ANSWER SHEET

53

The data collected from the above answer sheet rows are presented below.

Analog voltage readings for a set 24 rows of marks (taken four times)

First pass

A (V) B (V) C (V) D (V)

0.95 0.82 1.8 1.44

1.94 0.95 1.13 1.22

0.9 1.92 0.82 1.15

0.93 0.7 0.85 2.06

1.4 0.82 1.4 1.1

1.12 1.96 0.95 2

1.12 0.98 0.98 1.12

1.77 1.98 1.82 1.85

1.22 1.07 1.76 1.3

1.23 1 1.42 1.18

0.88 1.02 0.8 0.96

1.24 0.61 0.78 0.96

0.77 0.36 0.66 0.98

0.8 0.94 0.79 0.85

1.04 0.42 0.69 0.9

1.25 0.36 0.67 1.12

0.9 0.28 0.77 0.95

0.76 0.56 0.51 0.91

0.9 0.59 1.03 0.95

0.85 0.72 0.53 1

0.92 1.04 0.58 0.84

1.12 0.46 0.7 0.95

0.9 0.26 0.3 1.01

0.86 0.87 0.79 0.92

4.2 DATA ANALYSIS

54

Second pass

0.9 1.2 2.11 1.25

1.88 1.07 1.12 0.97

0.79 1.92 1.02 0.97

0.86 1.04 1.15 2.02

1.43 1 1.6 1.01

0.85 1.94 1.2 1.86

1 1.21 1.24 1.04

1.57 1.97 2.04 1.9

1.12 1.4 2.14 1.3

1.28 1.32 1.68 1.2

0.94 1.3 1.08 0.94

1.1 0.8 1.06 0.87

0.96 0.88 1.17 0.91

0.81 0.99 1.27 0.89

1 0.59 1.02 2

1.08 0.73 0.87 1

0.8 0.67 1.08 0.94

0.89 1.01 0.89 0.76

0.79 0.82 1.22 0.73

0.81 0.98 0.92 0.93

0.75 1.21 1 0.81

1.02 0.82 1.08 0.79

0.9 0.82 1.64 0.77

0.83 1.35 1.09 0.76

55

Third pass

0.52 0.42 1.66 1.03

1.65 0.4 0.64 0.63

0.45 1.38 0.5 0.62

0.49 0.29 0.61 1.82

1 0.32 1.22 0.66

0.6 1.36 0.68 1.68

0.6 0.44 0.72 0.64

1.25 1.54 1.76 1.61

0.83 0.82 1.87 1.01

0.95 0.71 1.24 0.97

0.57 0.72 0.63 0.65

0.83 0.32 0.63 0.64

0.5 0.28 0.68 0.68

0.64 0.8 0.92 0.72

0.84 0.48 0.65 1.92

0.91 0.31 0.54 0.9

0.52 0.25 0.79 0.74

0.6 0.59 0.57 0.75

0.7 0.42 1.03 0.72

0.69 0.69 0.71 0.92

0.59 0.84 0.49 0.72

0.81 0.34 0.66 0.78

0.64 0.39 1.4 0.77

0.77 1.15 0.76 0.67

56

Fourth pass

0.68 0.62 1.75 1.17

1.79 0.59 0.84 0.84

0.72 1.68 0.81 0.87

0.67 0.57 0.77 1.84

1.16 0.66 1.47 0.85

0.71 1.77 1.05 1.86

0.72 0.67 0.83 0.75

1.5 1.71 1.81 1.84

1.05 1.21 1.98 1.16

1.17 1.16 1.62 1.17

0.85 1.2 1.05 0.93

1.15 0.86 1.04 0.87

0.79 0.79 1.02 0.82

0.89 1.3 1.33 0.85

1.15 1.07 1.24 2.02

1.12 1.15 1.39 1.36

0.66 0.56 1.05 0.81

0.66 0.74 0.73 0.73

0.75 0.54 1.07 0.8

0.82 0.89 0.85 0.99

0.74 1.03 0.61 0.71

0.97 0.5 0.76 0.75

0.68 0.52 1.5 0.8

0.71 1.16 0.82 0.78

57

4.3 RESULTS

To verify the results a large number of answer sheets were used. Also, various

parameters, specially the threshold levels were varied in testing and tuning the device.

The dynamic thresholds were also used in VHDL implementation of algorithm in

order to attain best results for varying circumstances.

The figure below shows one such answer sheet used to check the result after

processing. The results of processing are shown alongside the figure. In the results, bit

patterns are used to indicate the given output condition.

Fig 4.2 Sample answer sheet and output of processing

In the testing certain kinds of marks such as a faint mark or incomplete mark in

14th row were also detected but the output showed some amount of inconsistency.

58

4.4 TOOLS AND SOFTWARE USED FOR THE IMPLEMENTATION

For the implementation of the project, Xilinx ISE 10.1 was used for coding,

debugging and downloading VHDL codes into the FPGA board. ISE simulator as

well as ModelSim 6.1b simulators was used to simulate the behavioral and post route

model of synthesized VHDL codes.

As the post route simulation gives best approximation of the actual

implementation of netlist in FPGA, it is shown in the diagram below.

Fig 4.3 Simulation result of processing

In the simulation, the calibration is done for dark readings only, however, the

vhdl code includes both dark and white paper calibration techniques. The final output

of the simulation, i.e. result shows the value “0001” corresponding to the valid dark

mark in first option. Although the simulator gets equal readings from all sensors in the

actual check, the adjusted values make the first option as valid mark.

After the synthesis of the modules in ISE 10.1, the RTL schematics were viewed

to determine correctness of some logics. The figure below shows the basic block of

the top level module.

59

Fig 4.4 Basic block of the top level VHDL module

Similarly the detailed circuitries of each module from RTL synthesis are shown

below.

Fig 4.5 RTL schematic of ADC_interface module

60

Fig 4.6 RTL schematic of data_acquisition module

The data processing module when synthesized formed complex RTL schematics

because of which it is not shown in the report.

Fig 4.7 Simulated output for serial transmission

61

The simulation shows the detail of transmission of a fixed byte “11001100”

using serial transmission. As the data is fed to the transmitter, the rising edge of

tx_start starts the transmission process. The serial output appears in the tx line. The

serial data that is transmitted through tx line is consistent with serial transmission

format. Finally, the rising edge of tx_done_tick signifies end of transmission of single

frame.

4.5 ECONOMIC ANALYSIS

INPUT SECTION COST S.No Materials Quantity Rate (NRs) Cost (NRs) 1 LEDs 4 15 60 2 Phototransistors 4 30 120 3 Resistors 30 4 Bread board 1 250 250 5 Wires 40 6 Miscellaneous 100 TOTAL 600 DATA ACQUISITION AND PROCESSING COST S.No Materials Quantity Rate (NRs) Cost (NRs) 1 FPGA 1 10,500 10,500 2 ADC (0808CCN) 1 450 450 3 Buffer (HEF4050BP) 2 60 120 4 Miscellaneous 100 TOTAL 11170 TOTAL COST IN NRs = 600+11,170 = NRs 11,770 Note:

1. Cost of the Components damaged during the project period isn’t included. 2. Cost is exclusive of transportation, communication and other overheads.

62

5.1 CONCLUSION

The project “Automatic Digital Examiner” has been completed as an essential task in the partial fulfillment of the requirement for the degree of Bachelor of Electronics Engineering.

The basic aim to build an optical mark reader using digital design has been completed through the given project. The project was also carried out as an objective to dig the aspects of digital design using VHDL and FPGA. The complex concepts of implementing VHDL in FPGA board were learned practically from the project. Similarly, analog optoelectronic components were effectively used in the project.

In contrary to normal situation, we had to find completely new algorithms to achieve the objectives. The creation of algorithms for the project was a real challenge. Various approaches were taken before a final method/algorithm was selected as the best one in our situation. Therefore, the creation and selection of algorithms best suitable for the project was an important aspect.

From the project so conducted, it is found that the realization of an optical mark reader in hardware has many limitations. The major issues found were of reliability and on the method of use of the device. Although the device, in normal circumstances showed excellent results, there were some inconsistencies in special cases such as faint marks and invalid marks such as more than one mark of different darkness. In cases of more than one marks of different darkness, the problem would be easily solved using dynamic thresholds, which however was not realized in time. Apart from these, the device showed high dependency on the alignment of paper during calibration process. Slight misalignment was found to produce large variations in output. However, by using accurate placement of analog components, the project can serve as a very reliable alternative to commonly used scanner-computer method.

Hence, we conclude that the method of objective answer sheet checking using dedicated hardware methods with the applied algorithm is applicable, but only under strict conditions discussed above.

5. EPILOGUE

63

5.2 LIMITATIONS:

1. The size of elliptical space used for marking cannot be made arbitrarily small. The recommended minimum size of ellipse is 0.5 cm diameter measured on the longer side.

2. The input modules show good responses for smooth surface papers such as standard photocopy paper. The device will not show predictable behavior for rough surface papers.

3. The device is affected by large environmental variations.

4. Data analysis is not always reliable because from each mark space we get a single voltage value.

5. The device cannot be used for high ambient light or on direct sunlight conditions.

6. Paper has to be kept completely stationary and height of the paper from optical sensors must be kept constant at all times.

7. Moving paper with hand is not a reliable method to obtain next row data automatically using “row detector” (black spot on the side of each row). Therefore, a manual switch is used to perform next row scan.

8. Pencil of enough darkness such as ‘B’ may be required for marking to make data processing reliable.

5.3 RECOMMENDATIONS FOR FUTURE ENHANCEMENT

1. The next row data can be taken automatically by moving the paper in a controlled way, for example, by using a printer.

2. The voltage used to drive LEDs can be obtained from a DAC so that all the phototransistors in input sensor module will have exactly same response for a white paper. This will greatly increase the reliability of the device.

3. More than one voltage data can be obtained for each mark space if we use tiny multiple phototransistors so that we have two or three voltage data from every mark space.

4. The mechanism to add correct answer sheet data in the FPGA memory can be devised so that we will not need any kind of comparison in the computer.

64

6. BIBLIOGRAPHY:

Circuit Design with VHDL by Volnei A. Pedroni

VHDL Programming by Examples by Douglas L. Perry

An Engineering Approach to Digital Design by I.L. Fletcher

Xilinx Spartan 3E user manual

FPGA Prototyping by VHDL Examples by Pong P. Chu

www.wikipedia.org

www.alldatasheet.com

Characteristics of Phototransistors

An equivalent circuit for a phototransistor consists of a photodiode feeding itsoutput photocurrent into the base of a small signal transistor. Based on thismodel it is not surprising that phototransistors display some of thecharacteristics of both types of devices.

Spectral Response

The output of a phototransistor is dependent upon the wavelength of incidentlight. These devices respond to light over a road range of wavelengths fromthe near UV, though the visible, and into the near IR part of the spectrum.Unless optical filters are used, the peak spectral response is in the near IR atapproximately 840 nm. The peak response is at a somewhat shorterwavelength than that of a typical photodiode. This is because the diffusedjunctions of a phototransistor are formed in epitaxial rather than crystal grownsilicon wafers.

Phototransistors will respond to fluorescent or incandescent light sources butdisplay better optical coupling efficiencies when matched with IREDs.

Sensitivity

For a given light source and illumination level, the output of a phototransistoris defined by the area of the exposed collector-base junction and the dccurrent gain of the transistor. The collector-base junction of thephototransistor functions as a photodiode generating a photocurrent which isfed into the base of the transistor section. Thus, like the case for a photodiode,doubling the size of the base region doubles the amount of generated basephotocurrent. This photocurrent (lP) then gets amplified by the dc current gainof the transistor. For the case where no external base drive current is applied:

lC = hFE (lP)

where:

lC = collector currenthFE = DC current gainlP = photocurrent

As is the case with signal transistors, hFE is not a constant butvaries with base drive, bias voltage, and temperature. At low lightlevels the gain starts out small but increases with increasing light(or base drive) until a peak is reached. As the light level is furtherincreased the gain of the phototransistor starts to decrease.

Transistor Gain vs Light Intensity

HFE will also increase with increasing values for VCE. The current-voltagecharacteristics of a typical transistor will demonstrate this effect. For aconstant base drive the curve shows a positive slope with increasing voltage.

It is clear the current gain at collector-emitter voltage VCE2 is greater than thecurrent gain at VCE1.

Current vs Voltage Curves

The current gain will also increase with increasing temperature.

9


Linearity

Unlike a photodiode whose output is linear with respect to incident light over 7to 9 decades of light intensity, the collector current (lC) of a phototransistor islinear for only 3 to 4 decades of illumination. The prime reason for thislimitation is that the dc gain (hFE) of the phototransistor is a function ofcollector current (lC) which in turn is determined by the base drive. The basedrive may be in the form of a base drive current or incident light.

Photodetector Relative Linearity

While photodiodes are the detector of choice when linear output versus lightintensity is extremely important, as in light intensity measuring equipment, thephototransistor comes into its own when the application requires aphotodetector to act like a switch. When light is present, a phototransistor canbe considered “on”, a condition during which they are capable of sinking a fairamount of current. When the light is removed these photodetectors enter an“off” state and function electrically as open switches. How wellphototransistors function as switches is covered in the next few sections.

Collector-Emitter Saturation Voltage - VCE(SAT)

By definition, saturation is the condition in which both the emitter-base andthe collector-base junctions of a phototransistor become forward based. Froma practical standpoint the collector-emitter saturation voltage, VCE(SAT), is the

parameter which indicates how closely the photodetector approximates aclosed switch. This is because VCE(SAT) is the voltage dropped across thedetector when it is in its “on” state.

VCE(SAT) is usually given as the maximum collector-emitter voltage allowed ata given light intensity and for a specified value of collector current.PerkinElmer tests their detectors for VCE(SAT) at a light level of 400 fc and with1 mA of collector current flowing through the device. Stock phototransistorsare selected according to a set of specifications where VCE(SAT) can rangefrom 0.25V (max) to 0.55V (max) depending on the device.

Dark Current - (lD)

When the phototransistor is placed in the dark and a voltage is applied fromcollector to emitter, a certain amount of current will flow. This current is calledthe dark current (lD). This current consists of the leakage current of thecollector-base junction multiplied by the dc current gain of the transistor. Thepresence of this current prevents the phototransistor from being consideredcompletely “off”, or being an ideal “open” switch.

The dark current is specified as the maximum collector current permitted toflow at a given collector-emitter test voltage. The dark current is a function ofthe applied collector-emitter voltage and ambient temperature.

PerkinElmer’s standard phototransistors are tested at a VCE applied voltage ofeither 5V, 10V or 20V depending on the device. Phototransistors are tested todark current limits which range from 10 nA to 100 nA.

Dark current is temperature dependent, increasing with increasingtemperature. It is usually specified at 25°C.

Breakdown Voltages - (VBR)

Phototransistors must be properly biased in order to operate. However, whenvoltages are applied to the phototransistor, care must be taken not to exceedthe collector-emitter breakdown voltage (VBRECO). Exceeding the breakdownvoltage can cause permanent damage to the phototransistor. Typical valuesfor VBRECO range from 20V to 50V. Typical values for VBRECO range from 4Vto 6V. The breakdown voltages are 100% screened parameters.

10


Speed of Response

The speed of response of a phototransistor is dominated almost totally by thecapacitance of the collector-base junction and the value of the loadresistance. These dominate due to the Miller Effect which multiplies the valueof the RC time constant by the current gain of the phototransistor. This leadsto the general rule that for devices with the same active area, the higher thegain of the photodetector, the slower will be its speed of response.

A phototransistor takes a certain amount of time to respond to suddenchanges in light intensity. This response time is usually expressed by the risetime (tR) and fall time (tF) of the detector where:

tR - The time required for the output to rise from 10% to 90% of its on-state value.

tF - The time required for the output to fall from 90% to 10% of its on-state value.

As long as the light source driving the phototransistor is not intense enough tocause optical saturation, characterized by the storage of excessive amountsof charge carriers in the base region, risetime equals falltime. If opticalsaturation occurs, tF can become much larger than tR.

PerkinElmer tests the tR and tF of its phototransistors at an lC = 1.0 mA andwith a 100 ohm load resistor in series with the detector. Phototransistorsdisplay tR and tF times in a range of 1 µsec to 10 µsec.

Selecting a Photodetector

Each application is a unique combination of circuit requirements, lightintensity levels, wavelengths, operating environment, and cost considerations.

PerkinElmer offers a broad range of catalog phototransistors to help you withthese design tradeoffs.

The charts presented below are intended to give some general guidelines andtradeoffs for selecting the proper detector for your application.

Size of Detector Chip

Gain (HFE)

SMALL SIZE PARAMETER LARGE SIZE

LOWER SENSITIVITY HIGHER

FASTER SPEED OF RESPONSE SLOWER

LOWER DARK CURRENT HIGHER

LOWER COST HIGHER

LOW GAIN PARAMETER HIGH GAIN

LOWER SENSITIVITY HIGHER

FASTER SPEED OF RESPONSE SLOWER

LOWER DARK CURRENT HIGHER

SMALLER TEMP. COEF. LARGER

LOWER COST HIGHER

11

ADC0808/ADC08098-Bit µP Compatible A/D Converters with 8-ChannelMultiplexerGeneral DescriptionThe ADC0808, ADC0809 data acquisition component is amonolithic CMOS device with an 8-bit analog-to-digital con-verter, 8-channel multiplexer and microprocessor compatiblecontrol logic. The 8-bit A/D converter uses successive ap-proximation as the conversion technique. The converter fea-tures a high impedance chopper stabilized comparator, a256R voltage divider with analog switch tree and a succes-sive approximation register. The 8-channel multiplexer candirectly access any of 8-single-ended analog signals.

The device eliminates the need for external zero andfull-scale adjustments. Easy interfacing to microprocessorsis provided by the latched and decoded multiplexer addressinputs and latched TTL TRI-STATE outputs.

The design of the ADC0808, ADC0809 has been optimizedby incorporating the most desirable aspects of several A/Dconversion techniques. The ADC0808, ADC0809 offers highspeed, high accuracy, minimal temperature dependence,excellent long-term accuracy and repeatability, and con-sumes minimal power. These features make this deviceideally suited to applications from process and machinecontrol to consumer and automotive applications. For16-channel multiplexer with common output (sample/holdport) see ADC0816 data sheet. (See AN-247 for more infor-mation.)

Featuresn Easy interface to all microprocessorsn Operates ratiometrically or with 5 VDC or analog span

adjusted voltage referencen No zero or full-scale adjust requiredn 8-channel multiplexer with address logicn 0V to 5V input range with single 5V power supplyn Outputs meet TTL voltage level specificationsn ADC0808 equivalent to MM74C949n ADC0809 equivalent to MM74C949-1

Key Specificationsn Resolution 8 Bitsn Total Unadjusted Error ±1⁄2 LSB and ±1 LSBn Single Supply 5 VDC

n Low Power 15 mWn Conversion Time 100 µs

Block Diagram

00567201

See OrderingInformation

October 2002A

DC

0808/AD

C0809

8-Bit

µPC

ompatible

A/D

Converters

with

8-ChannelM

ultiplexer

© 2002 National Semiconductor Corporation DS005672 www.national.com

Connection Diagrams

Dual-In-Line Package

00567211

Order Number ADC0808CCN or ADC0809CCNSee NS Package J28A or N28A

Molded Chip Carrier Package

00567212

Order Number ADC0808CCV or ADC0809CCVSee NS Package V28A

Ordering InformationTEMPERATURE RANGE −40˚C to +85˚C

Error ±1⁄2 LSB Unadjusted ADC0808CCN ADC0808CCV

±1 LSB Unadjusted ADC0809CCN ADC0809CCV

Package Outline N28A Molded DIP V28A Molded Chip Carrier

AD

C08

08/A

DC

0809

www.national.com 2

Absolute Maximum Ratings (Notes 2,

1)

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (VCC) (Note 3) 6.5V

Voltage at Any Pin −0.3V to(VCC+0.3V)

Except Control Inputs

Voltage at Control Inputs −0.3V to +15V

(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)

Storage Temperature Range −65˚C to +150˚C

Package Dissipation at TA=25˚C 875 mW

Lead Temp. (Soldering, 10 seconds)

Dual-In-Line Package (plastic) 260˚C

Molded Chip Carrier Package

Vapor Phase (60 seconds) 215˚C

Infrared (15 seconds) 220˚C

ESD Susceptibility (Note 8) 400V

Operating Conditions (Notes 1, 2)

Temperature Range (Note 1) TMIN≤TA≤TMAX

ADC0808CCN,ADC0809CCN −40˚C≤TA≤+85˚C

ADC0808CCV, ADC0809CCV −40˚C≤TA≤+85˚C

Range of VCC (Note 1) 4.5 VDC to 6.0 VDC

Electrical CharacteristicsConverter Specifications: VCC=5 VDC=VREF+, VREF(−)=GND, TMIN≤TA≤TMAX and fCLK=640 kHz unless otherwise stated.

Symbol Parameter Conditions Min Typ Max Units

ADC0808

Total Unadjusted Error 25˚C ±1⁄2 LSB

(Note 5) TMIN to TMAX ±3⁄4 LSB

ADC0809

Total Unadjusted Error 0˚C to 70˚C ±1 LSB

(Note 5) TMIN to TMAX ±11⁄4 LSB

Input Resistance From Ref(+) to Ref(−) 1.0 2.5 kΩAnalog Input Voltage Range (Note 4) V(+) or V(−) GND−0.10 VCC+0.10 VDC

VREF(+) Voltage, Top of Ladder Measured at Ref(+) VCC VCC+0.1 V

Voltage, Center of Ladder VCC/2-0.1 VCC/2 VCC/2+0.1 V

VREF(−) Voltage, Bottom of Ladder Measured at Ref(−) −0.1 0 V

IIN Comparator Input Current fc=640 kHz, (Note 6) −2 ±0.5 2 µA

Electrical CharacteristicsDigital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V,−40˚C≤TA≤+85˚C unless otherwise noted


ANALOG MULTIPLEXER

IOFF(+) OFF Channel Leakage Current VCC=5V, VIN=5V,

TA=25˚C 10 200 nA

TMIN to TMAX 1.0 µA

IOFF(−) OFF Channel Leakage Current VCC=5V, VIN=0,

TA=25˚C −200 −10 nA

TMIN to TMAX −1.0 µA

CONTROL INPUTS

VIN(1) Logical “1” Input Voltage VCC−1.5 V

VIN(0) Logical “0” Input Voltage 1.5 V

IIN(1) Logical “1” Input Current VIN=15V 1.0 µA

(The Control Inputs)

IIN(0) Logical “0” Input Current VIN=0 −1.0 µA

(The Control Inputs)

ICC Supply Current fCLK=640 kHz 0.3 3.0 mA

AD

C0808/A

DC

0809

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Electrical Characteristics (Continued)Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V,−40˚C≤TA≤+85˚C unless otherwise noted


DATA OUTPUTS AND EOC (INTERRUPT)

VOUT(1) Logical “1” Output Voltage VCC = 4.75VIOUT = −360µAIOUT = −10µA

2.44.5

V(min)V(min)

VOUT(0) Logical “0” Output Voltage IO=1.6 mA 0.45 V

VOUT(0) Logical “0” Output Voltage EOC IO=1.2 mA 0.45 V

IOUT TRI-STATE Output Current VO=5V 3 µA

VO=0 −3 µA

Electrical CharacteristicsTiming Specifications VCC=VREF(+)=5V, VREF(−)=GND, tr=tf=20 ns and TA=25˚C unless otherwise noted.

Symbol Parameter Conditions MIn Typ Max Units

tWS Minimum Start Pulse Width (Figure 5) 100 200 ns

tWALE Minimum ALE Pulse Width (Figure 5) 100 200 ns

ts Minimum Address Set-Up Time (Figure 5) 25 50 ns

tH Minimum Address Hold Time (Figure 5) 25 50 ns

tD Analog MUX Delay Time RS=0Ω (Figure 5) 1 2.5 µs

From ALE

tH1, tH0 OE Control to Q Logic State CL=50 pF, RL=10k (Figure 8) 125 250 ns

t1H, t0H OE Control to Hi-Z CL=10 pF, RL=10k (Figure 8) 125 250 ns

tc Conversion Time fc=640 kHz, (Figure 5) (Note 7) 90 100 116 µs

fc Clock Frequency 10 640 1280 kHz

tEOC EOC Delay Time (Figure 5) 0 8+2 µS Clock

Periods

CIN Input Capacitance At Control Inputs 10 15 pF

COUT TRI-STATE Output At TRI-STATE Outputs 10 15 pF

Capacitance

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operatingthe device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless othewise specified.

Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.

Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode dropgreater than the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltageby more than 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of4.900 VDC over temperature variations, initial tolerance and loading.

Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust.However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the referencevoltages can be adjusted to achieve this. See Figure 13.

Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and haslittle temperature dependence (Figure 6). See paragraph 4.0.

Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.

Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.

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Functional DescriptionMultiplexer. The device contains an 8-channel single-endedanalog signal multiplexer. A particular input channel is se-lected by using the address decoder. Table 1 shows the inputstates for the address lines to select any channel. Theaddress is latched into the decoder on the low-to-high tran-sition of the address latch enable signal.

TABLE 1.

SELECTED ADDRESS LINE

ANALOG CHANNEL C B A

IN0 L L L

IN1 L L H

IN2 L H L

IN3 L H H

IN4 H L L

IN5 H L H

IN6 H H L

IN7 H H H

CONVERTER CHARACTERISTICS

The Converter

The heart of this single chip data acquisition system is its8-bit analog-to-digital converter. The converter is designed togive fast, accurate, and repeatable conversions over a widerange of temperatures. The converter is partitioned into 3major sections: the 256R ladder network, the successiveapproximation register, and the comparator. The converter’sdigital outputs are positive true.

The 256R ladder network approach (Figure 1) was chosenover the conventional R/2R ladder because of its inherentmonotonicity, which guarantees no missing digital codes.Monotonicity is particularly important in closed loop feedbackcontrol systems. A non-monotonic relationship can causeoscillations that will be catastrophic for the system. Addition-ally, the 256R network does not cause load variations on thereference voltage.

The bottom resistor and the top resistor of the ladder net-work in Figure 1 are not the same value as the remainder ofthe network. The difference in these resistors causes theoutput characteristic to be symmetrical with the zero andfull-scale points of the transfer curve. The first output transi-tion occurs when the analog signal has reached +1⁄2 LSBand succeeding output transitions occur every 1 LSB later upto full-scale.

The successive approximation register (SAR) performs 8iterations to approximate the input voltage. For any SARtype converter, n-iterations are required for an n-bit con-verter. Figure 2 shows a typical example of a 3-bit converter.In the ADC0808, ADC0809, the approximation technique isextended to 8 bits using the 256R network.

The A/D converter’s successive approximation register(SAR) is reset on the positive edge of the start conversionstart pulse. The conversion is begun on the falling edge ofthe start conversion pulse. A conversion in process will beinterrupted by receipt of a new start conversion pulse. Con-tinuous conversion may be accomplished by tying theend-of-conversion (EOC) output to the SC input. If used inthis mode, an external start conversion pulse should beapplied after power up. End-of-conversion will go low be-tween 0 and 8 clock pulses after the rising edge of startconversion.

The most important section of the A/D converter is thecomparator. It is this section which is responsible for theultimate accuracy of the entire converter. It is also the com-parator drift which has the greatest influence on the repeat-ability of the device. A chopper-stabilized comparator pro-vides the most effective method of satisfying all theconverter requirements.

The chopper-stabilized comparator converts the DC inputsignal into an AC signal. This signal is then fed through ahigh gain AC amplifier and has the DC level restored. Thistechnique limits the drift component of the amplifier since thedrift is a DC component which is not passed by the ACamplifier. This makes the entire A/D converter extremelyinsensitive to temperature, long term drift and input offseterrors.

Figure 4 shows a typical error curve for the ADC0808 asmeasured using the procedures outlined in AN-179.

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Functional Description (Continued)

00567202

FIGURE 1. Resistor Ladder and Switch Tree

00567213

FIGURE 2. 3-Bit A/D Transfer Curve

00567214

FIGURE 3. 3-Bit A/D Absolute Accuracy Curve

00567215

FIGURE 4. Typical Error Curve

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Timing Diagram

00567204

FIGURE 5.

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Typical Performance Characteristics

00567216

FIGURE 6. Comparator IIN vs VIN

(VCC=VREF=5V)

00567217

FIGURE 7. Multiplexer RON vs VIN

(VCC=VREF=5V)

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TRI-STATE Test Circuits andTiming Diagrams

Applications Information

OPERATION

1.0 RATIOMETRIC CONVERSION

The ADC0808, ADC0809 is designed as a complete DataAcquisition System (DAS) for ratiometric conversion sys-tems. In ratiometric systems, the physical variable beingmeasured is expressed as a percentage of full-scale which isnot necessarily related to an absolute standard. The voltageinput to the ADC0808 is expressed by the equation

(1)

VIN=Input voltage into the ADC0808

Vfs=Full-scale voltage

VZ=Zero voltage

DX=Data point being measured

DMAX=Maximum data limit

DMIN=Minimum data limit

A good example of a ratiometric transducer is a potentiom-eter used as a position sensor. The position of the wiper isdirectly proportional to the output voltage which is a ratio ofthe full-scale voltage across it. Since the data is representedas a proportion of full-scale, reference requirements aregreatly reduced, eliminating a large source of error and costfor many applications. A major advantage of the ADC0808,ADC0809 is that the input voltage range is equal to thesupply range so the transducers can be connected directlyacross the supply and their outputs connected directly intothe multiplexer inputs, (Figure 9).

Ratiometric transducers such as potentiometers, straingauges, thermistor bridges, pressure transducers, etc., aresuitable for measuring proportional relationships; however,many types of measurements must be referred to an abso-lute standard such as voltage or current. This means asystem reference must be used which relates the full-scalevoltage to the standard volt. For example, ifVCC=VREF=5.12V, then the full-scale range is divided into256 standard steps. The smallest standard step is 1 LSBwhich is then 20 mV.

t1H, tH1

00567218

t1H, CL = 10 pF

00567219

tH1, CL = 50 pF

00567220

t0H, tH0

00567221

t0H, CL = 10 pF

00567222

tH0, CL = 50 pF

00567223

FIGURE 8.

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Applications Information (Continued)

2.0 RESISTOR LADDER LIMITATIONS

The voltages from the resistor ladder are compared to theselected into 8 times in a conversion. These voltages arecoupled to the comparator via an analog switch tree which isreferenced to the supply. The voltages at the top, center andbottom of the ladder must be controlled to maintain properoperation.

The top of the ladder, Ref(+), should not be more positivethan the supply, and the bottom of the ladder, Ref(−), should

not be more negative than ground. The center of the laddervoltage must also be near the center of the supply becausethe analog switch tree changes from N-channel switches toP-channel switches. These limitations are automatically sat-isfied in ratiometric systems and can be easily met in groundreferenced systems.

Figure 10 shows a ground referenced system with a sepa-rate supply and reference. In this system, the supply must betrimmed to match the reference voltage. For instance, if a5.12V is used, the supply should be adjusted to the samevoltage within 0.1V.

The ADC0808 needs less than a milliamp of supply currentso developing the supply from the reference is readily ac-complished. In Figure 11 a ground referenced system isshown which generates the supply from the reference. Thebuffer shown can be an op amp of sufficient drive to supplythe milliamp of supply current and the desired bus drive, or ifa capacitive bus is driven by the outputs a large capacitor willsupply the transient supply current as seen in Figure 12. TheLM301 is overcompensated to insure stability when loadedby the 10 µF output capacitor.

The top and bottom ladder voltages cannot exceed VCC andground, respectively, but they can be symmetrically less thanVCC and greater than ground. The center of the laddervoltage should always be near the center of the supply. Thesensitivity of the converter can be increased, (i.e., size of theLSB steps decreased) by using a symmetrical referencesystem. In Figure 13, a 2.5V reference is symmetricallycentered about VCC/2 since the same current flows in iden-tical resistors. This system with a 2.5V reference allows theLSB bit to be half the size of a 5V reference system.

00567207

FIGURE 9. Ratiometric Conversion System

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00567224

FIGURE 10. Ground ReferencedConversion System Using Trimmed Supply

00567225

FIGURE 11. Ground Referenced Conversion System withReference Generating VCC Supply

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3.0 CONVERTER EQUATIONS

The transition between adjacent codes N and N+1 is givenby:

(2)

The center of an output code N is given by:

(3)

The output code N for an arbitrary input are the integerswithin the range:

(4)

Where: VIN=Voltage at comparator input

VREF(+)=Voltage at Ref(+)

VREF(−)=Voltage at Ref(−)

VTUE=Total unadjusted error voltage (typically

VREF(+)÷512)

00567226

FIGURE 12. Typical Reference and Supply Circuit

00567227

RA=RB

*Ratiometric transducers

FIGURE 13. Symmetrically Centered Reference

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4.0 ANALOG COMPARATOR INPUTS

The dynamic comparator input current is caused by theperiodic switching of on-chip stray capacitances. These areconnected alternately to the output of the resistor ladder/switch tree network and to the comparator input as part ofthe operation of the chopper stabilized comparator.

The average value of the comparator input current variesdirectly with clock frequency and with VIN as shown inFigure 6.

If no filter capacitors are used at the analog inputs and thesignal source impedances are low, the comparator inputcurrent should not introduce converter errors, as the tran-sient created by the capacitance discharge will die out be-fore the comparator output is strobed.

If input filter capacitors are desired for noise reduction andsignal conditioning they will tend to average out the dynamiccomparator input current. It will then take on the character-istics of a DC bias current whose effect can be predictedconventionally.

Typical Application

00567210

*Address latches needed for 8085 and SC/MP interfacing the ADC0808 to a microprocessor

TABLE 2. Microprocessor Interface Table

PROCESSOR READ WRITE INTERRUPT (COMMENT)

8080 MEMR MEMW INTR (Thru RST Circuit)

8085 RD WR INTR (Thru RST Circuit)

Z-80 RD WR INT (Thru RST Circuit, Mode 0)

SC/MP NRDS NWDS SA (Thru Sense A)

6800 VMA•φ2•R/W VMA•φ•R/W IRQA or IRQB (Thru PIA)

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Physical Dimensions inches (millimeters)unless otherwise noted

Molded Dual-In-Line Package (N)Order Number ADC0808CCN or ADC0809CCN

NS Package Number N28B

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Molded Chip Carrier (V)Order Number ADC0808CCV or ADC0809CCV

NS Package Number V28A

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERALCOUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implantinto the body, or (b) support or sustain life, andwhose failure to perform when properly used inaccordance with instructions for use provided in thelabeling, can be reasonably expected to result in asignificant injury to the user.

2. A critical component is any component of a lifesupport device or system whose failure to performcan be reasonably expected to cause the failure ofthe life support device or system, or to affect itssafety or effectiveness.

National SemiconductorCorporationAmericasEmail: [email protected]

National SemiconductorEurope

Fax: +49 (0) 180-530 85 86Email: [email protected]

Deutsch Tel: +49 (0) 69 9508 6208English Tel: +44 (0) 870 24 0 2171Français Tel: +33 (0) 1 41 91 8790

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www.national.com

AD

C0808/A

DC

08098-B

itµP

Com

patibleA

/DC

onvertersw

ith8-C

hannelMultiplexer

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

TL/F/5971

CD

4049U

BM

/C

D4049U

BC

Hex

Invertin

gB

uffe

rC

D4050B

M/C

D4050B

CH

ex

Non-In

vertin

gB

uffe

r

March 1988

CD4049UBM/CD4049UBC Hex Inverting BufferCD4050BM/CD4050BC Hex Non-Inverting Buffer

General DescriptionThese hex buffers are monolithic complementary MOS

(CMOS) integrated circuits constructed with N- and P-chan-

nel enhancement mode transistors. These devices feature

logic level conversion using only one supply voltage (VDD).

The input signal high level (VIH) can exceed the VDD supply

voltage when these devices are used for logic level conver-

sions. These devices are intended for use as hex buffers,

CMOS to DTL/TTL converters, or as CMOS current drivers,

and at VDD e 5.0V, they can drive directly two DTL/TTL

loads over the full operating temperature range.

FeaturesY Wide supply voltage range 3.0V to 15VY Direct drive to 2 TTL loads at 5.0V over full tempera-

ture rangeY High source and sink current capabilityY Special input protection permits input voltages greater

than VDD

ApplicationsY CMOS hex inverter/bufferY CMOS to DTL/TTL hex converterY CMOS current ‘‘sink’’ or ‘‘source’’ driverY CMOS high-to-low logic level converter

Connection Diagrams

CD4049UBM/CD4049UBC


TL/F/5971–1

Top View

Order Number CD4049UB or CD4049B

CD4050BM/CD4050BC


TL/F/5971–2

Top View

Order Number CD4050UB or CD4050B

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage (VDD) b0.5V to a18V

Input Voltage (VIN) b0.5V to a18V

Voltage at Any Output Pin (VOUT) b0.5V to VDD a 0.5V

Storage Temperature Range (TS) b65§C to a150§CPower Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260§C

Recommended OperatingConditions (Note 2)

Supply Voltage (VDD) 3V to 15V

Input Voltage (VIN) 0V to 15V

Voltage at Any Output Pin (VOUT) 0 to VDD

Operating Temperature Range (TA)

CD4049UBM, CD4050BM b55§C to a125§CCD4049UBC, CD4050BC b40§C to a85§C

DC Electrical Characteristics CD4049M/CD4050BM (Note 2)

Symbol Parameter Conditionsb55§C a25§C a125§C

UnitsMin Max Min Typ Max Min Max

IDD Quiescent Device Current VDD e 5V 1.0 0.01 1.0 30 mA

VDD e 10V 2.0 0.01 2.0 60 mA

VDD e 15V 4.0 0.03 4.0 120 mA

VOL Low Level Output Voltage VIH e VDD, VIL e 0V,

lIOl k 1 mA

VDD e 5V 0.05 0 0.05 0.05 V

VDD e 10V 0.05 0 0.05 0.05 V

VDD e 15V 0.05 0 0.05 0.05 V

VOH High Level Output Voltage VIH e VDD, VIL e 0V,

lIOl k 1 mA

VDD e 5V 4.95 4.95 5 4.95 V

VDD e 10V 9.95 9.95 10 9.95 V

VDD e 15V 14.95 14.95 15 14.95 V

VIL Low Level Input Voltage lIOl k 1 mA

(CD4050BM Only) VDD e 5V, VO e 0.5V 1.5 2.25 1.5 1.5 V

VDD e 10V, VO e 1V 3.0 4.5 3.0 3.0 V

VDD e 15V, VO e 1.5V 4.0 6.75 4.0 4.0 V


(CD4049UBM Only) VDD e 5V, VO e 4.5V 1.0 1.5 1.0 1.0 V

VDD e 10V, VO e 9V 2.0 2.5 2.0 2.0 V

VDD e 15V, VO e 13.5V 3.0 3.5 3.0 3.0 V

VIH High Level Input Voltage lIOl k 1 mA

(CD4050BM Only) VDD e 5V, VO e 4.5V 3.5 3.5 2.75 3.5 V

VDD e 10V, VO e 9V 7.0 7.0 5.5 7.0 V

VDD e 15V, VO e 13.5V 11.0 11.0 8.25 11.0 V


(CD4049UBM Only) VDD e 5V, VO e 0.5V 4.0 4.0 3.5 4.0 V

VDD e 10V, VO e 1V 8.0 8.0 7.5 8.0 V

VDD e 15V, VO e 1.5V 12.0 12.0 11.5 12.0 V

IOL Low Level Output Current VIH e VDD, VIL e 0V

(Note 3) VDD e 5V, VO e 0.4V 5.6 4.6 5 3.2 mA

VDD e 10V, VO e 0.5V 12 9.8 12 6.8 mA

VDD e 15V, VO e 1.5V 35 29 40 20 mA

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices

should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device

operation.

Note 2: VSS e 0V unless otherwise specified.

Note 3: These arepeak output current capabilities. Continuous output current is rated at 12 mA maximum. The output current should not be allowed to exceed this

value for extended periods of time. IOL and IOH are tested one output at a time.

2

DC Electrical Characteristics CD4049M/CD4050BM (Note 2) (Continued)



IOH High Level Output Current VIH e VDD, VIL e 0V

(Note 3) VDD e 5V, VO e 4.6V b1.3 b1.1 b1.6 b0.72 mA

VDD e 10V, VO e 9.5V b2.6 b2.2 b3.6 b1.5 mA

VDD e 15V, VO e 13.5V b8.0 b7.2 b12 b5.0 mA

IIN Input Current VDD e 15V, VIN e 0V b0.1 b10b5 b0.1 b1.0 mA

VDD e 15V, VIN e 15V 0.1 10b5 0.1 1.0 mA



operation.




DC Electrical Characteristics CD4049UBC/CD4050BC (Note 2)



IDD Quiescent Device Current VDD e 5V 4 0.03 4.0 30 mA

VDD e 10V 8 0.05 8.0 60 mA

VDD e 15V 16 0.07 16.0 120 mA

VOL Low Level Output Voltage VIH e VDD, VIL e 0V,

lIOl k 1 mA

VDD e 5V 0.05 0 0.05 0.05 V

VDD e 10V 0.05 0 0.05 0.05 V

VDD e 15V 0.05 0 0.05 0.05 V

VOH High Level Output Voltage VIH e VDD, VIL e 0V,

lIOl k 1 mA

VDD e 5V 4.95 4.95 5 4.95 V

VDD e 10V 9.95 9.95 10 9.95 V

VDD e 15V 14.95 14.95 15 14.95 V


(CD4050BC Only) VDD e 5V, VO e 0.5V 1.5 2.25 1.5 1.5 V

VDD e 10V, VO e 1V 3.0 4.5 3.0 3.0 V

VDD e 15V, VO e 1.5V 4.0 6.75 4.0 4.0 V


(CD4049UBC Only) VDD e 5V, VO e 4.5V 1.0 1.5 1.0 1.0 V

VDD e 10V, VO e 9V 2.0 2.5 2.0 2.0 V

VDD e 15V, VO e 13.5V 3.0 3.5 3.0 3.0 V


(CD4050BC Only) VDD e 5V, VO e 4.5V 3.5 3.5 2.75 3.5 V

VDD e 10V, VO e 9V 7.0 7.0 5.5 7.0 V

VDD e 15V, VO e 13.5V 11.0 11.0 8.25 11.0 V


(CD4049UBC Only) VDD e 5V, VO e 0.5V 4.0 4.0 3.5 4.0 V

VDD e 10V, VO e 1V 8.0 8.0 7.5 8.0 V

VDD e 15V, VO e 1.5V 12.0 12.0 11.5 12.0 V



operation.




3

DC Electrical Characteristics CD4049UBC/CD4050BC (Note 2) (Continued)



IOL Low Level Output Current VIH e VDD, VIL e 0V

(Note 3) VDD e 5V, VO e 0.4V 4.6 4.0 5 3.2 mA

VDD e 10V, VO e 0.5V 9.8 8.5 12 6.8 mA

VDD e 15V, VO e 1.5V 29 25 40 20 mA

IOH High Level Output Current VIH e VDD, VIL e 0V

(Note 3) VDD e 5V, VO e 4.6V b1.0 b0.9 b1.6 b0.72 mA

VDD e 10V, VO e 9.5V b2.1 b1.9 b3.6 b1.5 mA

VDD e 15V, VO e 13.5V b7.1 b6.2 b12 b5 mA

IIN Input Current VDD e 15V, VIN e 0V b0.3 b0.3 b10b5 b1.0 mA

VDD e 15V, VIN e 15V 0.3 0.3 10b5 1.0 mA

AC Electrical Characteristics* CD4049UBM/CD4049UBC

TA e 25§C, CL e 50 pF, RL e 200k, tr e tf e 20 ns, unless otherwise specified


tPHL Propagation Delay Time VDD e 5V 30 65 ns

High-to-Low Level VDD e 10V 20 40 ns

VDD e 15V 15 30 ns

tPLH Propagation Delay Time VDD e 5V 45 85 ns

Low-to-High Level VDD e 10V 25 45 ns

VDD e 15V 20 35 ns

tTHL Transition Time VDD e 5V 30 60 ns


VDD e 15V 15 30 ns

tTLH Transition Time VDD e 5V 60 120 ns


VDD e 15V 25 45 ns

CIN Input Capacitance Any Input 15 22.5 pF

*AC Parameters are guaranteed by DC correlated testing.

AC Electrical Characteristics* CD4050BM/CD4050BC

TA e 25§C, CL e 50 pF, RL e 200k, tr e tf e 20 ns, unless otherwise specified


tPHL Propagation Delay Time VDD e 5V 60 110 ns


VDD e 15V 20 30 ns

tPLH Propagation Delay Time VDD e 5V 60 120 ns


VDD e 15V 25 45 ns

tTHL Transition Time VDD e 5V 30 60 ns


VDD e 15V 15 30 ns

tTLH Transition Time VDD e 5V 60 120 ns


VDD e 15V 25 45 ns

CIN Input Capacitance Any Input 5 7.5 pF

*AC Parameters are guaranteed by DC correlated testing.

4

Schematic DiagramsCD4049UBM/CD4049UBC

1 of 6 Identical Units

TL/F/5971–3

CD4050BM/CD4050BC

1 of 6 Identical Units

TL/F/5971–4

Switching Time Waveforms

TL/F/5971–5

Typical Applications

CMOS to TTL or CMOS at a Lower VDD

TL/F/5971–6Note: VDD1 t VDD2

Note: In the case of the CD4049UBM/CD4049UBC

the output drive capability increases with increasing

input voltage. E.g., If VDD1 e 10V the CD4049UBM/

CD4049UBC could drive 4 TTL loads.

5

CD

4049U

BM

/C

D4049U

BC

Hex

Invert

ing

Buff

er

CD

4050B

M/C

D4050B

CH

ex

Non-Invert

ing

Buff

er

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4049UBMJ, CD4049UBCJ, CD4049BMJ or CD4049BCJ

NS Package Number J16A

Molded Dual-In-Line Package (N)

Order Number CD4050BMN, CD4050BCN, CD4050BMN or CD4050BCN

NS Package Number N16E

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or 2. A critical component is any component of a life

systems which, (a) are intended for surgical implant support device or system whose failure to perform can

into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life

failure to perform, when properly used in accordance support device or system, or to affect its safety or

with instructions for use provided in the labeling, can effectiveness.

be reasonably expected to result in a significant injury

to the user.

National Semiconductor National Semiconductor National Semiconductor National SemiconductorCorporation Europe Hong Kong Ltd. Japan Ltd.1111 West Bardin Road Fax: (a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309Arlington, TX 76017 Email: cnjwge@ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408Tel: 1(800) 272-9959 Deutsch Tel: (a49) 0-180-530 85 85 Tsimshatsui, KowloonFax: 1(800) 737-7018 English Tel: (a49) 0-180-532 78 32 Hong Kong

Fran3ais Tel: (a49) 0-180-532 93 58 Tel: (852) 2737-1600Italiano Tel: (a49) 0-180-534 16 80 Fax: (852) 2736-9960

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

II. VHDL source codes

-- Module Name: ADC_interface - Behavioral

-- Project Name: ADE_final

-- Target Devices: Spartan 3E

-- Tool versions:

-- Description: Acquisition of data from sensors through four data channels of the 8 channel ADC

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ADC_interface is

Port ( clk : in STD_LOGIC;

clk_out : out STD_LOGIC;

cali0 : in STD_LOGIC;


address : out STD_LOGIC_VECTOR (2 downto 0);

ALE : out STD_LOGIC;

SC : out STD_LOGIC;

OE : out STD_LOGIC;

EOC : in STD_LOGIC;

Reset : in STD_LOGIC;

tx : out STD_LOGIC;

data : in STD_LOGIC_VECTOR (7 downto 0);

--mark_no : out STD_LOGIC_VECTOR(1 downto 0);

result_qno: out STD_LOGIC_VECTOR(7 downto 0));

end ADC_interface;

architecture Behavioral of ADC_interface is

component data_acquisition is

Port( clk : in STD_LOGIC;


clk_out : in STD_LOGIC;



nextoption : in STD_LOGIC;

tx : out STD_LOGIC;

reg_temp : in STD_LOGIC_VECTOR(7 downto 0);

option : out STD_LOGIC_VECTOR(2 downto 0);


result_qno : out STD_LOGIC_VECTOR(7 downto 0));

end component;

signal nextoption : STD_LOGIC :='0';

signal option : STD_LOGIC_VECTOR(2 downto 0):="000";

signal reg_temp : STD_LOGIC_VECTOR(7 downto 0);

signal nextstate,prstate : INTEGER range 0 to 12:=0;

signal praddress, nxaddress : STD_LOGIC_VECTOR(2 downto 0); --present and next values to remove latch synthesis

signal prreg,nextreg : STD_LOGIC_VECTOR(7 downto 0); --same as above

signal clk_temp: STD_LOGIC:='0';

begin

U1: data_acquisition Port Map(clk, Reset, clk_temp, cali0, cali1, nextoption, tx, reg_temp, option, result_qno);

process(clk)

variable count: INTEGER range 0 to 49;

begin

if(clk'event and clk='1') then

if(count=49) then

clk_temp<= NOT clk_temp;

count:=0;

else

count:=count+1;

end if;

end if;

end process;

clk_out<=clk_temp;

process (clk_temp,Reset)

begin

if (Reset='1') then

prstate<=0;

elsif(clk_temp'event and clk_temp='1') then

prstate<=nextstate;

praddress<=nxaddress;

prreg<=nextreg;

end if;

end process;

address<=praddress;

reg_temp<=prreg;

process(prstate,EOC,option,data,praddress,prreg)

begin

ALE<='0';

OE<='0';

SC<='0';

nextoption<='0';

nxaddress<=praddress;

nextreg<=prreg;

case prstate is

when 0=>

ALE<='0';

OE<='0';

SC<='0';

nextstate<=1;

when 1=>

nxaddress<=option;

nextstate<=2;

when 2=>

nextstate<=3;

when 3=>

ALE<='1';

nextstate<=4;

when 4=>

ALE<='1';

SC<='1';

nextstate<=5;

when 5=>

ALE<='0';

SC<='1';

nextstate<=6;

when 6=>

SC<='0';

nextstate<=7;

when 7=>

if(EOC='0') then

nextstate<=8;

else

nextstate<=7;

end if;

when 8=>

if(EOC='1') then

nextstate<=9;

else

nextstate<=8;

end if;

when 9=>

OE<='1';

nextstate<=10;

when 10=>

nextreg<=data;

nextstate<=11;

when 11=>

nextoption<='1';

if(option = "011") then

nextstate<=12;

else

nextstate<=0;

end if;

when 12=>

nextstate<=12;

end case;

end process;

end Behavioral;

-- Module Name: data_processcopy - Behavioral

-- Description: storage and processing of data acquired, inside the FPGA

----------------------------------------------------------------------------------

library IEEE;




use IEEE.NUMERIC_STD.ALL;

use WORK.MY_DATA_TYPES.ALL;



--library UNISIM;


entity data_acquisition is



clk_out : in STD_LOGIC;



nextoption : in STD_LOGIC;

tx : out STD_LOGIC;

reg_temp : in STD_LOGIC_VECTOR(7 downto 0);

option : out STD_LOGIC_VECTOR(2 downto 0);



end data_acquisition;

architecture Behavioral of data_acquisition is

component data_process is

port( clk : in STD_LOGIC;




process_en : in STD_LOGIC;

rowdata : in row;

process_clk : in STD_LOGIC;

tx : out STD_LOGIC;



end component;

signal rowdata : row;

signal process_en : STD_LOGIC;

signal process_clk : STD_LOGIC;

signal option_temp : STD_LOGIC_VECTOR(2 downto 0);

signal nextstate1,prstate1: INTEGER range 0 to 4 :=0;

begin

U2 : data_process Port Map(clk, Reset, cali0, cali1, process_en, rowdata, process_clk, tx, result_qno);

process(clk_out,Reset,nextoption)

begin

if (Reset='1') then

prstate1<=0;

elsif(clk_out'event and clk_out='1') then

if(nextoption='1') then

rowdata(conv_integer(option_temp(1 downto 0)))<=reg_temp;

prstate1<=nextstate1;

else

end if;

end if;

end process;

process_clk<=clk_out;

process(prstate1)

begin

process_en<='0';

case prstate1 is

when 0=>

option_temp<="000";

nextstate1<=1;

when 1=>

option_temp<="001";

nextstate1<=2;

when 2=>

option_temp<="010";

nextstate1<=3;

when 3=>

option_temp<="011";

nextstate1<=4;

when 4=>

process_en<='1';

option_temp<="011";

nextstate1<=4;

end case;

end process;

option<=option_temp;

end Behavioral;

-- Module Name: dataprocess - Behavioral

-- Additional Comments: next values in signals are used to remove inferred latches

--

----------------------------------------------------------------------------------

library IEEE;




use WORK.MY_DATA_TYPES.ALL;



--library UNISIM;


entity data_process is

port( clk : in STD_LOGIC;




process_en : in STD_LOGIC;

rowdata : in row;

process_clk : in STD_LOGIC;

tx : out STD_LOGIC;



end data_process;

architecture Behavioral of data_process is

component serial_tx is


reset : in STD_LOGIC;

tx_start : in STD_LOGIC;--if high state changes to start else remain idle

tick_out: out STD_LOGIC;

count_out: out STD_LOGIC_VECTOR(7 downto 0);

din : in STD_LOGIC_VECTOR (7 downto 0);

tx : out STD_LOGIC;

tx_done_tick : out STD_LOGIC);

end component;

signal nxThreshold1, Threshold1, nxThreshold2, Threshold2: INTEGER range 0 to 127; --dynamic threshold values

signal prwhite_mark_val, prdark_mark_val, nxwhite_mark_val, nxdark_mark_val : INTEGER range -512 to 512;

signal result_8bit : STD_LOGIC_VECTOR(7 downto 0);

signal tx_done_tick : STD_LOGIC;

signal pr_qno, nx_qno : STD_LOGIC_VECTOR(3 downto 0);

signal tick_out : STD_LOGIC;

signal count_out : STD_LOGIC_VECTOR(7 downto 0);

signal pr_process_complete, nx_process_complete : STD_LOGIC;

signal max_adj, min_adj, next_max_adj, next_min_adj : rowint; --adjust values for large and small data

signal next_temp_addition_register, temp_addition_register : INTEGER range -512 to 512;

signal nextstate2,prstate2: INTEGER range 0 to 10 :=0;

signal next_temp_rowdata, temp_rowdata : rowintp; --temporary adjusted voltages for processing

signal darkest_val, nextdarkest_val : INTEGER range 0 to 3;

signal diff0, diff1, diff2, ndiff0, ndiff1, ndiff2 : INTEGER range 0 to 512; --difference values

signal next_result, pr_result : STD_LOGIC_VECTOR(3 downto 0); --final result

signal cal : STD_LOGIC_VECTOR(1 downto 0);

begin

U3: serial_tx Port Map(clk, Reset, nx_process_complete, tick_out, count_out, result_8bit, tx, tx_done_tick);

process(process_clk,process_en,Reset)

begin

if(Reset='1') then

prstate2<=0;

pr_process_complete<='0';

elsif(process_clk'event and process_clk='1') then

if(process_en='1') then

Threshold1<=nxThreshold1;

Threshold2<=nxThreshold2;

prwhite_mark_val<=nxwhite_mark_val;

prdark_mark_val<=nxdark_mark_val;

pr_qno<=nx_qno;

pr_process_complete<=nx_process_complete;

pr_result<=next_result;

diff0<=ndiff0;

diff1<=ndiff1;

diff2<=ndiff2;

darkest_val<=nextdarkest_val;

max_adj<=next_max_adj;

min_adj<=next_min_adj;

temp_rowdata<=next_temp_rowdata;

temp_addition_register<=next_temp_addition_register;

prstate2<=nextstate2;

end if;

end if;

end process;

process(prstate2,rowdata,cali0,cali1,darkest_val,diff0,diff1,diff2,max_adj,min_adj,temp_rowdata,temp_addition_register,pr_result,pr_process_complete,tx_done_tick)

begin

nx_qno<=pr_qno;

cal<=cali1 & cali0;

nxThreshold2<=Threshold2;

nxThreshold1<=Threshold1;

nxwhite_mark_val<=prwhite_mark_val;

nxdark_mark_val<=nxdark_mark_val;

next_result<=pr_result;

next_max_adj<=max_adj;

next_min_adj<=min_adj;

next_temp_rowdata<=temp_rowdata;

next_temp_addition_register<=temp_addition_register;

nextdarkest_val<=darkest_val;

ndiff0<=diff0;

ndiff1<=diff1;

ndiff2<=diff2;

nx_process_complete<=pr_process_complete;

case prstate2 is

when 0=>

nx_process_complete<='0';

next_temp_addition_register<=conv_integer(rowdata(0)) + conv_integer(rowdata(1)) + conv_integer(rowdata(2)) + conv_integer(rowdata(3));

nextstate2<=1;

when 1=> --redundant state to ensure update of temp_addition_register

nextstate2<=2;

when 2=> --finding calibration constants and adjusting readings

if (cal="01") then --finding calibration constant for dark reading

for i in 0 to 3 loop

next_max_adj(i)<= (temp_addition_register/4)-conv_integer(rowdata(i)); --shifting right by 2 bits and subtracting

end loop;

nx_qno<="0000";

nxdark_mark_val<=temp_addition_register/4;

nextstate2<=10;

elsif(cal="10" or cal="11") then --finding calibration constant for white reading


next_min_adj(i)<= (temp_addition_register/4)-conv_integer(rowdata(i)); --shifting right by 2 bits and subtracting

end loop;

nx_qno<="0000";

nxwhite_mark_val<=temp_addition_register/4;

nextstate2<=10;

else --adjust readings if not in calibration mode


if(rowdata(i)> Threshold1) then

next_temp_rowdata(i)<=conv_integer(rowdata(i)) + max_adj(i);

else

next_temp_rowdata(i)<=conv_integer(rowdata(i)) + min_adj(i);

end if;

end loop;

nextstate2<=3;

end if;

when 3=> --redundant state to ensure update of temp_rowdata

nextstate2<=4;

when 4=> --finding darkest reading after calibration

if (temp_rowdata(0)>temp_rowdata(1)) then



nextdarkest_val<=0;

else

nextdarkest_val<=3;

end if;

else


nextdarkest_val<=2;

else

nextdarkest_val<=3;

end if;

end if;

else



nextdarkest_val<=1;

else

nextdarkest_val<=3;

end if;

else


nextdarkest_val<=2;

else

nextdarkest_val<=3;

end if;

end if;

end if;

nextstate2<=5;

when 5=> --redundant state to ensure update of darkest_val

nextstate2<=6;

when 6=> --finding voltage differences w.r.t. darkest reading

if(darkest_val=0) then

ndiff0<=temp_rowdata(0)-temp_rowdata(1);



elsif(darkest_val=1) then








else




end if;

if(temp_rowdata(darkest_val)< prwhite_mark_val+15) then

nxThreshold2<=10;

else

nxThreshold2<=temp_rowdata(darkest_val)-(prwhite_mark_val+40);

end if;

nxThreshold1<=prwhite_mark_val+6;

nextstate2<=7;

when 7=> --redundant state to ensure update of ndiff's

nextstate2<=8;

when 8=> --comparing differences and darkest reading with threshold levels

if (temp_rowdata(darkest_val)<Threshold1) then

next_result<="1001";

elsif (diff0>Threshold2 and diff1>Threshold2 and diff2>Threshold2) then

if(darkest_val=0) then






else


end if;

else


end if;

nextstate2<=9;

when 9=>


nx_qno<=pr_qno + 1;

nextstate2<=10;

when 10=> --system stops and stays idle at this state until next Reset

if(tx_done_tick='1') then


end if;

nextstate2<=10;

end case;

end process;

--mark_no<=conv_std_logic_vector(darkest_val, 2);

result_8bit<=pr_qno & pr_result;

result_qno<=result_8bit;

end Behavioral;

-- Module Name: serial_tx - serial_tx_arch

----------------------------------------------------------------------------------

library IEEE;






--library UNISIM;


entity serial_tx is


reset : in STD_LOGIC;

tx_start : in STD_LOGIC;--if high state changes to start else remain idle

tick_out:out std_logic;

count_out:out std_logic_vector(7 downto 0);

din : in STD_LOGIC_VECTOR (7 downto 0);

tx : out STD_LOGIC;

tx_done_tick : out STD_LOGIC);

end serial_tx;

architecture serial_tx_arch of serial_tx is

type state_type is (idle, start, data, stop);

signal state_present, state_next : state_type;

signal counterS_present,counterS_next : unsigned (3 downto 0) ;

signal counterN_present,counterN_next : unsigned (2 downto 0) ;

signal regB_present,regB_next : std_logic_vector (7 downto 0) ;

signal tx_present , tx_next : std_logic ;

signal clk_tick:std_logic:='0';

signal count: unsigned(7 downto 0);

begin

process(clk, reset)

begin

if reset='1' then

state_present<=idle;

counterS_present<=(others=>'0');

counterN_present<=(others=>'0');

regB_present <=(others=>'0');

tx_present<='1';

count<=(others=>'0');

clk_tick<='0';

elsif( clk'event and clk='1') then

state_present<=state_next;

counterS_present<=counterS_next;--counts to 7 in start bit,15 in databit

counterN_present<=counterN_next;--counts no of data bits in a frame

regB_Present<=regB_next;

tx_present<= tx_next;

--if(tx_start='1') then

if(count=162) then

clk_tick<='1';--not clk_tick ;

count<=(others=>'0');

else

count<=count+1;

clk_tick<='0';

end if;

--end if;

end if;

count_out<=std_logic_vector(count);

end process;

tick_out<=clk_tick;

-- next-state logic & data path functional units /routing

process(state_present,counterS_present,counterN_present,regB_present,clk_tick,

tx_present,tx_start,din)

begin

state_next<=state_present;

counterS_next<=counterS_present;

counterN_next<=counterN_present;

regB_next<=regB_present;

tx_next<=tx_present;

tx_done_tick<='0';

case state_present is

when idle =>

tx_next<='1';

if(tx_start='1') then

state_next<=start;

regB_next<=din;

counterS_next<=(others=>'0');

end if;

when start=>

tx_next<='0';

--always check present state values to update next state values

if(clk_tick='1') then

--if( clk_tick'event and clk_tick='0') then

if counterS_present=15 then

state_next<=data;


counterN_next<=(others=>'0');

else

counterS_next<=counterS_present+1;

end if;

end if;

when data=>

tx_next<=regB_present(0);--the lSB of the data din

--if(clk_tick'event) then





--to eliminate the LSB once it is assinged to tx_next

regB_next<=('0'& regB_present(7 downto 1)) ;

--to count data serial databits

if counterN_present=7 then

state_next<=stop;

counterN_next<=(others=>'0');

else

counterN_next<=counterN_present+1;

end if;

else


end if;

end if;

when stop=>

tx_next<='1';

--if(clk_tick'event) then




state_next<=stop;


--counterN_next<=(others=>'0');

tx_done_tick<='1';

else


end if;

end if;

end case;

end process;

--tick_out<=s_tick;

tx<=tx_present;

end serial_tx_arch;

--Design Name: final_tb

--Device: Xilinx

--

library IEEE;




USE IEEE.STD_LOGIC_TEXTIO.ALL;

USE STD.TEXTIO.ALL;

ENTITY final_tb IS

END final_tb;

ARCHITECTURE testbench_arch OF final_tb IS

FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

COMPONENT ADC_interface

PORT (

clk : In std_logic;

clk_out : Out std_logic;

cali0 : In std_logic;

cali1 : In std_logic;

address : Out std_logic_vector (2 DownTo 0);

ALE : Out std_logic;

SC : Out std_logic;

OE : Out std_logic;

EOC : In std_logic;

Reset : In std_logic;

tx : Out std_logic;

data : In std_logic_vector (7 DownTo 0);

mark_no : Out std_logic_vector (1 DownTo 0);

result : Out std_logic_vector (3 DownTo 0)

);

END COMPONENT;

SIGNAL clk : std_logic := '0';

SIGNAL clk_out : std_logic := '0';

SIGNAL cali0 : std_logic := '0';

SIGNAL cali1 : std_logic := '0';

SIGNAL address : std_logic_vector (2 DownTo 0) := "000";

SIGNAL ALE : std_logic := '0';

SIGNAL SC : std_logic := '0';

SIGNAL OE : std_logic := '0';

SIGNAL EOC : std_logic := '0';

SIGNAL Reset : std_logic := '0';

SIGNAL tx : std_logic := '0';

SIGNAL data : std_logic_vector (7 DownTo 0) := "00000000";

SIGNAL mark_no : std_logic_vector (1 DownTo 0) := "00";

SIGNAL result : std_logic_vector (3 DownTo 0) := "0000";

constant PERIOD : time := 20 ns;

constant DUTY_CYCLE : real := 0.5;

constant OFFSET : time := 0 ns;

BEGIN

UUT : ADC_interface

PORT MAP (

clk => clk,

clk_out => clk_out,

cali0 => cali0,

cali1 => cali1,

address => address,

ALE => ALE,

SC => SC,

OE => OE,

EOC => EOC,

Reset => Reset,

tx => tx,

data => data,

mark_no => mark_no,

result => result

);

PROCESS -- clock process for clk

BEGIN

WAIT for OFFSET;

CLOCK_LOOP : LOOP

clk <= '0';

WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));

clk <= '1';

WAIT FOR (PERIOD * DUTY_CYCLE);

END LOOP CLOCK_LOOP;

END PROCESS;

PROCESS

BEGIN

-- ------------- Current Time: 105ns

WAIT FOR 105 ns;

EOC <= '1';

-- -------------------------------------

-- ------------- Current Time: 14665ns

WAIT FOR 14560 ns;

EOC <= '0';

-- -------------------------------------

-- ------------- Current Time: 28085ns

WAIT FOR 13420 ns;

data <= "10010000";

-- -------------------------------------

-- ------------- Current Time: 32285ns

WAIT FOR 4200 ns;

EOC <= '1';

-- -------------------------------------

-- ------------- Current Time: 51165ns

WAIT FOR 18880 ns;

EOC <= '0';

-- -------------------------------------

-- ------------- Current Time: 64165ns

WAIT FOR 13000 ns;

data <= "10110000";

-- -------------------------------------

-- ------------- Current Time: 68345ns

WAIT FOR 4180 ns;

EOC <= '1';

-- -------------------------------------

-- ------------- Current Time: 85965ns

WAIT FOR 17620 ns;

EOC <= '0';

-- -------------------------------------

-- ------------- Current Time: 99385ns

WAIT FOR 13420 ns;

data <= "10110101";

-- -------------------------------------

-- ------------- Current Time: 103165ns

WAIT FOR 3780 ns;

EOC <= '1';

-- -------------------------------------

-- ------------- Current Time: 121205ns

WAIT FOR 18040 ns;

EOC <= '0';

-- -------------------------------------

-- ------------- Current Time: 128325ns

WAIT FOR 7120 ns;

cali0 <= '1';

-- -------------------------------------

-- ------------- Current Time: 130425ns

WAIT FOR 2100 ns;

data <= "10101111";

-- -------------------------------------

-- ------------- Current Time: 135465ns

WAIT FOR 5040 ns;

EOC <= '1';

-- -------------------------------------

-- ------------- Current Time: 157265ns

WAIT FOR 21800 ns;

Reset <= '1';

-- -------------------------------------

-- ------------- Current Time: 163145ns

WAIT FOR 5880 ns;

cali0 <= '0';

-- -------------------------------------

-- ------------- Current Time: 164805ns

WAIT FOR 1660 ns;

Reset <= '0';

-- -------------------------------------

-- ------------- Current Time: 182005ns

WAIT FOR 17200 ns;

EOC <= '0';

-- -------------------------------------

-- ------------- Current Time: 197945ns

WAIT FOR 15940 ns;

data <= "01100000";

-- -------------------------------------

-- ------------- Current Time: 201305ns

WAIT FOR 3360 ns;

EOC <= '1';

-- -------------------------------------

-- ------------- Current Time: 218085ns

WAIT FOR 16780 ns;

EOC <= '0';

-- -------------------------------------

-- ------------- Current Time: 231505ns

WAIT FOR 13420 ns;

EOC <= '1';

-- -------------------------------------

-- ------------- Current Time: 247845ns

WAIT FOR 16340 ns;

EOC <= '0';

-- -------------------------------------

-- ------------- Current Time: 258765ns

WAIT FOR 10920 ns;

EOC <= '1';

-- -------------------------------------

-- ------------- Current Time: 271765ns

WAIT FOR 13000 ns;

EOC <= '0';

-- -------------------------------------

-- ------------- Current Time: 282245ns

WAIT FOR 10480 ns;

EOC <= '1';

-- -------------------------------------

WAIT FOR 37775 ns;

END PROCESS;

END testbench_arch;

III. MATLAB source codes

GUI development in MATLAB

function varargout = ADE(varargin)

% ADE M-file for ADE.fig

% ADE, by itself, creates a new ADE or raises the existing

% singleton*.

%

% H = ADE returns the handle to a new ADE or the handle to

% the existing singleton*.

%

% ADE('CALLBACK',hObject,eventData,handles,...) calls the local

% function named CALLBACK in ADE.M with the given input arguments.

%

% ADE('Property','Value',...) creates a new ADE or raises the

% existing singleton*. Starting from the left, property value pairs are

% applied to the GUI before ADE_OpeningFunction gets called. An

% unrecognized property name or invalid value makes property application

% stop. All inputs are passed to ADE_OpeningFcn via varargin.

%

% *See GUI Options on GUIDE's Tools menu. Choose "GUI allows only one

% instance to run (singleton)".

%

% See also: GUIDE, GUIDATA, GUIHANDLES

% Copyright 2002-2003 The MathWorks, Inc.

% Edit the above text to modify the response to help ADE

% Last Modified by GUIDE v2.5 23-Mar-2009 13:12:08

% Begin initialization code - DO NOT EDIT

gui_Singleton = 1;

gui_State = struct('gui_Name', mfilename, ...

'gui_Singleton', gui_Singleton, ...

'gui_OpeningFcn', @ADE_OpeningFcn, ...

'gui_OutputFcn', @ADE_OutputFcn, ...

'gui_LayoutFcn', [] , ...

'gui_Callback', []);

if nargin && ischar(varargin1)

gui_State.gui_Callback = str2func(varargin1);

end

if nargout

[varargout1:nargout] = gui_mainfcn(gui_State, varargin:);

else

gui_mainfcn(gui_State, varargin:);

end

% End initialization code - DO NOT EDIT

% --- Executes just before ADE is made visible.

function ADE_OpeningFcn(hObject, eventdata, handles, varargin)

% This function has no output args, see OutputFcn.

% hObject handle to figure

% eventdata reserved - to be defined in a future version of MATLAB

% handles structure with handles and user data (see GUIDATA)

% varargin command line arguments to ADE (see VARARGIN)

conn=database('exam','root','');

curs=exec(conn,['SELECT ALL roll_no,name,obtained_marks FROM result ORDER BY obtained_marks DESC']);

curs=fetch(curs);

data=curs.data;

colnames = 'Roll NO.', 'Name', 'Obtained Marks';

t = uitable(data, colnames,'ColumnWidth',98,'Position', [21,36,290,250]);

set(t,'Editable',0,'Visible',1);

% Choose default command line output for ADE

handles.output = hObject;

% Update handles structure

guidata(hObject, handles);

% UIWAIT makes ADE wait for user response (see UIRESUME)

% uiwait(handles.figure1);

% --- Outputs from this function are returned to the command line.

function varargout = ADE_OutputFcn(hObject, eventdata, handles)

% varargout cell array for returning output args (see VARARGOUT);

% hObject handle to figure



% Get default command line output from handles structure

varargout1 = handles.output;

% --------------------------------------------------------------------

function Untitled_1_Callback(hObject, eventdata, handles)

% hObject handle to Untitled_1 (see GCBO)




curs=exec(conn,['SELECT ALL roll_no,name,obtained_marks FROM result ORDER BY obtained_marks DESC']);

curs=fetch(curs);

data=curs.data;




% --------------------------------------------------------------------






curs=exec(conn,['SELECT ALL roll_no,name,obtained_marks FROM result ORDER BY name ASC']);

curs=fetch(curs);

data=curs.data;




function search_Callback(hObject, eventdata, handles)

% hObject handle to search (see GCBO)



% Hints: get(hObject,'String') returns contents of search as text

% str2double(get(hObject,'String')) returns contents of search as a double

% --- Executes during object creation, after setting all properties.

function search_CreateFcn(hObject, eventdata, handles)

% hObject handle to search (see GCBO)


% handles empty - handles not created until after all CreateFcns called

% Hint: edit controls usually have a white background on Windows.

% See ISPC and COMPUTER.

if ispc

set(hObject,'BackgroundColor','white');

else

set(hObject,'BackgroundColor',get(0,'defaultUicontrolBackgroundColor'));

end

% --- Executes on selection change in popupmenu1.

function popupmenu1_Callback(hObject, eventdata, handles)

% hObject handle to popupmenu1 (see GCBO)



% Hints: contents = get(hObject,'String') returns popupmenu1 contents as cell array

% contentsget(hObject,'Value') returns selected item from popupmenu1


function popupmenu1_CreateFcn(hObject, eventdata, handles)

% hObject handle to popupmenu1 (see GCBO)



% Hint: popupmenu controls usually have a white background on Windows.


if ispc


else


end

% --- Executes on button press in go.

function go_Callback(hObject, eventdata, handles)

% hObject handle to go (see GCBO)




n=get(handles.search,'String');

%n='bikram';

value=get(handles.popupmenu1,'Value');

string=get(handles.popupmenu1,'String');

set(handles.search,'String',n);

switch stringvalue

case 'By Name'

curs=exec(conn,['select roll_no,name,obtained_marks from result where name like ''',n,'''']);

case 'By Roll No.'

curs=exec(conn,['select roll_no,name,obtained_marks from result where roll_no=''',n,'''']);

end

curs=fetch(curs);

data=curs.data;

[a,b]=size(data);


switch b

case 3



otherwise

errordlg('No Match Found in Database','Not Found');

end

% --- Executes on button press in read.

function read_Callback(hObject, eventdata, handles)

% hObject handle to read (see GCBO)



%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

s = serial('COM1');

set(s,'BaudRate',19200);

fopen(s);

true_result=1;

out = fscanf(s)

fclose(s);

delete(s);

clear s;

a=uint8(out);

b=a/16;

d='false';

c=a-b*16;

if(c==1)

d='true';

end

op='invalid';

if(c==1)

op='a';

elseif(c==2)

op='b';

elseif(c==4)

op='c';

elseif(c==8)

op='d';

end

%data=b,c,d;

%%%%%%%%%%%%%%%%%%%

upload=a/16,op,d;


insert(conn,'answer_sheet','qn','option_chosed','result',upload);

curs=exec(conn,['select qn,option_chosed,result from answer_sheet']);

curs=fetch(curs);

data=curs.data;

colnames = 'QN', 'op_chosen','result';

t = uitable(upload, colnames,'ColumnWidth',60,'Position', [350,90,185,200]);


%set(handles.roll,'String',roll_no);

%set(handles.marks,'String',marks);

% --- Executes on button press in upload.

function upload_Callback(hObject, eventdata, handles)

% hObject handle to upload (see GCBO)



%data=get(handles.roll,'string'),get(handles.marks,'string');

%conn=database('exam','root','');

%insert(conn,'result','roll_no','obtained_marks',data);

set(handles.message,'String','successfully uploaded');

function roll_Callback(hObject, eventdata, handles)

% hObject handle to roll (see GCBO)



% Hints: get(hObject,'String') returns contents of roll as text

% str2double(get(hObject,'String')) returns contents of roll as a double


function roll_CreateFcn(hObject, eventdata, handles)

% hObject handle to roll (see GCBO)





if ispc


else


end

function marks_Callback(hObject, eventdata, handles)

% hObject handle to marks (see GCBO)



% Hints: get(hObject,'String') returns contents of marks as text

% str2double(get(hObject,'String')) returns contents of marks as a double


function marks_CreateFcn(hObject, eventdata, handles)

% hObject handle to marks (see GCBO)





if ispc


else


end

% --------------------------------------------------------------------






curs=exec(conn,['SELECT ALL roll_no,name,obtained_marks FROM result ORDER BY roll_no ASC']);

curs=fetch(curs);

data=curs.data;




% --- Executes on button press in pushbutton7.

function pushbutton7_Callback(hObject, eventdata, handles)

% hObject handle to pushbutton7 (see GCBO)



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