Flipped Voltage Follower Low Dropout (LDO)Voltage Regulators: A Tutorial Overview

(Invited Tutorial)

Punith R. Surkanti, Annajirao Garimella and Paul M. FurthVLSI Laboratory, Klipsch School of Electrical and Computer Engineering

New Mexico State University, Las Cruces, NM, USApunith@nmsu.edu

Abstract—This tutorial introduces flipped voltage follower(FVF) based low dropout voltage regulators (LDOs) and theirrecent advances in the literature. Conventional stand-alone LDOICs often deploy an external output capacitor in the range ofhundreds of nanofarads to tens of microfarads with an inherentequivalent series resistance (ESR) in order to attain stability andlow overshoot and undershoot during load transients. Becauseof the large value of the output capacitor, the bandwidth ofthe LDO is often limited. Higher SoC integration and thenecessity to reduce bill of materials cost has resulted in theproliferation of low-value on-chip capacitor LDOs. One of themajor requirements of on-chip capacitor LDOs is to achieve highbandwidth and, thereby, good power supply rejection ratio.

An FVF is an analog voltage buffer circuit with fast localfeedback, resulting in high bandwidth. It is capable of sourcingheavy current loads, which makes it an ideal candidate for LDOs.The architecture and design details, such as pole-zero equations,stability, and output impedance, of FVF LDOs are dealt with indetail in this tutorial.

Index Terms—Low dropout voltage regulators (LDOs), Flippedvoltage follower (FVF), common-drain transistor amplifier, pole-zero analysis, stability, output impedance, PSRR.

I. INTRODUCTION

The objective of this paper is to elucidate the basic archi-tecture and some of the recent advances in flipped voltagefollower (FVF) based low dropout voltage regulators (LDOs).FVF LDOs are also compared to conventional multi-stageLDO architectures.

A. Conventional Output Dominant Pole LDO

Conventional stand-alone LDO ICs require a huge off-chipoutput capacitor COUT in the range of hundreds of nanofaradsto tens of microfarads in order to attain stability and lowovershoot and undershoot during load transients. COUT createsa load tracking low-frequency dominant pole, whereas a non-dominant pole is created at the gate of the pass transistor.The equivalent series resistance (ESR) of the off-chip outputcapacitor RESR creates a left-half-plane (LHP) zero, whichhelps in cancelling the non-dominant pole and improve thestability of the LDO. Because of the high output capacitorvalue, the bandwidth of the LDO is lower and the transientresponse is slow [1]–[40].

In a closed-loop system, power supply rejection ratio(PSRR) is proportional to the open-loop gain of the system, to

a first order. In conventional LDOs, the DC open-loop gain ishigh; therefore, the low frequency PSRR is high. Because ofthe LDO’s low bandwidth, the PSRR begins to drop at a lowfrequency. Beyond the unity gain frequency (UGF), where theopen-loop gain is less than unity, the PSRR depends on theoutput capacitor COUT alone.

In modern systems the usage of high switching frequencyDC-DC converters are increasing in order to reduce the sizeof the passive elements. These switching converters convertthe main variable supply to a regulated voltage and thereaftermultiple LDOs are used to generate a quieter low-ripple supplyvoltage to several points-of-load (POLs). Therefore, LDOs areoften required to have good PSRR at high frequencies in orderto attenuate the high-frequency switching noise introduced bythe DC-DC converters.

Most circuits in portable applications operate with low inputvoltage. Therefore, POL supply generators operating with low-voltage headroom are gaining importance. Due to bill ofmaterials (BOM) cost, size and integration requirements, SoCdesigners are restricted to architectures which require feweroff-chip components and input-output (IO) pins. Integrated on-chip capacitor LDOs satisfy these demands [41].

B. Integrated On-Chip Capacitor LDO with Internal Domi-nant Pole

The architecture of an integrated on-chip output capacitorLDO is shown in Fig. 1. It consists of a bandgap reference, anoperational transconductance amplifier (OTA) with transcon-

MPASS

b

CEAREA

BandgapVBG

gm1 gBU

VLINE

VLDO

COUT

CGS,P

CGD,P

Dominant

pole

Load tracking

non-dominant

pole

High-frequency

pole

VEA VGP

VFB

Bandgap Error Amplifier BufferPass Transistor

and Feedback

Output

Capacitor

Varying

Load

ILOADRESR

Fig. 1: On-chip capacitor LDO architecture with internal dominant pole situated at theoutput of error amplifier gm1.

ductance gm1, cascaded with a buffer driving the gate of apass transistor MPASS . The scaled output voltage VFB is fedback to the OTA in a negative feedback loop that regulatesthe output voltage VLDO based on the bandgap voltage VBGand scale factor β. The regulation of the LDO output voltagedepends on the open-loop gain. Since the LDO drives heavyoutput loads, the gain of the output-stage common-sourceamplifier created by MPASS is low. Therefore, the input-stage OTA needs to have high gain in order to achieve a highloop gain, even at heavy loads [12], [16]. In addition, highloop bandwidth helps reduce the load transient overshoot andundershoot and allows the LDO output to settle faster.

wP1

wP2

wP3

|AV|

with load

change

Freq

Heavy current load

Light current load

Fig. 2: Frequency magnitude response of an integrated on-chip capacitor LDO of Fig. 1with pole-zero locations for light and heavy load current conditions. Not drawn to scale.

The pole associated with the output node is non-dominantand tracks with the load. The gate capacitance associatedwith MPASS is often high. Depending on the resistance atnode VGP , the pole associated with that node could becomea low frequency dominant pole, limiting the bandwidth. In-serting a buffer gBU with a low output impedance movesthe pole associated with the gate of the MPASS to highfrequencies [16], [23]. Due to the low input capacitance ofgBU , the dominant pole associated with the output node ofthe OTA, VEA moves to a higher frequency, resulting in anoverall bandwidth increase. The location of poles and zerosfor heavy and light load conditions are shown in Fig. 2. Sincethe bandwidth of the on-chip capacitor LDO is increased, thePSRR is high at low and moderate frequencies, but still low athigher frequencies, limiting this LDO’s usage for wide-bandapplications.

II. FLIPPED VOLTAGE FOLLOWER LDO ARCHITECTURES

A flipped voltage follower (FVF) is a voltage buffer, withlower output impedance compared to its common-drain tran-sistor amplifier counterpart [1], [9], [40]. A PMOS FVFhas large current sourcing capability with low-voltage dropoutfrom VLINE to VLDO and, hence, is an ideal candidate forLDO implementation [1], [12], [40].

The schematic of an FVF LDO is shown in Fig. 3. The FVFLDO architecture comprises a bandgap circuit (not shown)which generates VBG, control voltage VCTRL generation cir-cuitry, PMOS pass transistor MPASS , FVF control transistorMC and bias current IB LDO. VCTRL drives the gate of MC .The output of the FVF LDO VLDO is obtained at the source

MPASS

VLINE

VLDO

CL

CGS,P

CGD,P

Non-dominant

pole

Dominant

pole

MC

IB_LDO

Fast

loopVCTRL

VFBCC1

M1 M2

IB_EA IB_CTRL

M3 M4 M5

M6VBG

1

VBG_BUF

V1

Control Voltage GeneratorFlipped Voltage Follower

(FVF)

NILOAD

rOIB_LDO

CC_LDO

Fig. 3: Flipped voltage follower (FVF) LDO with on-chip output capacitor. The controlvoltage generator circuit is also shown.

of MC , which is also the drain of MPASS . Since the currentthrough control transistor is fixed at IB LDO, the VSG of MCis ideally constant. Thus, the output VLDO will be one VSGabove VCTRL.

The fast local analog feedback loop created by MC andMPASS of the FVF regulates VLDO. MPASS is configuredas a source follower and transistor MC is a common-gateamplifier, resulting in a moderate open-loop gain.

Because of the local feedback loop, the output range of theFVF is limited on the low side, both by the input voltage,VCTRL, and VSG,PASS . The output voltage VLDO satisfies

VLDO ≤ VDD − VSDsat,PASSVLDO ≥ VDD − VSG,PASS + VSDsat,C (1)VLDO ≥ VCTRL + |VTHP,C |

where |VTHP,C | is the PMOS threshold voltage. This outputrange is lower than the conventional LDO. This limitedrange impacts the pass transistor at light load currents, whenVSG,PASS is small. Indeed, it is not possible to turn off thepass transistor completely.

The minimum bias current through MPASS is IB LDO andoccurs when the load current is zero. During a load transientfrom light to heavy load current, VLDO will drop. When VLDOdrops, the VSG of control transistor MC decreases, whichpulls down the gate of MPASS to source higher current to theload. As such, VLDO is restored to one VSG above VCTRL.Similarly, during a load transient from heavy to light outputcurrent, VLDO will increase because of the high MPASScurrent. This increases the VSG of MC and pulls up the gateof MPASS to decrease the current through it. Consequently,VLDO pulls back to one VSG above VCTRL. The slew rateand bandwidth of the FVF loop determines the settling timeof the output voltage.

The VCTRL generator circuit is a CMOS two-stage amplifierin buffer configuration with a level shifter in the output stage.The bandgap VBG reference voltage is buffered at the outputof the two-stage amplifier as VBG,BUF . A PMOS diode-connected transistor M6 is used as a level shifter to moveVBG,BUF down by oe VSG to generate VCTRL. VCTRL isapplied to the gate of the FVF control transistor MC , whichlevel shifts up to VLDO by one VSG. Thus, the goal is to

generate an LDO output voltage VLDO that is equal to VBG.Grounded capacitor CC1 is added at node VCTRL to achievestability for the control voltage generator circuit.

The open-loop gain of the FVF LDO is given by

ADC ≈ −gmP [rOIB LDO|| (gmC rOC RLDO)] (2)

where gmP , rOP , gmC , and rOC are the transconductance andoutput resistance of transistors MPASS and MC , respectively.RLDO is the load resistor RL (not shown) in parallel withrOP . Parameter rOIB LDO is the output resistance of currentsource IB LDO. The open-loop gain of the FVF has a maxi-mum value of −gmP rOIB LDO at light load currents, wheregmCrOCRLDO >> rOIB LDO. At heavy load currents, theopen-loop gain reduces to −gmP (gmC rOC RLDO).

Since the gate capacitance of MPASS is large and the resis-tance at feedback node VFB is also high, the pole associatedwith that node will be the dominant pole. The impedance atthe output node is low and thus the pole associated with thatnode will be non-dominant. The expression for the poles aregiven by

ωP1 ≈ −1

[rOIB LDO|| (gmC rOC RLDO)] CGS,P

ωP2 ≈ −1(

1gmC||RLDO

)CLDO

(3)

where, CGS,P and CGD,P are the gate-to-source and gate-to-drain parasitic capacitance of pass transistor MPASS . CLDOis the total equivalent grounded capacitance at node VLDO,mainly dominated by the load capacitance CL. From (3), weconclude that both poles move with load current. At light loadcurrents, the poles are located at

ωP1 ≈ −1

rOIB LDO CGS,P

ωP2 ≈ −gmCCLDO

(4)

Since rOIB LDO >> 1/gmC , the poles are located far fromeach other, resulting in good stability. The bandwidth of theFVF loop is set by ωP1.

At heavy load currents, the poles move to

ωP1 ≈ −1

(gmC rOC RLDO) CGS,P

ωP2 ≈ −1

RLDO CLDO(5)

In this case, the separation between the two poles is definedby the ratio gmCrOCCGS,P /CLDO. Careful design ensuresthese two poles are separated far enough to meet the phasemargin requirements. Adding a suitable grounded compensa-tion capacitor CC LDO at node VFB will make sure the twopoles are far from each other to ensure stability. The magnituderesponse of the FVF LDO with pole-zero locations at heavyand light load currents is shown in Fig. 4.

One of the issues with the FVF LDO is relatively poorload regulation. The lower the output resistance, the better theoutput regulation. Output resistance is inversely proportional

wP1

FreqwP2

Heavy current load

Light current load

|AV|

Fig. 4: Frequency response of FVF LDO with pole-zero locations for light and heavyload current conditions.

to the open-loop gain. The output resistance of the FVF LDOis expressed as

ROUT =

(1

gmC||rOP

)gmP [rOIB LDO|| (gmC rOC RLDO)]

(6)

The output resistance of the FVF LDO varies with loadcurrent. This variation impacts load regulation.

III. FOLDED FVF LDO

To overcome FVF LDO’s loop gain limitation and toimprove the output regulation, the FVF can be replaced bya folded FVF, as illustrated in Fig. 5, with the addition ofcascode transistor MCAS in the feedback loop. Bias voltageVCN is selected such that node VFB is the minimum voltagerequired across current source IB LDO.

MPASS

VLINE

VLDO

CL

CGS,P

CGD,P

MC

IB_LDO

K

MCASVCN

VFB

VGP

IB_CAS

Dominant

pole

Non-dominant

pole

VCTRLBandgap

VBGControl

Voltage

GeneratorILOAD

rOIB_CAS

FVFFolded Cascode

rOIB_LDO

Fig. 5: Schematic of folded flipped voltage follower based LDO.

The major effect of MCAS , high loop gain, is possible onlyif current source IB CAS is similarly cascoded. Nevertheless,the equivalent resistance at the gate of MPASS is large andthus the pole associated with node VGP is dominant and limitsthe bandwidth of the FVF loop.

The output voltage range is high in the folded FVF architec-ture. The inequality containing VSG,PASS in (2) is no longervalid. As such, it is possible to turn off transistor MPASSalmost completely.

In [4], the authors introduce a common-drain buffer MBUFin the FVF loop, to drive the gate of the pass transistor,as shown in Fig. 6(a). Because of the low output resistance

(b)

(a)

RLDOgmPvgpvin

vldo

CLDO rOIB_LDO CFB1

gmCvldo

rOC

vfb1

ac

G

S

ROUT

Loop Break

vout vin

MPASS

VLINE

VLDO

CL

CGS,P

CGD,P

MC

IB_LDO

MBUF

IB_BUF

MCASVCN

VFB1

VGP

IB_CAS

VFB2

ILOAD

rOIB_CAS

RGPgmBUF

(vgp–vin)

vgp

CGS,P

CGD,P

vgp

rOIB_CAS CFB2

gmCASvfb1

rOCAS

vfb2

rOIB_LDO

CC1

FVFBuffered Folded

Cascode

M1 M2

IB_EA IB_CTRL

M3 M4 M5

M6VBG

1

VBG_BUF

V1

Control Voltage Generator

VCTRL

Fig. 6: (a) Transistor level schematic of buffered folded FVF based LDO from [4] and (b) its small-signal model.

of the buffer, the pole associated with node VGP moves tohigher frequencies. Now the dominant pole is determined bythe high output impedance node VFB2, which is at the drainof cascode transistor MCAS . Since the input capacitance ofbuffer transistor MBUF is low, the dominant pole moves tohigher frequencies by nearly two decades. This increase inthe bandwidth of the FVF loop has no impact on the low-frequency loop gain, since the buffer has a nominal gain ofone.

The small-signal model of the buffered folded FVF LDO isshown in Fig. 6(b). Assuming current IB CAS attached to nodeVFB2 is a cascoded current source with high output impedancerOIB CAS , whereas current source IB LDO is simple, thesmall-signal gain and pole locations of the LDO of Fig. 6are approximately

ADC ≈ −gmP [rOIB CAS ||(gmCASrOCAS)rOIB LDO]

ωP1 ≈ −1

[rOIB CAS ||(gmCASrOCAS)rOIB LDO]CFB2

ωP2 ≈ −1(

1gmC||RLDO

)CLDO

ωP3 ≈ −1(

1gmBUF

)CGS,P

(7)

ωZ1 ≈ +1(

1gmP

)CGD,P

where CFB2 is the equivalent grounded capacitance at nodeVFB2 and other parameters follow naming conventions.

From the DC gain expression, we note that the gain varieswith gmP . At light load currents, gmP is lower and the gain isreduced. As the load current increases, gmP increases with thesquare-root of load current and, thus, at higher load currents,

the gain is higher. This higher loop gain reduces the outputresistance of the FVF to a much lower value and improvesoutput regulation.

The dominant pole is created by the resistance and capac-itance at node VFB2. As the capacitance CFB2 is small, thelocation of the pole will be at higher frequencies but dominantby the high cascoded resistance of IB CAS . The second poleis defined by CLDO, RLDO and 1/gmC , Since 1/gmC issmall, this pole is also located at higher frequencies. Thesehigher frequency poles compete for dominance as they mightbe closely located. Adding a compensation capacitor at nodeVFB2 to ground will help in achieving stability with littlecompromise in bandwidth. The third pole and the RHP zeroare defined by CGS,P & 1/gmBUF and CGD,P & 1/gmP ,respectively; they are located at high frequencies.

One drawback of this FVF LDO configuration is that theadditional buffer MBUF increases the minimum voltage atnode VGP by VSG,BUF . It is no longer possible to turn onMPASS completely, which increases the dropout voltage ofthe LDO.

IV. MULTI-LOOP BUFFERED FVF LDO

The bandwidth of the buffered folded FVF LDO is limitedby the dominant pole of the FVF loop that is created by thehigh impedance node VFB2 shown in Fig. 6. This bandwidthmay be limited to tens of megahertz. In order to increase thebandwidth even higher, all the nodes in the FVF loop needto have high-frequency poles without compromising outputvoltage regulation. The authors in [20] introduce a multi-loopbuffered FVF LDO that achieves high bandwidth; however,the regulation improvement is nominal. An advancement ofthe multi-loop LDO of [20] is presented in [10], in which thevoltage regulation is improved significantly with no compro-

MPASS

CC1

VLINE

VLDO

CL

CGS,P

CGD,P

MC

IB_LDO

M2 M3

IB_EA IB_CTRL

M4 M5 M6

M7

VBG

VCTRL

1 K

VBG_BUF

V1

M10

IB_FFVF

M8 VFB

VGP

IB_FFVF

M9

M1

N1

Error amplifierControl Voltage

GenerationFolded FVF Flipped Voltage Follower

(FVF)

ILOAD

Output Regulation

Opamp

CC2

N+1VREF

rOIB_LDO

Fig. 7: Schematic of buffered cascoded FVF based LDO for accurate output regulation and high bandwidth, adapted from [3], [20].

mise in bandwidth. The schematic of the multi-loop bufferedFVF LDO is shown in Fig. 7.

The buffered FVF loop consists of an FVF output stageMPASS −MC − IB LDO buffered with a folded FVF formedby transistors M8 − M10 with two bias currents labeledIBFFV F . The advantage of a folded FVF over a common-drain (CD) voltage follower is lower output resistance. Thus,the pole at the gate of MPASS is moved to higher frequencies.Transistor M9 is added as a diode-connected transistor load ofthe folded FVF, which further reduces the impedance at nodeVGP , particularly at high frequencies when the folded FVFoutput impedance begins to rise [2]. Note also that transistorM9 forms the input side of a current mirror with transistorMPASS . Thus, the ground current in the output stage increaseswith load current.

The loop gain of the FVF loop is designed to be relativelylow, such that its bandwidth is high and, without the presenceof the outer loops, would result in poor phase margin and poorload regulation. The dominant pole is moved to the outputnode, where a minimum load capacitance, CL, is required forstability. The value of output capacitance is in the hundredsof picofarads and thus can easily be integrated on-chip.

The control voltage generation circuit is similar to the circuitshown in Fig. 6, with the exception that one side of the inputdifferential pair is split into two transistors, M2 and M3,described below.

In order to improve load regulation and phase margin, oneouter loop from the LDO output, VLDO, to the control voltagegeneration circuit is added. The outer loop feedback is madestronger than the inner loop feedback from VBG,BUF . This isimplemented by splitting the input differential pair transistorinto two transistors with ratio N : 1. The outer loop isconnected to the higher-weighted transistor and the inner-loopto the smaller one. If the output deviates far from the referencevoltage, then the control voltage VCTRL is adjusted in orderto pull the output voltage back to the reference value.

A second outer loop is added in [10] to improve the outputregulation significantly by integrating the error between thebandgap voltage VBG and the output voltage VLDO using asingle-stage opamp and capacitor CC2. Opamp output signal

VREF is now the input to the control voltage generationblock. In steady-state, VREF equals VBG. However, duringa transient, if the output drops below VBG, VREF increasesso as to restore the output voltage to VBG.

The outer loop bandwidths are slower than the main FVFloop, such that excellent DC output regulation is achievedby the slow loops and excellent transient response is madepossible by the high-frequency FVF loop.

V. DISCUSSION AND CONCLUSION

This tutorial began with a discussion of the conventionalstand-alone LDO IC, which used an external output capacitorin the range of hundreds of nanofarads to tens of microfarads.It then described the recent trend in SoCs toward point-of-loadintegrated LDOs, requiring a low-value on-chip output capac-itor. These LDOs achieve high open-loop gain for excellentoutput voltage regulation, but their bandwidth is limited byan internal dominant pole. This limited bandwidth resulted inreduced PSRR at high frequencies.

The tutorial then introduced the basic FVF circuit as apromising candidate for implementing high bandwidth LDOsdue to its fast local feedback loop. Several iterations, includingfolding and buffering the FVF loop led up to a multi-loopdesign that simultaneously achieved high open-loop gain forgood load regulation and high bandwidth. A peculiar char-acteristic of this integrated multi-loop FVF LDO architectureis the dominance of the output pole, which is set at a highfrequency by an output capacitor in the hundreds of picofarads.This high bandwidth resulted in good PSRR over a widefrequency range.

A present challenge in FVF LDOs is the maximum achiev-able load current. Indeed, the multi-loop folded FVF LDOsof [10], [20] are limited to a load current of 10 mA. Thislimit appears to be caused, at least in part, by the limitedvoltage range at the gate of the pass transistor. Whereas thepass transistor can be fully turned off, it cannot be fully turnedon.

REFERENCES

[1] A. Garimella and P. M. Furth, Eds., High Performance Analog andPower Management Circuit Design Techniques for Modern SoCs.Springer International Publishing, manuscript in preparation.

[2] S. H. Pakala, M. Manda, P. R. Surkanti, A. Garimella, and P. M. Furth,“Voltage Buffer Compensation Using Flipped Voltage Follower in atwo-stage CMOS op-amp,” in 2015 IEEE 58th International MidwestSymposium on Circuits and Systems, Aug 2015, pp. 1–4.

[3] Y. Lu, Y. Wang, Q. Pan, W. H. Ki, and C. P. Yue, “A Fully-IntegratedLow-Dropout Regulator With Full-Spectrum Power Supply Rejection,”IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62,no. 3, pp. 707–716, March 2015.

[4] H. Chen and K. N. Leung, “A Fast-Transient LDO Based on BufferedFlipped Voltage Follower,” in 2010 IEEE International Conference ofElectron Devices and Solid-State Circuits (EDSSC), Dec 2010, pp. 1–4.

[5] P. Y. Or and K. N. Leung, “An Output-Capacitorless Low-DropoutRegulator With Direct Voltage-Spike Detection,” IEEE Journal of Solid-State Circuits, vol. 45, no. 2, pp. 458–466, Feb 2010.

[6] V. Peluso, P. Vancorenland, A. M. Marques, M. S. J. Steyaert, andW. Sansen, “A 900-mV Low-Power ∆Σ A/D Converter with 77-dBDynamic Range,” IEEE Journal of Solid-State Circuits, vol. 33, no. 12,pp. 1887–1897, Dec 1998.

[7] K. Wong and D. Evans, “A 150mA Low Noise, High PSRR Low-Dropout Linear Regulator in 0.13µm Technology for RF SoC Applica-tions,” in 2006 Proceedings of the 32nd European Solid-State CircuitsConference, Sept 2006, pp. 532–535.

[8] W. M. Chen, H. Chiueh, T. J. Chen, C. L. Ho, C. Jeng, M. D. Ker,C. Y. Lin, Y. C. Huang, C. W. Chou, T. Y. Fan, M. S. Cheng, Y. L.Hsin, S. F. Liang, Y. L. Wang, F. Z. Shaw, Y. H. Huang, C. H. Yang, andC. Y. Wu, “A Fully Integrated 8-Channel Closed-Loop Neural-ProstheticCMOS SoC for Real-Time Epileptic Seizure Control,” IEEE Journal ofSolid-State Circuits, vol. 49, no. 1, pp. 232–247, Jan 2014.

[9] R. G. Carvajal, J. R.-. Angulo, A. J. Lopez-Martin, A. Torralba, J. A. G.Galan, A. Carlosena, and F. M. Chavero, “The flipped voltage follower: auseful cell for low-voltage low-power circuit design,” IEEE Transactionson Circuits and Systems I: Regular Papers, vol. 52, no. 7, pp. 1276–1291, July 2005.

[10] M. Manda, S. H. Pakala, and P. M. Furth, “A Multi-Loop Low-DropoutFVF Voltage Regulator with Enhanced Load Regulation,” 2017 IEEE60th International Midwest Symposium on Circuits and Systems, August2017.

[11] X. L. Tan, K. C. Koay, S. S. Chong, and P. K. Chan, “A FVF LDORegulator With Dual-Summed Miller Frequency Compensation for WideLoad Capacitance Range Applications,” IEEE Transactions on Circuitsand Systems I: Regular Papers, vol. 61, no. 5, pp. 1304–1312, May2014.

[12] T. Y. Man, K. N. Leung, C. Y. Leung, P. K. T. Mok, and M. Chan,“Development of Single-Transistor-Control LDO Based on FlippedVoltage Follower for SoC,” IEEE Transactions on Circuits and SystemsI: Regular Papers, vol. 55, no. 5, pp. 1392–1401, June 2008.

[13] Rincon-Mora and Gabriel, Analog IC Design with Low-Dropout Regu-lators. McGraw-Hill, Inc., 2006.

[14] X. Qu, Z. K. Zhou, B. Zhang, and Z. J. Li, “An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push-Pull Output Stage,” IEEE Transactions on Circuits and Systems II:Express Briefs, vol. 60, no. 2, pp. 96–100, Feb 2013.

[15] Y. i. Kim and S. s. Lee, “A Capacitorless LDO Regulator With FastFeedback Technique and Low-Quiescent Current Error Amplifier,” IEEETransactions on Circuits and Systems II: Express Briefs, vol. 60, no. 6,pp. 326–330, June 2013.

[16] A. Garimella, M. W. Rashid, and P. M. Furth, “Reverse Nested MillerCompensation Using Current Buffers in a Three-Stage LDO,” IEEETransactions on Circuits and Systems II: Express Briefs, vol. 57, no. 4,pp. 250–254, April 2010.

[17] F. Centurelli, P. Monsurrò, and A. Trifiletti, “A class-AB flipped voltagefollower output stage,” in 2011 20th European Conference on CircuitTheory and Design (ECCTD), Aug 2011, pp. 757–760.

[18] A. J. Lopez-Martin, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal,“Low-Voltage Super class AB CMOS OTA cells with very high slewrate and power efficiency,” IEEE Journal of Solid-State Circuits, vol. 40,no. 5, pp. 1068–1077, May 2005.

[19] G. A. Rincon-Mora and P. E. Allen, “A Low-Voltage, Low QuiescentCurrent, Low Drop-out Regulator,” IEEE Journal of Solid-State Circuits,vol. 33, no. 1, pp. 36–44, Jan 1998.

[20] Y. Lu, W. H. Ki, and C. P. Yue, “A 0.65ns-Response-Time 3.01ps FOMFully-Integrated Low-Dropout Regulator with Full-Spectrum Power-Supply-Rejection for Wideband Communication Systems,” in 2014 IEEEInternational Solid-State Circuits Conference Digest of Technical Papers(ISSCC), Feb 2014, pp. 306–307.

[21] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, andS. Borkar, “Area-Efficient Linear Regulator with Ultra-Fast Load Regu-lation,” IEEE Journal of Solid-State Circuits, vol. 40, no. 4, pp. 933–940,April 2005.

[22] V. Gupta and G. A. Rincon-Mora, “A 5mA 0.6 CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-SupplyRejection Using 60pF of On-Chip Capacitance,” in 2007 IEEE Inter-national Solid-State Circuits Conference. Digest of Technical Papers,Feb 2007, pp. 520–521.

[23] M. Al-Shyoukh, H. Lee, and R. Perez, “A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer ImpedanceAttenuation,” IEEE Journal of Solid-State Circuits, vol. 42, no. 8, pp.1732–1742, Aug 2007.

[24] G. A. Rincon-Mora and P. E. Allen, “Optimized Frequency-ShapingCircuit Topologies for LDOs,” IEEE Transactions on Circuits andSystems II: Analog and Digital Signal Processing, vol. 45, no. 6, pp.703–708, Jun 1998.

[25] K. N. Leung and P. K. T. Mok, “A Capacitor-free CMOS Low-Dropout Regulator with Damping-Factor-Control Frequency Compen-sation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1691–1702, Oct 2003.

[26] S. K. Lau, P. K. T. Mok, and K. N. Leung, “A Low-Dropout Regulatorfor SoC with Q-Reduction,” IEEE Journal of Solid-State Circuits,vol. 42, no. 3, pp. 658–664, March 2007.

[27] R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, “Full On-Chip CMOS Low-Dropout Voltage Regulator,” IEEE Transactions onCircuits and Systems I: Regular Papers, vol. 54, no. 9, pp. 1879–1890,Sept 2007.

[28] T. Y. Man, P. K. T. Mok, and M. Chan, “A High Slew-Rate Push-PullOutput Amplifier for Low-Quiescent Current Low-Dropout Regulatorswith Transient-Response Improvement,” IEEE Transactions on Circuitsand Systems II: Express Briefs, vol. 54, no. 9, pp. 755–759, Sept 2007.

[29] A. P. Patel and G. A. Rincon-Mora, “High Power-Supply-Rejection(PSR) Current-Mode Low-Dropout (LDO) Regulator,” IEEE Transac-tions on Circuits and Systems II: Express Briefs, vol. 57, no. 11, pp.868–873, Nov 2010.

[30] A. D. Grasso, G. Palumbo, and S. Pennisi, “Advances in ReversedNested Miller Compensation,” IEEE Transactions on Circuits and Sys-tems I: Regular Papers, vol. 54, no. 7, pp. 1459–1470, July 2007.

[31] P. J. Hurst, S. H. Lewis, J. P. Keane, F. Aram, and K. C. Dyer,“Miller Compensation using Current Buffers in Fully Differential CMOSTwo-Stage Operational Amplifiers,” IEEE Transactions on Circuits andSystems I: Regular Papers, vol. 51, no. 2, pp. 275–285, Feb 2004.

[32] G. A. Rincon-Mora, “Active Capacitor Multiplier in Miller-CompensatedCircuits,” IEEE Journal of Solid-State Circuits, vol. 35, no. 1, pp. 26–32,Jan 2000.

[33] G. Rincon-Mora, Analog IC Design with Low-Dropout Regulators(LDOs), ser. McGraw-Hill professional engineering: Electronicengineering. McGraw-Hill Education, 2009. [Online]. Available:https://books.google.com/books?id=TxaRZlb3YbIC

[34] A. Garimella, M. W. Rashid, and P. M. Furth, “Single Miller Com-pensation using Inverting Current Buffer for Multi-Stage Amplifiers,”in Proceedings of 2010 IEEE International Symposium on Circuits andSystems, May 2010, pp. 1579–1582.

[35] P. R. Gray and R. G. Meyer, “MOS Operational Amplifier Design-ATutorial Overview,” IEEE Journal of Solid-State Circuits, vol. 17, no. 6,pp. 969–982, Dec 1982.

[36] B. K. Ahuja, “An Improved Frequency Compensation Technique forCMOS Operational Amplifiers,” IEEE Journal of Solid-State Circuits,vol. 18, no. 6, pp. 629–633, Dec 1983.

[37] R. J. Reay and G. T. A. Kovacs, “An Unconditionally Stable Two-StageCMOS Amplifier,” IEEE Journal of Solid-State Circuits, vol. 30, no. 5,pp. 591–594, May 1995.

[38] D. B. Ribner and M. A. Copeland, “Design Techniques for Cas-coded CMOS Opamps with Improved PSRR and Common-Mode Input

Range,” IEEE Journal of Solid-State Circuits, vol. 19, no. 6, pp. 919–925, Dec 1984.

[39] G. Palumbo and S. Pennisi, Feedback Amplifiers: Theoryand Design. Springer US, 2002. [Online]. Available:https://books.google.com/books?id=Xb0W1VsQFe0C

[40] P. R. Surkanti, A. Garimella, M. Manda, and P. M. Furth, “On theAnalysis of Low Output Impedance Characteristic of Flipped VoltageFollower (FVF) and FVF LDOs,” 2017 IEEE 60th International MidwestSymposium on Circuits and Systems, Aug. 2017.

[41] J. Torres, M. El-Nozahi, A. Amer, S. Gopalraju, R. Abdullah, K. En-tesari, and E. Sanchez-Sinencio, “Low Drop-Out Voltage Regulators:Capacitor-less Architecture Comparison,” IEEE Circuits and SystemsMagazine, vol. 14, no. 2, pp. 6–26, Secondquarter 2014.