floorplacement

FloorplacementFloorplacement

Igor L. Markov Igor L. Markov

FloorplacementFloorplacement(the term was coined by Steve Teig(the term was coined by Steve Teig

of Simplex/Cadence in 2002) of Simplex/Cadence in 2002)

OutlineOutline IntroductionIntroduction BackgroundBackground

FloorplanningFloorplanning Standard-cell placementStandard-cell placement

Tricks & extensionsTricks & extensions Netlist pre-processing and process migrationNetlist pre-processing and process migration Optimization for timing and powerOptimization for timing and power

Unification of placement and floorplanningUnification of placement and floorplanning Large-scale mixed-size placementLarge-scale mixed-size placement Applications to large-scale floorplanningApplications to large-scale floorplanning Free-shape floorplanningFree-shape floorplanning

SummarySummary

Traditional VLSI Design FlowsTraditional VLSI Design Flows

Specification

Logic Design

Physical Design

Fabrication

Testing

Partitioning

Floorplanning

Placement

Routing

Compaction

Unfortunate Trend:Unfortunate Trend: Interconnect Does Not Scale Interconnect Does Not Scale

Interconnect51%

Gate34%

Diffusion15%

Source: Intel, Feb 2004

Total dynamic power breakdownTotal dynamic power breakdown for for Intel CentrinoIntel Centrino ((global clock included ))

Modern VLSI Design FlowsModern VLSI Design FlowsSpecification

Logic DesignPhysical Design

Fabrication

Testing

Partitioning

Floorplanning

Placement

Routing

Physical Synthesis

Design ForManufacturing

Detail Routing

Compaction

Floorplacement

This Work

Fixed-Die LayoutFixed-Die Layout 10 years ago placement was done for variable die10 years ago placement was done for variable die

Except for FPGAsExcept for FPGAs Modern ASICs use pre-defined floorplansModern ASICs use pre-defined floorplans

Layout area, routing tracks, power lines, etcLayout area, routing tracks, power lines, etcmay be fixed before placement may be fixed before placement

Area minimization is irrelevant (Area minimization is irrelevant (area is fixedarea is fixed)) New phenomenon: unroutable placementsNew phenomenon: unroutable placements New phenomenon: whitespace is known New phenomenon: whitespace is known a prioria priori Row utilizationRow utilization %% = = densitydensity % % = = 100% - whitespace100% - whitespace % %

Fixed-die layout is harder than variable-dieFixed-die layout is harder than variable-die Can perform variable die with fixed-die tools,Can perform variable die with fixed-die tools,

but not vice versabut not vice versa Tools from Cadence, Synopsys, Mentor, IBM Tools from Cadence, Synopsys, Mentor, IBM

explicitly support fixed-die onlyexplicitly support fixed-die only

Review: Partitioning & FloorplanningReview: Partitioning & Floorplanning

Partitioning Partitioning Facilitates a hierarchical design methodologyFacilitates a hierarchical design methodology

(older placers not scalable)(older placers not scalable) Floorplanning: seeks non-overlapping locations Floorplanning: seeks non-overlapping locations

for hard and soft blocks, shapes for soft blocksfor hard and soft blocks, shapes for soft blocks Objectives: minimize area and wirelength Objectives: minimize area and wirelength Traditionally assumes “variable-die” (full-chip) layout Traditionally assumes “variable-die” (full-chip) layout

Partitioning & Floorplanning allow early Partitioning & Floorplanning allow early estimation of interconnect for logic optimizationestimation of interconnect for logic optimization

Std-cell Design Mixed-size DesignBlock-based Design

Large rectangles can representLarge rectangles can represent Intellectual Property (IP): hard or softIntellectual Property (IP): hard or soft Macros, memories, data-paths, analog modulesMacros, memories, data-paths, analog modules Modules of unsynthesized logicModules of unsynthesized logic

Placement versus FloorplanningPlacement versus FloorplanningMathematically, placement and Mathematically, placement and

floorplanning (FP) are the same problemfloorplanning (FP) are the same problemSeek module locationsSeek module locationsMust avoid overlaps between modulesMust avoid overlaps between modulesMust observe region constraintsMust observe region constraintsSeek to minimize wirelength (power)Seek to minimize wirelength (power)Seek to satisfy delay constraintsSeek to satisfy delay constraints

Main differencesMain differencesScale (number of objects) and algorithmsScale (number of objects) and algorithms

This work: This work: a unified tool (a unified tool (floorplacerfloorplacer))can dynamically invoke FP or placementcan dynamically invoke FP or placement

Placement vs. FloorplanningPlacement vs. Floorplanning

CharacteristicsCharacteristics Floor-Floor-plannersplanners

PlacersPlacers Floor-Floor-placers placers (this work)(this work)

Scalable w runtimeScalable w runtime NoNo YesYes YesYesScalable w wirelength Scalable w wirelength NoNo YesYes YesYesExplicit non-overlapping Explicit non-overlapping constraintsconstraints

YesYes NoNo YesYes

Can handle large modulesCan handle large modules YesYes NoNo YesYesSupport for non-Support for non-rectangular blocksrectangular blocks

LimitedLimited NoNo YesYes

Support for soft-Support for soft-rectangular blocksrectangular blocks

YesYes NoNo YesYes


Floorplanning: Floorplanning: datastructures and algorithmsdatastructures and algorithms Standard-cell placementStandard-cell placement



SummarySummary

Slicing vs. Non-slicing FloorplansSlicing vs. Non-slicing Floorplans

Slicing FP: Simpler

Non-slicing FP: More general

Classical Block PackingClassical Block Packing Seeks non-overlapping locationsSeeks non-overlapping locations

of hard and soft blocksof hard and soft blocks Objectives: minimize area and/or wirelength Objectives: minimize area and/or wirelength Core area not pre-defined (variable-die layout)Core area not pre-defined (variable-die layout) Floorplan representations: Floorplan representations:

Location-based versus topologicalLocation-based versus topological O-Tree, B*-Tree, O-Tree, B*-Tree, Sequence PairSequence Pair, TCG, CBL etc, TCG, CBL etc We use We use SPSP, but our methods are generally applicable , but our methods are generally applicable

Simulated Annealing (SA) used for optimizationSimulated Annealing (SA) used for optimization

Sequence Pair (SP)Sequence Pair (SP) Proposed by Murata et al. [TCAD ’97]Proposed by Murata et al. [TCAD ’97] Two permutations of N blocks capture the geometric Two permutations of N blocks capture the geometric

relation between each pair of blocksrelation between each pair of blocks(<…a…b…>,<…a…b…>)(<…a…b…>,<…a…b…>) a is to the left of b a is to the left of b(<…a…b…>,<…b…a…>)(<…a…b…>,<…b…a…>) a is above b a is above b

Horizontal (Vertical) constraint graphsHorizontal (Vertical) constraint graphs Edge aEdge ab iff a is to the left of b (a is above b)b iff a is to the left of b (a is above b)

Given block dimensions and an SP, can find locationsGiven block dimensions and an SP, can find locations O(nO(n22)-)-time time (faster!)(faster!) O(n log(n))-timeO(n log(n))-time O(n log(log(n)))-timeO(n log(log(n)))-time

A

B C

<ABC, BAC>

Left

Top

Right

Bottom

Fixed Outline FloorplanningFixed Outline Floorplanning Not an area minimization problemNot an area minimization problem

Rather a constraint satisfaction problem Rather a constraint satisfaction problem ““Classical Floorplanning Considered Harmful” Classical Floorplanning Considered Harmful”

[Kahng, ISPD `00][Kahng, ISPD `00] First addressed in our work First addressed in our work [ICCD`01, TVLSI`03][ICCD`01, TVLSI`03]

x-span

y-sp

an

Floorplan “Floorplan “SlackSlack” (compatible ” (compatible with many FP representations)with many FP representations)

FE

D

A

B C

FE

A

B C

D

Left Packing Right Packing

x-Slack Computation

<FEDBCA, ABFECD>

x-slack for block A =

x(Aright) – x(Aleft)

<FED> is the LCS

Example: A Slack-based MoveExample: A Slack-based Move

Block with y-slack=0

Fixed-outline FP’er ParquetFixed-outline FP’er Parquet(based on Simulated Annealing)(based on Simulated Annealing)[Adya&Markov, ICCD 01, TVLSI 03][Adya&Markov, ICCD 01, TVLSI 03]

S.A.

x-violation

y-violation

current floorplan

required outline

Restart

S.A.

S.A.



Tricks & extensionsTricks & extensions Pre-processing and process migrationPre-processing and process migration Optimization for timing and powerOptimization for timing and power


SummarySummary

Global Placement TechniquesGlobal Placement Techniques Simulated AnnealingSimulated Annealing

TimberWolfTimberWolf Dragon (Min-cut + SA)Dragon (Min-cut + SA)

Min-cutMin-cut partitioningpartitioning (IBM-Cplace, Cadence-Qplace, Capo, Feng Shui) (IBM-Cplace, Cadence-Qplace, Capo, Feng Shui)

Multi-level Fiduccia-MattheysesMulti-level Fiduccia-Mattheyses Analytical PlacementAnalytical Placement

Force-directed [Cheng & Kuh 84]Force-directed [Cheng & Kuh 84] PROUD [Tsay & Kuh 88]PROUD [Tsay & Kuh 88] GORDIAN and GORDIAN-L [Sigl, Dohl & Johannes 91]GORDIAN and GORDIAN-L [Sigl, Dohl & Johannes 91] Geometric Partitioning [Vygen 97]Geometric Partitioning [Vygen 97] Poisson equation [Eisenmann & Johannes, DAC ‘98]Poisson equation [Eisenmann & Johannes, DAC ‘98] ACG [Alpert et al, ICCAD 2002]ACG [Alpert et al, ICCAD 2002]

etc.

Global Placement Global Placement by Recursive Min-cut Partitioningby Recursive Min-cut Partitioning1 2

3 4

Placement Bin

End-case placement by

branch-and-bound

Placers using min-cut bisection: Capo, Placers using min-cut bisection: Capo, FengShui, IBM CPlace, Cadence QPlaceFengShui, IBM CPlace, Cadence QPlace

Detail: Partitioning One BinDetail: Partitioning One Bin

100%area

Tentative Cut-line

50% 50%


60% 40%

Shift cutline to equalize density

50% 50%


60% 40%

60% 40%

Actual cutline

Min-cut Placement Can Min-cut Placement Can Produce Slicing FloorplansProduce Slicing Floorplans

Slicing Floorplan!

We are going to useWe are going to usethis effect for floorplanningthis effect for floorplanningPotential reductionsPotential reductions

in run-time and wirelengthin run-time and wirelengthRecall: traditional floorplannersRecall: traditional floorplanners

use Simulated Annealinguse Simulated Annealing





SummarySummary

Whitespace Allocation vs BufferingWhitespace Allocation vs Buffering(72K Cells, 74% WS)(72K Cells, 74% WS)

Min-cut/IBMWL=11.43e6

ACG/IBMWL=10.48e6

Filler Cells/CapoWL=8.76e6

Uniform WSWL=15.32e6

Tethering a Cell to a LocationTethering a Cell to a Location Idea: soft region constraintsIdea: soft region constraints Fake nets contribute to wirelengthFake nets contribute to wirelength

Penalty for violating soft region constraints Penalty for violating soft region constraints Tunable parametersTunable parameters

Size Size of tethering boxof tethering box Number of cellsNumber of cells tethered tethered

Fake Pin

Fake Net

Tethering offers a tunable amountTethering offers a tunable amountof freedom for further optimizationof freedom for further optimization

Stable Re-PlacementStable Re-Placement

1.1. Start with an initial placementStart with an initial placement2.2. Tether x% of the cells to the locations Tether x% of the cells to the locations

specified by initial placementspecified by initial placement• Add fixed pins and fake netsAdd fixed pins and fake nets

3.3. Rerun placementRerun placement4.4. Remove fake pins and netsRemove fake pins and nets

Controllable Stability Controllable Stability of Min-cut Placersof Min-cut Placers

Initial 5% tether0% tether

Capo (randomized min-cut)

Application 1: Process MigrationApplication 1: Process MigrationShorter design cycles require IP reuseShorter design cycles require IP reuse# of repeaters is increasing rapidly# of repeaters is increasing rapidly

in more advanced technology nodesin more advanced technology nodesWires are not scaling as well as devicesWires are not scaling as well as devicesMore # of repeaters / logic gateMore # of repeaters / logic gate

Different Different minimum local whitespaceminimum local whitespace requirements for blocks during migrationrequirements for blocks during migration

It is desirable to preserveIt is desirable to preserverelativerelative timing characteristics of a design timing characteristics of a design

Application 2: Floorplan ReshapingApplication 2: Floorplan ReshapingFloorplans may change due to process Floorplans may change due to process

migration or due to poor initial estimatesmigration or due to poor initial estimatesWhen changing the block shape,When changing the block shape,

a designer may want to maintain the a designer may want to maintain the relative timing characteristics of the designrelative timing characteristics of the design

Examples: Rescaling and Examples: Rescaling and ReshapingReshaping

Use of Netlist Pre-processingUse of Netlist Pre-processingFor a placed netlistFor a placed netlist

Geometrically rescale all locationsGeometrically rescale all locationsXnew = Xold * Widthnew / Widthold

Ynew = Yold * Heightnew / Heightold

(resulting locations may not be legal)(resulting locations may not be legal)Unplace all objects, but tether themUnplace all objects, but tether them

to the above “ideal” locationsto the above “ideal” locationsDuring reshaping, must re-place I/O padsDuring reshaping, must re-place I/O padsPerform placement, record legal locationsPerform placement, record legal locationsRemove fake pins and netsRemove fake pins and nets

Designs Used for Our Designs Used for Our ExperimentsExperiments

Downloaded from http://www.opencores.org

Rescaling ResultsRescaling Results

Placer: Cadence QplacePlacer: Cadence Qplace

Reshaping ResultsReshaping Results

Placer: Cadence QplacePlacer: Cadence Qplace

Tricks for Performance OptimizationTricks for Performance Optimization

Net-weights, net-bounds etc. extend wirelength-Net-weights, net-bounds etc. extend wirelength-driven design flows to timing-driven design flowsdriven design flows to timing-driven design flows

Placement-driven synthesis & re-synthesis Placement-driven synthesis & re-synthesis Technology mapping, gate sizing and bufferingTechnology mapping, gate sizing and buffering Gate replicationGate replication [Lillis et al, DAC 03 and 04] [Lillis et al, DAC 03 and 04]

DAC 04: “DAC 04: “Efficient Timing Closure w/o Timing-driven Efficient Timing Closure w/o Timing-driven Placement and RoutingPlacement and Routing”, U. Washington”, U. Washington

DAC 04: Performance Optimization in DAC 04: Performance Optimization in Microarchitectural Floorplanning, GA TechMicroarchitectural Floorplanning, GA Tech

DAC 03: Cycle-time Opt. in Floorplanning, UCLADAC 03: Cycle-time Opt. in Floorplanning, UCLA Extended our software (Parquet) Extended our software (Parquet)

Tricks for Power OptimizationTricks for Power Optimization

Compute net activity factorsCompute net activity factors Increase weights of active signal netsIncrease weights of active signal nets

Reduce the clock tree length by placingReduce the clock tree length by placingflip-flops closer togetherflip-flops closer togetherE.g., in a given placement, cluster FFs,E.g., in a given placement, cluster FFs,

connect FFs in each cluster by fake nets;connect FFs in each cluster by fake nets;re-place everythingre-place everything

This may increase length of signal netsThis may increase length of signal nets



Tricks & extensionsTricks & extensions Netlist pre-processing & process migrationNetlist pre-processing & process migration Optimization for timing and powerOptimization for timing and power


SummarySummary

A New Generation of Layout ToolsA New Generation of Layout Tools Place objects of very different sizes & semanticsPlace objects of very different sizes & semantics

Standard cellsStandard cells Hard and soft IPHard and soft IP Macros and datapathsMacros and datapaths Registers and unsynthesized logic (modules)Registers and unsynthesized logic (modules)

Shape modulesShape modules Discrete or variable aspect ratiosDiscrete or variable aspect ratios Flexible shapes (rectilinear or not)Flexible shapes (rectilinear or not)

Optimize very different objectivesOptimize very different objectives Handle differences between logicalHandle differences between logical

and physical hierarchiesand physical hierarchies

Why Mixed-size Placement is DifficultWhy Mixed-size Placement is Difficult

IP reuse, memories etc IP reuse, memories etc large rectangles in layout large rectangles in layout Mixed-size placement is at least as hard as Mixed-size placement is at least as hard as

Standard cell placement (Standard cell placement (many small movable modulesmany small movable modules)) Floorplanning (Floorplanning (large, bulky modules are difficult to pack,large, bulky modules are difficult to pack,

especially on a fixed die!especially on a fixed die!)) Typical optimization heuristics are move-basedTypical optimization heuristics are move-based

Each move is “local”, i.e., affects few other objectsEach move is “local”, i.e., affects few other objects However, However, large modules affect many other moduleslarge modules affect many other modules Some moves have ripple-effect on small cellsSome moves have ripple-effect on small cells

Removing overlaps after global placementRemoving overlaps after global placementis not easy, invalidates top-down estimationis not easy, invalidates top-down estimation

Cadence-recommendedCadence-recommended Mixed-size Placement Flow Mixed-size Placement Flow

QPlace (SEDSM) places large modules firstQPlace (SEDSM) places large modules firstDesigner manually removes overlapsDesigner manually removes overlapsFrom now on, modules are considered fixedFrom now on, modules are considered fixedQPlace is called to place standard-cellsQPlace is called to place standard-cells

Otherwise, as our experiments show,Otherwise, as our experiments show,Handling many large cells Handling many large cells

is not ideal in QPlaceis not ideal in QPlace

Cadence (SEDSM/QPlace) Cadence (SEDSM/QPlace) ScreenshotScreenshot ((v. 5.1.67 in v. 5.1.67 in 20022002))

Cadence (SEDSM / QPlace) Cadence (SEDSM / QPlace) Screenshot Screenshot ((v. 5.4.126 in v. 5.4.126 in 20042004))

Relevant Academic Work : Relevant Academic Work : Continuous OptimizationContinuous Optimization

Force directed Force directed approachesapproaches [Eisenmann, Johannes, [Eisenmann, Johannes,

DAC ‘98] : mixed-sizeDAC ‘98] : mixed-size Wires modelled as Wires modelled as

attractive forcesattractive forces Overlaps modelled as Overlaps modelled as

repelling forcesrepelling forces Are good when there isAre good when there is

abundant white-spaceabundant white-space Otherwise, Otherwise, designer must designer must

remove overlapsremove overlaps

Relevant Academic Work : Relevant Academic Work : Combinatorial OptimzationCombinatorial Optimzation

Particularly promisingParticularly promisingon constrained designson constrained designs

[Adya & Markov, ISPD `02]: [Adya & Markov, ISPD `02]: Min-cut Placement + Min-cut Placement + FloorplanningFloorplanning

[Cong et. al, ASPDAC `03]: [Cong et. al, ASPDAC `03]: Multi-level SA placementMulti-level SA placement

[Adya&Markov, ICCAD `03]:[Adya&Markov, ICCAD `03]:Better whitespace distributionBetter whitespace distribution

[Madden et. al, ISPD `04]: [Madden et. al, ISPD `04]: Min-cut placement + Min-cut placement + Post Post Placement LegalizationPlacement Legalization

This work : FloorplacementThis work : Floorplacement

Capo+Parquet Flow Capo+Parquet Flow [Adya & Markov, ISPD ’02][Adya & Markov, ISPD ’02]

Proposed Proposed pre-processingpre-processing techniques for techniques for solving the mixed-size placement problemsolving the mixed-size placement problem

Can be used with standard-cell placersCan be used with standard-cell placersMain approach: loose integrationMain approach: loose integration

of floorplanning and placementof floorplanning and placementApparently the first publicationApparently the first publication

to to reliably achieve overlap-free placementsreliably achieve overlap-free placements

Capo+Parquet Flow Capo+Parquet Flow [Adya & Markov, ISPD ’02] (Outline)[Adya & Markov, ISPD ’02] (Outline)

1.1. Generate Generate initial placementinitial placement using a using a standard-cell placer (pre-processing trick)standard-cell placer (pre-processing trick)

2.2. Generate a Generate a fixed-outline floorplanningfixed-outline floorplanning instance by “instance by “physical clusteringphysical clustering””

3.3. Remove overlapsRemove overlaps and generate valid macro and generate valid macro locations using a fixed-outline floorplanner locations using a fixed-outline floorplanner

4.4. Place small cellsPlace small cells again using standard-cell again using standard-cell placer with macros considered fixedplacer with macros considered fixed

Shredding Macro CellsShredding Macro Cells

0 1 2

1

2

3

0

Shred all macros into smaller sub-cellsShred all macros into smaller sub-cells Place shredded netlist using a black-box min-WL placerPlace shredded netlist using a black-box min-WL placer Determine location of macros by averaging locations of Determine location of macros by averaging locations of

sub-cellssub-cells

(Should work with many min-WL placers)(Should work with many min-WL placers)

Va

VrMACRO

Fake std-cell

Fake wires

Mixed-size Flow (Capo+Parquet) Mixed-size Flow (Capo+Parquet)

[Adya&Markov, ISPD ’02][Adya&Markov, ISPD ’02]Initial Placement Floorplanned design Final Placement

Shredding + Shredding + Analytical Incremental LegalizationAnalytical Incremental Legalization

[Adya&Markov, TODAES ’04][Adya&Markov, TODAES ’04]

Initial Placement Final Placement

Integrated Partitioning, Integrated Partitioning, Floorplanning and PlacementFloorplanning and Placement

Traditional design flows Traditional design flows apply separate optimizationsapply separate optimizationsMostly a scalability concern for old algorithmsMostly a scalability concern for old algorithms

New generation of fast min-cut placers New generation of fast min-cut placers enable an integrated approachenable an integrated approach

A min-cut partitionerA min-cut partitioner is part of the placer is part of the placerShifting cut-lines perform Shifting cut-lines perform floorplanningfloorplanningEnd result: locations of modules (a End result: locations of modules (a placementplacement))

Our New Approach: Our New Approach: Direct Integration of Placement & FloorplanningDirect Integration of Placement & Floorplanning

We use top-down placement,We use top-down placement,fall back on floorplanning when necessaryfall back on floorplanning when necessary(many “local” calls to a floorplanner)(many “local” calls to a floorplanner) In a In a mixed-size placement problemmixed-size placement problem,,

can start with several slicing cutscan start with several slicing cutsEventually will need to pack blocksEventually will need to pack blocks

(when exactly?)(when exactly?) This allows to solve This allows to solve fixed-outline floorplanningfixed-outline floorplanning In rare cases, packing may be infeasibleIn rare cases, packing may be infeasible

(what can be done then?) (what can be done then?)

etc.

Placement by Recursive Bisection + Placement by Recursive Bisection + Fixed-outline floorplanningFixed-outline floorplanning

Placement bin needs

Floorplanning

Our Floorplacement AlgorithmOur Floorplacement AlgorithmVariables: queue of placement binsVariables: queue of placement bins Initialize: queue with top-level binInitialize: queue with top-level binWhile (queue not empty)While (queue not empty)

Dequeue a binDequeue a binIf (bin has If (bin has large/manylarge/many macros) macros)

Cluster std-cells into soft blocksCluster std-cells into soft blocks Use Use fixed–outline floorplannerfixed–outline floorplanner to pack all macros to pack all macros Fix macrosFix macros

else if (small enough)else if (small enough) Process end caseProcess end case

elseelse Bi-partition the bin into smaller binsBi-partition the bin into smaller bins Enqueue each child binEnqueue each child bin

Floorplacement ExampleFloorplacement Example

Cut-line(min-cut)

Placement bin needs

floorplanning

When to Floorplan ?When to Floorplan ? Large-macro testsLarge-macro tests

At least 1 macro does not fit in child binsAt least 1 macro does not fit in child bins <30 macros total, with total area > 80% of bin area<30 macros total, with total area > 80% of bin area

What What if fixed-outline floorplanning failsif fixed-outline floorplanning fails ? ?Return to previous level of placement hierarchyReturn to previous level of placement hierarchy

Merge two child bins to form a parent binMerge two child bins to form a parent bin

Try area-only floorplanningTry area-only floorplanning Else final placement has overlapsElse final placement has overlaps

(can try legalizing it at the end!)(can try legalizing it at the end!) Above conditions detect block-based designs,Above conditions detect block-based designs,

std-cell and mixed-size designsstd-cell and mixed-size designs

Mixed-size PlacementsMixed-size PlacementsDesign A: ibm01 Design B: Faraday RISC

Empirical Results : Empirical Results : Placement vs. FloorplacementPlacement vs. Floorplacement

cktckt WLWL TimeTime WLWL TimeTime WLWL TimeTime WLWL TimeTime WLWL TimeTime

ibm01ibm01 3.053.05 2m2m 2.922.92 5m5m 3.013.01 9m9m 3.363.36 10m10m 2.772.77 4.9m4.9m

ibm02ibm02 6.836.83 9m9m 6.56.5 11m11m 7.427.42 18m18m 6.796.79 19m19m 5.605.60 11m11m



ibm18ibm18 51.8451.84 110m110m 57.257.2 158m158m 50.750.7 220m220m 53,8153,81 316m316m 50.950.9 78m78m

Avg%Avg% --14.8814.88 -10.07-10.07 --9.469.46 -7.72-7.72 00

Capo8.5+Parquet(2002)

mPG(2003)

CadenceSEDSM (2004)

Capo8.8+KraftWerk(2003)

Capo9.0(Floorplacement)

Empirical Results:Empirical Results:Floorplanning vs. FloorplacementFloorplanning vs. Floorplacement

GSRC GSRC CircuitCircuit

#Blks#Blks Parquet Parquet (Floorplanner)(Floorplanner)

Capo9.0 Capo9.0 (Floorplacer)(Floorplacer)

WLWL Time Time (sec)(sec)

WLWL Time Time (sec)(sec)

#Min-cut #Min-cut levelslevels

N10N10 1010 5.585.58 0.270.27 5.575.57 0.370.37 00

N30N30 3030 17.3817.38 2.352.35 16.9316.93 1.891.89 11

N50N50 5050 20.7720.77 8.168.16 20.3420.34 5.35.3 11

N100N100 100100 34.5334.53 50.1250.12 32.3932.39 10.510.5 22

N200N200 200200 62.2862.28 240.6240.6 56.8256.82 27.427.4 33

N300N300 300300 75.6975.69 433.9433.9 63.6263.62 25.225.2 33

Floorplanning vs. Floorplanning vs. Free-shape FloorplacementFree-shape Floorplacement

Rectangular shapes during Rectangular shapes during floorplanning seem arbitraryfloorplanning seem arbitrary

Instead, can shred blocks into Instead, can shred blocks into fake standard cells (+fake wires)fake standard cells (+fake wires)

Apply traditional placementApply traditional placement Shape blocksShape blocks, minimize WL, minimize WL

Rect-Rect-angularangular

Free-Free-shapeshape

CircuitCircuit ParquetParquet Shred+Shred+Capo9.0Capo9.0

Avg Avg %%

Ami33Ami33 7698776987 4607246072 40.140.1Ami49Ami49 895560895560 469476469476 47.547.5N50N50 202240202240 8795787957 56.556.5N100N100 350593350593 157548157548 55.055.0

SummarySummary A hybrid algorithm which combines min-cut A hybrid algorithm which combines min-cut

partitioner and fixed-outline floorplannerpartitioner and fixed-outline floorplanner A software tool for large-scale chip designA software tool for large-scale chip design

PartitioningPartitioning Wirelength-driven floorplanningWirelength-driven floorplanning Standard-cell and mixed-size placementStandard-cell and mixed-size placement

Directly applicable to low-power design,Directly applicable to low-power design,can be adapted to performance optimizationcan be adapted to performance optimization DAC`03 paper from UCLA use ParquetDAC`03 paper from UCLA use Parquet

User-friendly design methodologiesUser-friendly design methodologies Hide artifacts of algorithm developmentHide artifacts of algorithm development

from chip designersfrom chip designers

Another New Layout ToolAnother New Layout ToolIs On the Way Is On the Way

Simultaneous placement and routingSimultaneous placement and routingBased on min-cut placementBased on min-cut placementBypasses global routingBypasses global routingDeals directly with detailed pre-routesDeals directly with detailed pre-routes

Expected benefitsExpected benefitsBetter overall runtimeBetter overall runtimeMore accurate estimates of wire delayMore accurate estimates of wire delayMore accurate estimates of congestionMore accurate estimates of congestionBetter end resultsBetter end results

Relevant Publications: ConferencesRelevant Publications: Conferences S.N. Adya, S.C. Chaturvedi, D.A. Papa and I.L. Markov, “S.N. Adya, S.C. Chaturvedi, D.A. Papa and I.L. Markov, “Unification of VLSI Unification of VLSI

Placement and FloorplanningPlacement and Floorplanning", to appear at ", to appear at ICCADICCAD, 2004., 2004. D.A. Papa, S.N. Adya and I.L. Markov, "D.A. Papa, S.N. Adya and I.L. Markov, "Constructive Benchmarking for Constructive Benchmarking for

PlacementPlacement", Great Lakes Symposium on VLSI (", Great Lakes Symposium on VLSI (GLSVLSIGLSVLSI), 2004.), 2004. S.N. Adya, I.L. Markov and P.G. Villarrubia, ”S.N. Adya, I.L. Markov and P.G. Villarrubia, ”On Whitespace and Stability in On Whitespace and Stability in

Mixed-size Placement and Physical SynthesisMixed-size Placement and Physical Synthesis”, International Conference ”, International Conference on Computer Aided Design (on Computer Aided Design (ICCADICCAD), pp. 311-318, 2003.), pp. 311-318, 2003.

S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh and S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, P.N. Parakh and P.H. Madden, "P.H. Madden, "Benchmarking for Large-scale Placement and BeyondBenchmarking for Large-scale Placement and Beyond", ", International Symposium on Physical Design (International Symposium on Physical Design (ISPDISPD), pp. 95-103, 2003), pp. 95-103, 2003

S.N. Adya, I.L. Markov and P.G. Villarrubia, "S.N. Adya, I.L. Markov and P.G. Villarrubia, "Improving Min-cut Placement Improving Min-cut Placement for VLSI Using Analytical Techniquesfor VLSI Using Analytical Techniques", ", IBM ACASIBM ACAS Conference, pp. 55-62, Conference, pp. 55-62, 2003.2003.

S.N. Adya and I.L. Markov, "S.N. Adya and I.L. Markov, "Consistent Placement of Macro-Blocks using Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell PlacementFloorplanning and Standard-Cell Placement", International Symposium of ", International Symposium of Physical Design (Physical Design (ISPDISPD), pp.12-17, 2002. ), pp.12-17, 2002.

S.N. Adya and I.L. Markov, "S.N. Adya and I.L. Markov, "Fixed Outline Floorplanning Through Better Fixed Outline Floorplanning Through Better Local SearchLocal Search", International Conference of Computer Design (", International Conference of Computer Design (ICCDICCD), ), pp.328-334, 2001 pp.328-334, 2001

Relevant Publications: JournalsRelevant Publications: Journals S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia, S.N. Adya, M.C. Yildiz, I.L. Markov, P.G. Villarrubia,

P.N. Parakh and P.H. Madden, “P.N. Parakh and P.H. Madden, “Benchmarking for Large-Benchmarking for Large-scale Placement and Beyond”scale Placement and Beyond”, IEEE Trans. on CAD, vol , IEEE Trans. on CAD, vol 23(4), April, 2004, pp. 472-487.23(4), April, 2004, pp. 472-487.

S.N. Adya and I.L. Markov, “S.N. Adya and I.L. Markov, “Combinatorial Techniques for Combinatorial Techniques for Mixed-size Placement”Mixed-size Placement”, to appear in ACM Trans. on Design , to appear in ACM Trans. on Design Automation of Electronic Systems, 2004Automation of Electronic Systems, 2004

S.N. Adya and I.L. Markov, “S.N. Adya and I.L. Markov, “Fixed-outline Floorplanning : Fixed-outline Floorplanning : Enabling Hierarchical Design”Enabling Hierarchical Design”, IEEE Trans. on VLSI, vol. , IEEE Trans. on VLSI, vol. 11(6), December 2003, pp. 1120-1135 11(6), December 2003, pp. 1120-1135

S.N. Adya, I. L. Markov and P. G. Villarrubia, S.N. Adya, I. L. Markov and P. G. Villarrubia, ““On Whitespace and Stability in Physical Synthesis”On Whitespace and Stability in Physical Synthesis”, , in Preparation, 2004.in Preparation, 2004.

AcknowledgementsAcknowledgements

Funding: Funding: GSRCGSRC (MARCO/SIA and DARPA) (MARCO/SIA and DARPA) Funding: Funding: IBMIBM Equipment grants: Equipment grants: IntelIntel and and IBMIBM Thanks for help and commentsThanks for help and comments

Frank JohannesFrank Johannes (TU Munich) (TU Munich) Andrew KahngAndrew Kahng (UCSD) (UCSD)

Students: Students: Saurabh AdyaSaurabh Adya (Synplicity),(Synplicity), Shubhyant Chaturvedi Shubhyant Chaturvedi (AMD),(AMD),

David PapaDavid Papa,, Jarrod Roy Jarrod Roy and and Hayward ChanHayward Chan

Thank You !Thank You !

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