floorplanner: effective layout

© 2003 Xilinx, Inc. All Rights Reserved

Floorplanner: Effective Layout

Rhett Whatcott:Rhett Whatcott:

Floorplanner - 15 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

After completing this module, you will be able to:

Objectives

• Identify the Floorplanner windows• Specify the Floorplanner flow • Describe how to use area constraints• Identify how PACE is used to specify area constraints• Identify optimal pin layout

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Outline

• Introduction• Floorplanning Procedures• Area Constraints & I/O Layout• PACE• Summary• Appendix:

– RPM Core– Overcoming MAP/PAR Limitations– Pseudo Guide File with Floorplanner– Additional I/O Considerations

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What is the Floorplanner?

• Graphical tool used to display/edit design layout

– Easy to review the results of implementation

Close-up of Virtex-II die


When to Floorplan

• Use the Floorplanner to:– Increase productivity/design performance– View the layout of your implemented design– Partition design sub-systems into general areas on the die (area

constraints/layout)– Make minor placement modifications– Create RPMs (Relationally Placed Macros)

• Use the Floorplanner carefully– Poor floorplanning can decrease design performance– The implementation tools cannot disregard a poor floorplan

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Floorplanner Prerequisites

• Do not perform significant floorplanning unless you are very familiar with:– The design– The target device architecture– Xilinx software

• Without sufficient knowledge, it is suggested you try the following first– Use timing constraints– Increase Place & Route Effort Level– Specify Perform Timing-Based Packing (Map) and extra-effort level

(PAR)– Pipeline or redesign logic in critical paths– Use re-entrant routing or MPPR

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Floorplanning Advantage:

• Given sufficient knowledge…

– In large and/or high performance designs, floorplanning/layout is an effective precursor to implementation

• Provides guidance to implementations tools on the layout of the design• Can help to reduce run time• Can help to increase performance

– Floorplanning is required for Incremental Design Techniques and Modular Design Techniques

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NGDBUILD

MAP

PAR

edn, ngc

ucf

ngd

ncd, pcf

ncf

FloorplannerFloorplanner

Floorplanning Flow

fnf

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ncd


Floorplanner Versus PACE

• PACE:– Easiest tool for specifying pin placement constraints and area constraints

• Floorplanner:– More advanced tool with placement capabilities beyond that of PACE

• Create groups of logic• Constrain logic to a specific location (hard location constraints - hard LOC)• Constrain logic from a current placement (hard LOC)• View and edit placed design• Perform packing of logic resources• Used for cross-probing with Timing Analyzer

– PACE is much better for specifying pin constraints– Specifying area constraints is similar to PACE

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Main Floorplanner Windows

Floorplan (in back)

Shows current placement constraints and design edits

Placement Shows the current design layout from the implementation tools

Design HierarchyDisplays color-coded hierarchicalBlocks.Traverse hierarchy to view any component in the design

Design NetsLists all the nets in the design

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Viewing the Device

• Click View Options, or click the Toggle Resources button to display device resources

– Function Generators and RAM

– Flip-flops and latches

– Three-state buffers– I/O pads

and global buffers• Row and column numbers are

displayed for easy reference

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Locating Logic and Nets

• Use the Edit Find command

• Filters help you narrow your search

– Logic type (flip-flops, I/O pins, nets, etc.)

– Status (floorplanned, not floorplanned, selected, etc.)

– Connections (driving selected logic, sourcing selected logic, etc.)


Viewing Connectivity

• View connectivity by components– Click Edit Preferences Ratsnest Tab. Check Display nets connected

to selected logic– Select a component or group of logic in the Hierarchy window

Connections are shown in the Placement and Floorplan windows

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Package View

• To view the package pins, click View menu Package Pins

• You can view the bottom view or the top view

• PACE provides a more complete package view for more beneficial pin placement

– All dual-purpose and special pins are identified

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Timing Analyzer Cross-Probing

• The Timing Analyzer and Floorplanner can be used together to cross- probe paths

Click on path in Timing Analyzer

Click on path in Timing Analyzer

1 Path appears in Floorplanner

Path appears in Floorplanner

2

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Outline

• Introduction• Floorplanning Procedures• Area Constraints & I/O Layout • PACE• Summary• Appendix:

– RPM Core – Overcoming MAP/PAR Limitations– Pseudo Guide File with Floorplanner– Additional I/O Considerations

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Floorplanning Procedures

• Creating groups of logic• Constraining logic to a specific location• Constraining from the current placement• Locking I/O pins• Area constraints (covered in the next section)


Creating Groups of Logic

• When the design is loaded, logic is automatically grouped according to the design hierarchy

• Create your own groups of logic in two ways:

– Select the logic and use the command Hierarchy Group

– Use the command Hierarchy Group By, to select and group logic


Changing Group Colors

• Use color to identify parts of your design easily

• Select a group of logic • Use the command

Edit Colors

• Choose a new color• Click Apply

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Constraining Logic toa Specific Location

• Select the method in which you would like the logic to be distributed

– Distribute One at a Time drops each component individually

– Up, Down, Left, or Right quickly shapes the logic into a row or column

• Pick up the logic by clicking the icon in the Hierarchy window

• Move the cursor in the Floorplan window

• Click to place the logic– Valid locations are highlighted

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Moving Logic

• To move logic that is already placed in the Floorplan window– Select the logic that you want to move (in the Hierarchy, Placement, or

Floorplan window)– Click the logic to pick it up– Move the cursor to a new location– Click to place the logic

• To remove logic from the Floorplan window– Select the logic you want to remove– Press <Delete> or move the logic back into the Hierarchy window


Block RAM Placement

• The placement algorithm for block RAM does not always result in an optimal placement with its source and load

• Consider placing most (if not all) of your block RAMs– Block RAM placement can be very critical to the timing of your design

• Hand-place them to use the flow of the device wisely– Horizontal data flow, carry chain runs up

• Discussed further in Area Constraints section

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Constraining From theCurrent Placement

• Use these commands when you want to make minor layout changes

• To constrain selected logic in Placement window:– Select the logic that you want to constrain, from the Placement window– Use the command Floorplan Constrain from Placement– The layout for the selected logic is copied from the Placement window into

the Floorplan window– Make changes to the logic placement in the Floorplan window

• To copy the entire Placement window: use the command Floorplan Replace All with Placement

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Locking I/O Pins

• For high-speed, complicated, and large I/O designs, Xilinx suggests you manually lock I/O

– Use PACE (recommended)– Use the Constraints Editor (Ports tab) – Lock the pins based on the pinout from the implementation tools:

• From ISE Project Navigator: Expand Implement Design, expand Place & Route, double-click Back-annotate Pin Locations

• Floorplanner– Use the Edit Find command to select all I/O Pads– Use the Floorplan Constrain from Placement command– Make adjustments, if needed, and save

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Outline

• Introduction• Floorplanning Procedures• Area Constraints & I/O Layout• PACE • Summary• Appendix:


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I/O Location Constraints

• For high-speed designs, complex designs, and designs with a large number of I/O pins, Xilinx recommends manual placement of I/O

– Guides the internal data flow– The implementation tools have the ability to place logic and pins, but this

does not always result in the most optimal placement– Poor pin placement can reduce the chances of your design meeting your

performance objectives– Making good pin assignments requires detailed knowledge of the design

functionality and Xilinx architecture• Pin assignments must also comply with the silicon’s capabilities

– Assignments must follow the I/O banking rules and the pre-grouping of the differential I/O pins

– Clock pin assignments affect clock region access and shared input pairs– Take advantage of internal data-flow


Pin Constraints

• Clocks should be constrained to dedicated clock pins– Or clock pin pairs for differential clocks– Keep in mind the global clock buffer limitations

• Eight global clocks or eight clocks total into each clock region• Rules previously described

• Use dual-purpose pins last – For example, configuration and DCI pins– This will help to reduce contention during board power-up or when the

FPGA is reconfigured on demand– PACE or the Xilinx Constraints Editor can be used to prohibit configuration

pins


Internal Logic Layout

C_REG E_REG G_REG

A+B E+FC+D

Bit 0 Datapath

Bit 7Datapath

• Horizontal data flow with vertical bus alignment

– Carry logic runs vertically– Bidirectional data bus longlines

run horizontally• 3-state enable lines run

vertically– Control lines (CE, resets, etc)

are generally driven on vertical long lines

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General guidelines for chips with 100K system gates or less:

Layout for Smaller FPGAs

• I/O for control signals on the top or bottom

– Signals are routed vertically• I/O for data buses on the left or right• Internal layout favors horizontal data

flow– Align area blocks to flow horizontally– Allow enough room for carry chains– Place block RAMs appropriately to align

with arithmetic logic

Da

ta B

us

es

Control Signals

Control Signals

Da

ta B

us

es

Data Flow

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Layout for Larger FPGAs

• Use the same guidelines as you would use for smaller chips

• In addition, consider the following:– Group control signals and data

buses near related internal logic– High-fanout signals may be placed

near the middle of the chip, for easy access to horizontal long lines

For chips with 500K system gates or more:

Co

ntr

ol S

ign

als C

on

trol S

ign

als

Data Flow


LSB

MSB

Data Bus Layout

• Arithmetic functions with more than five bits typically utilize carry logic

• Carry chains require specific vertical orientation

– Affects both internal and I/O layout


Interleaved Bus Layout

• Arithmetic functions involving two or more buses will benefit from interleaved pin constraints

– For example:• C <= A + B; or

C <= A * B;

A(0)

B(0)

A(1)

B(1)

A(2)

B(2)

A(3)

B(3)


Area Constraints (a.k.a. Layout, a.k.a. AREA_GROUPs)

• Easiest and most effective application of floorplanning

• Preferred method of floorplanning for synthesis users and large designs– Individual component names change often during synthesis, but hierarchical

block names remain constant• For this to be effective, you must retain hierarchy during synthesis

– Each sub-section of a large design can be constrained to an area• Area constraints allow you to provide guidance while still giving the

implementation tools freedom• This is the primary floorplanning methodology for use with incremental

design techniques

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Area Constraints

1. Select the area group you want to constrain

2. Click the Assign Area button3. Click and drag to define the

area constraint– Floorplanner estimates the

required area and will not allow you to select an area that is too small

1

2

3


Area Constraint Compression

• When assigning area constraints, it may be helpful to apply a compression factor for mapping

– This is equivalent to the global -c option applied in map, but it only applies to an individual AREA_GROUP

– Right-click the AREA_GROUP, select Edit Constraints

• Constraint: Compression• Value: <%>

– <%> represents the percentage of logic resources in that area constraint available for packing

– Click OK

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Area Constraints in UCF

• Floorplanner (and PACE) area constraints create AREA_GROUP and RANGE constraints in the UCF

– AREA_GROUP constraints bind instances into a group– RANGE constraints assign an AREA_GROUP to an area on the die– Syntax:

• INST <hierarchical_group> AREA_GROUP = AG_<ag_name>;• AREA_GROUP <ag_name> RANGE = SLICE_XnYm:SLICE_XnYm;• AREA_GROUP <ag_name> COMPRESSION= <value>; # if applied

– For example:• INST data_control_inst AREA_GROUP = AG_data_control_inst;• AREA_GROUP AG_data_control_inst RANGE =

SLICE_X0Y47:SLICE_X27Y32 ; • AREA_GROUP AG_data_control_inst COMPRESSION= 90;

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RANGE Constraints

• RANGE constraints are written for slices, block RAM, multipliers, and 3-state buffers

– Range constraints will be written for each of these logic types• Slices: AREA_GROUP "AG_data_control_inst" RANGE = SLICE_X0Y47:SLICE_X27Y32 ; • Block RAMs: AREA_GROUP " AG_data_control_inst " RANGE = RAMB16_X1Y18:RAMB16_X3Y15 ;• Block multipliers: AREA_GROUP " AG_data_control_inst " RANGE = MULT18X18_X1Y18:MULT18X18_X3Y15 ;• Three state buffers:AREA_GROUP " AG_data_control_inst " RANGE = TBUF_X0Y15:TBUF_X10Y9 ;

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Multiplier and Block RAM RANGE Constraints

• In this situation, you are only interested in constraining the slices and 3-state buffers

– Hand-place the block RAMs and block multipliers

There’s only room for 4 block RAMs…

but, I need room for 8! What do I do?

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Multiplier and Block RAM RANGE Constraints

• Comment-out the block RAM and multiplier RANGE constraints in the UCF

• Hand-place the block RAMs and multipliers for optimal placement and timing

• This will provide the most optimal approach to floorplanning– Control placement of block RAMs and multipliers through hand placement– Control placement of slice logic and 3-state buffers through area constraints


Outline



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Pinout and Area Constraints Editor (PACE)

• PACE is a tool used to create pinout and area constraints• Constraints are written to the UCF file• The flow, look, and use are very similar to that of Floorplanner

– It does not have all the capabilities of Floorplanner


Pinout and Area Constraints Editor (PACE)

Device ArchitectureAllows area constraint specification

Package PinsAllows pin loc specifications

DesignHierarchy

Displays color-coded hierarchicalblocks

Design Object ListDisplays elements contained in the group that are selected in the Design Hierarchy window

Package Pins Legend


Pin Constraints• Pin constraints most easily made using PACE

Specify I/O options in Object List window

Drag & Drop I/O to Package Pin window


PACE Features

• To prohibit pin sites or slice sites, use the Prohibit icon in the toolbar

• To allow the use of prohibited sites, use the Allow Icon

• Package migration: When a design has the possibility of moving to a different package, PACE will write out prohibit constraints on incompatible pins so user can avoid reassigning I/Os

– IOB Make Pin Compatible With...


Area Constraints

1. Select the area group that you want to constrain

2. Click the Assign Area button

3. Click and drag to define the area constraint

– PACE estimates the required area and will not allow you to select an area that is too small

1

2

3

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Area Constraint Compression

• When assigning area constraints, it may be helpful to apply a compression factor for mapping

– This is equivalent to the global -c option applied in MAP, but it only applies to an individual AREA_GROUP

– Click Areas menu Edit Constraints, enter Constraint: Compression, Value: <%>

• <%> represents the number of logic resources in that area constraint available for packing

– Click Enter, click OK

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Outline



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Review Questions

• Will the implementation tools override any manual edits that decrease performance of your design?

• What is Floorplanner beneficial for?• What is the easiest and most beneficial application of floorplanning?• After which implementation steps can you perform floorplanning? • After creating a new floorplan, which phases of implementation need to

be run again?• Describe an optimal pin layout for Virtex-II/Spartan -3 devices

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Review Questions

• Specify the windows of the floorplanner and explain how they are used


Answers

• Will the implementation tools override any manual edits that decrease performance of your design?

– No


Answers

• What is Floorplanner beneficial for?– In large and/or high performance designs

• Provides guidance to implementations tools on the layout of the design• Can help to reduce run time• Can help to increase performance

– Floorplanning is required for IDT and MDT– Increase productivity/design performance– View the layout of your implemented design– Partition design sub-systems into general areas on the die (area

constraints/layout)– Make minor placement modifications– Create RPMs (Relationally Placed Macros)

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Answers

• What is the easiest and most beneficial application of floorplanning? – Area Constraints (a.k.a. Layout, a.k.a. AREA_GROUPs)

• After which implementation steps can you perform floorplanning? – Translate– MAP– Place & Route

• After creating a new floorplan, which phases of implementation need to be run again?

– Translate, MAP, Place & Route, Configuration

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Answers

• Specify the windows of the floorplanner and explain how they are used

Floorplan (in back)Shows the current placement constraints and design edits

Placement Shows the current design layout from the implementation tools

Design HierarchyDisplays color-coded hierarchical blocks. Traverse hierarchy to view any component in design

Design NetsLists all nets in the design


Answers

• Describe an optimal pin layout for Virtex-II/Spartan-3 devices– Place data to flow horizontally across the device– Place data, addresses, etc. for proper alignment with carry chain

• LSBs below MSBs -- flowing up


Summary

• Take care when editing design placement because the implementation tools cannot change a poor floorplan

• Floorplanning can be an effective method of providing guidance to implementation tools

• Area constraints give the implementation tools guidance but provide the most flexibility to meet your goals

• I/O pin layout guidelines: – Data buses on the left and right of the die– Control signals on the top and bottom– MSB of buses at the top, LSB at the bottom

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Where Can I Learn More?

• Virtex-II, Virtex-II Pro, and Spartan-3 User Guides and Data book– Details on device architecture– http://support.xilinx.com Documentation

• Online Software Manuals Constraints Guide Constraint Entry Floorplanner

• Floorplanner Online Help

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Outline


– RPM Core– Overcoming MAP/PAR Limitations– Pseudo Guide-File with Floorplanner– Additional I/O Considerations

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Reusable RPM Core

• Floorplanner can be used to create cores that retain relative placement and, therefore, performance and timing repeatability

– It allows you to transform a design (or design block) into a Relationally Placed Macro (RPM) core that can be reused via instantiation in any design


Reusable RPM Core Steps

Step 1: Define the logical function of your core in HDLStep 2: Synthesize your design to create an EDIF netlist such as

my_core.edf– Disable I/O insertion and clock buffer insertion

Step 3: Process the EDIF netlist using NGDBuild to produce an NGD file, such as my_core.ngd

Step 4: Load your design (NGD or NCD) into the Floorplanner, and shape the relative placement of the design

Step 5: Save your design using the Write RPM to NCF command in the File menu


Relationally Placed Macro

• What is a Relationally Placed Macro (RPM)?– An RPM uses relative location constraints to constrain logic relationally to

other logic– This helps to keep associated logic close together to reduce routing delays

• RPMs can be created on BELs, COMPs, and hierarchy– Before COMPs can be relationally placed, BELs must be relationally placed – Before hierarchy can be relationally placed, COMPs must be relationally

placed• You must be aware that too many RPM blocks can significantly hinder

the placement tools – They can, in fact, prohibit the tools from finding a placement


Outline

• Introduction• Floorplanning Procedures• Area Constraints & I/O Layout • PACE• Summary• Appendix:


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MAP Limitations

• RPM sourcing locked flip-flops

• Constrained by Packing problems


RPM Sourcing Locked Flip-Flops

• Relationally Placed Macros are components that have been assigned a specific shape with RLOC constraints

– Synthesized arithmetic components larger than six bits may be RPMs

– All RPMs in your design are listed in Section 7 of the MAP report

• In this example, an 8-bit incrementer/decrementer is driving 8 flip-flops to create a counter

8 Flip-flops

8-Bit Inc-Dec


RPM Sourcing Locked Flip-Flops

• When the flip-flops are physically constrained with LOC or RLOC, MAP is unable to pack the Inc-Dec and flip-flops together

– Creates extra delay in the datapath

8 Flip-flops8-Bit Inc-Dec


RPM Sourcing LockedFlip-Flops: Workarounds

• Remove the constraints from the flip-flops

– Now MAP can pull the flip-flops into the same slice with the RPM

• Use the Floorplanner to place both components into the same slice

8 registers8-Bit Inc-Dec


Design Considerations

• When locking down flip-flops, make sure you know what is sourcing them

• If the flip-flops are sourced by an RPM, you should lock down the RPM instead of the flip-flops

• If flops are sourced by non-RPM logic, then it is up to you to determine whether you want to lock down the logic

– In many cases, it should NOT be necessary to lock down the non-RPM logic. MAP will pack this logic into the appropriate slice


Constrained By Packing

• Flip-flop A is constrained to Slice_R1C1 because it drives an output on the NW corner of the die

• Flip-flop B is unconstrained and drives an output on the SE corner of the die• MAP is allowed to pack unconstrained logic together with constrained logic• Result: Bad placement for flip-flop B

D Q

AD Q

F/G

F/GH

Slice R1C1

D Q

B

D Q

AF/G

F/GH

Slice R1C1

D Q

B

MAP


Constrained by Packing: Workarounds

• Avoid partially filled slices (Recommended)– Constrain all the components (LUTs, FFs) of a locked slice– You can use the Floorplanner to fill up the slice

• Set the XIL_MAP_LOC_CLOSED environment variable to TRUE– Tells MAP not to pack unconstrained logic into slices with constrained logic– Can cause an increase in resource utilization if many slices are only

partially filled• Use the Floorplanner to lock flip-flop B in the example• Use map -timing implementation option


Interleaving Logic

• Interleaving spreads out the resources associated with a bus– Other logic can be interspersed with the bus

• MAP and PAR will not automatically interleave logic– You must manually interleave logic with RLOCs or the Floorplanner


Interleaving Example:Related Buses

• A and B input pins are interleaved– Skew between bits of interrelated

buses is minimized– Nets do not cross each other

Verilog:always@(posedge CLK)OUT <= A & B;

VHDL:process ( clk ) begin if ( clk' event and clk = '1' ) then Q <= (A AND B); end if; end process;

A1

A0

B0

B1LUT FF

LUT FF


Dual-PortRAM

ArithmeticFunction

6-7

0-1

2-3

4-5

0 1

2 3

4 5

6 7

Interleaving Example:Dual-Port RAM

• Dual-port RAM produces 1-bit of output per slice• Arithmetic functions and registers produce 2-bits per slice• Placing the RAM in a tall column can cause routing problems and skew• Horizontally interleave the dual-port RAMs to line up with other functions


Working with Patterns

• The Capture Pattern and Impose Pattern commands allow you to create a template pattern of placed logic that can be used later when placing similar logic

– Multiple instances of the same hierarchical block– Components along a datapath

• Procedure:– Select a template group of logic, and click the Capture Pattern button– Select a new group of logic to impose the pattern upon and click the Impose

Pattern button• The new group of logic must have the same number and type of components as

the template group– Place the new logic in the Floorplan window


Outline



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Guide Introduction

• The Floorplanner can be used to create a pseudo guide file to guide future implementations

• What is a guide file?– A guide file is a file from a previous implementation that is used to guide the

placement and/or routing of future implementations– Guiding of logic is based on re-using named elements (FFS, latches, RAMs,

ROMs, LUTs, BUFTs, etc.) from a previous implementation on a new one• What is the purpose of using a guide file?

– To preserve previous good results– Reduce run time


Guide Questions

• What are the prerequisites for using a Floorplanner guide file?

• When would it be appropriate to use a Floorplanner guide file?

• Which elements would be appropriate to floorplan (i.e., which elements are least likely to change)? Why?


Guide Answers

• What are the prerequisites for using a Floorplanner guide file?– Preservation of hierarchy

• When would it be appropriate to use a Floorplanner guide file?– Small changes to overall design (generally, less than ten percent)

• Which elements would be appropriate to floorplan (i.e., which elements are least likely to change)? Why?

– Synchronous elements: FFs, latches, RAMs– Guide files are effective if names remain the same. Names of synchronous

elements usually do not change from one implementation to the next as long as the hierarchy does not change. LUT names (because they are usually machine generated) change almost entirely


Floorplanned Guide File

• Step One: Click Synchronous Elements

• From the Floorplanner window, click Edit Find

• Enter * (star wildcard) in the Name textbox

• Enter Flip-Flops (or memory) in the Type drop-down box

• Click Find• Click Select Found• Click Close


Floorplanned Guide File

• Step Two: Constrain selected logic• From Floorplanner window, click Floorplan menu Constrain from

Placement

• Save and Exit Floorplanner


Expected Guide Results

• Keep in mind with this flow that you are preserving only the placement of the synchronous elements

– In addition to not placing any LUT logic, you have not retained the routing– You are only guiding the placement of LUT logic based on the location of

the synchronous elements• You can expect the results to be similar

– You should not expect the results to match entirely. Why?• Because of the changes that were made to the design


Outline



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v6.1: Added this section.



Device Migration Considerations

• Virtex-II and Virtex-II Pro pinouts were created to allow for migration to a larger or smaller device

• For a larger device, the number of reference voltage pins will increase (Vcco and Vref)

– Those pins will need to be connected on the PCB, as if you are planning for the larger device

• Vref pins connected to reference supply voltage– That is, not used as user I/O– Listed as No Connect (NC) for smaller devices

• Vcco pins connected to reference supply voltage


Package Migration Considerations

• Specific packages allow migration to a larger or smaller package

– The FG456 and FG676 packages are pinout compatible

– The FF896 and FF1152 packages are pinout compatible

• Pin definitions remain nearly identical – Some Vref pins in larger packages are

user I/O in smaller packages– LVDS pairs are different– Some user I/O are in different banks


Planning Board Layout

• Due to the board-level layout of devices, some internal layout tips may not be obeyed

– For example, for the board shown here, interface signals between the two FPGAs may not allow for the most optimal internal layout

• Attempt to take into account the optimal internal layout when performing board-level layout


I/O Layout: ReducingGround Bounce

• Simultaneously Switching Outputs (SSO) are the main cause of ground bounce

• Review the Ground Bounce Recommendation Charts in the Data Book– This chart describes the maximum number of SSO pins per power and

ground pair for Virtex-II devices– Do not exceed these ratings if possible– If you do, you may need to modify your design, your pin assignments, or

your system to reduce the risk of suffering from ground bounce • Some possible solutions are described in the notes

• PACE will help you review SSO via command Tools SSO Analysis

Rhett Whatcott:

v6.1: Added Final Bullet.

Rhett Whatcott:

v6.1: Added Final Bullet.

floorplanner: effective layout

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