floyd chapter 4 model answers

8/12/2019 Floyd Chapter 4 Model Answers

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CHAPTER 4BOOLEAN ALGEBRA AND LOGIC SIMPLIFICATION

Section 4-1 Boolean Operations and Expressions

1. X = A + B + C + D This is an OR configuration.

2. Y = ABCDE

3. X = C B A

4. (a) 0 + 0 + 1 = 1 (b) 1 + 1 + 1 = 1(c) 1 0 0 = 1 (d) 1 1 1 = 1(e) 1 0 1 = 0 (f) 1 1 + 0 1 1 = 1 + 0 = 1

5. (a) AB = 1 when A = 1, B = 1(b) C B A = 1 when A = 1, B = 0, C = 1(c) A + B = 0 when A = 0, B = 0(d) C B A = 0 when A = 1, B = 0, C = 1(e) C B A = 0 when A = 1, B = 1, C = 0(f) B A = 0 when A = 1, B = 0(g) C B A = 1 when A = 1, B = 0, C = 0

6. (a) X = ( A + B)C + B

A B C A + B ( A + B)C X 00001111

00110011

01010101

00111111

00010101

00110111

(b) X = C B A )(

A B C B A X 00001111

00110011

01010101

11000000

01000000


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(c) X = C B A + AB

A B C C B A AB X 00

001111

00

110011

01

010101

00

000100

00

000011

00

000111

(d) X = ( A + B)( A + B)

A B A + B B A X 0011

0101

0111

1101

0101

(e) X = ( A + BC ) )( C B

A B C A + BC C B X 00001

111

00110

011

01010

101

00011

111

11101

110

00001

110

Section 4-2 Laws and Rules of Boolean Algebra

7. (a) Commutative law of addition(b) Commutative law of multiplication(c) Distributive law

8. Refer to Table 4-1 in the textbook.

(a) Rule 9: A A (b) Rule 8: 0 A A (applied to 1st and 3rd terms)(c) Rule 5: A + A = A (d) Rule 6: A A = 1(e) Rule 10: A + AB = A (f) Rule 11: B A B A A (applied to 1st and 3rd terms)


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Section 4-3 DeMorgans Theorems

9. (a) B A B A B A

(b) B A B A B A

(c) C B A = C B A (d) C B A ABC

(e) C B A )()( C B AC B A

(f) DC B A CD AB (g) ))(()()( DC B A CD ABCD AB

(h) DC B A DC B A DC B A ))((

10. (a) DC B A )()( DC B A DC B A

(b) )()()()( EF CD B A EF CD AB EF CD AB

= ))(( F E DC B A

(c) DC B A DC B A D ABC DC B A )(

(d) ))(()()( DC B A DC B A DC B A DC B A

= DC B A DC B A DC B A DC B A

(e) )()())(( CD AB F E CD ABCD AB F E CD AB

= ))(())(( CD AB F E CD AB

= ABCDF E DC AB ))((

11. (a) KLM HIJ EFG ABC KLM HIJ EFG ABC ))(()()(

= ))()()(( KLM HIJ EFG ABC KLM HIJ EFG ABC

= ))()()(( M L K J I H G F E C B A

(b) BC CDC B A BC CDC B A BC CDC B A ))(())(()(

= BC DC B A BC DC B AC B A BC DC C B A )1()(

= BC C B A

(c) ))()()(( H G F E DC B A

= H G F E DC B A))()(()( H G F E DC B A


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Section 4-4 Boolean Analysis of Logic Circuits

12. (a) AB = X (b) A = X (c) A + B = X

(d) A + B + C = X

13. See Figure 4-1.

14. See Figure 4-2.

X

X


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15. See Figure 4-3.

16. (a) See Figure 4-4(a).(b) See figure 4-4(b).

17. See Tables 4-1 and 4-2.

Table 4-1INPUTS OUTPUT

VCR CAMI RDY RECORD0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 11 1 0 11 1 1 1

Table 4-2INPUTS OUTPUT

RTS ENABLE BUSY SEND0 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 01 1 1 1

FIGURE 4-3

FIGURE 4-3


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18. (a) X = A + B

A B X 0011

0101

0111

(c) X = AB + BC

A B C X 00001111

00110011

01010101

00010011

(b) X = AB

A B X 0011

0101

0001

(d) X = ( A + B)C

A B C X 00001111

00110011

01010101

00010101

(e) X = ))(( C B B A

A B C A + B C B X 000011

11

001100

11

010101

01

001111

11

110111

01

000111

01

Section 4-5 Simplification Using Boolean Algebra

19. (a) A( A+ B) = AA + BB = A + AB = A(1 + B) = A

(b) AB AAB A A AB A A 0)( AB

(c) )( B BC C B BC = C (1) = C

(d) B A A AA B A A A )( = A + (0) B = A + 0 = A

(e) )1()( C AC B A B BC AC B AC B A BC AC B A

= C BC A )()( B AC B A AC C AC B A


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20. (a) C B B A AC AC B B A AC AAC A B A ))((

= C B A C B AC B BC A )1()1(

(b) )1()1( B A E DC CDC B A E DC B A BCD AC B A B A

= B A

(c) AC BC A AB AC B A AB AC AB AB )()1()1( BC AC BC AC BC A AC BC A B A

= A + C (d) C AB A AB AC AAB AABC AB AB A A ))((

= AB)1(00 C ABC AB AB

(e) C B A AB ABC BC A AB ABC B A AB )()(

= C AB C AB AB

21. (a) F D D D BE BD BD F D D E D B BD )()(

= F D BE BD

F D BE BD 0(b) DC B AC B A DC B AC B AC B A DC B AC B AC B A )(

= D B AC B A )()( DC B A DC C B A

(c) ))()(1())()(( D BC BC B D BC B B BC B = ))(())(())(( D B BC B D B BC BB D BC B B = B(1 + C )( B + D) = B( B + D) = BB + BD = B + BD = B(1 + D) = B

(d) CD B A DC AB ABCDCD ABCD AB ABCD )()()()(

= CD BCD A D ABC AB ABCD = D ABC AB B A BCD D ABC AB B A ABCD )()(

= ABCD)()1( CD ABCD D ABC ABCD D ABC AB ACD (e) )()]([ AC BC C ABC ABABC AC BC C AB ABC

= ABC + 0( BC + AC ) = ABC


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22. First develop the Boolean expression for the output of each gate network and simplify.

(a) See Figure 4-5.

X = D AC C A A B B A D AC C B A B DC AC B A )()(

= D AC C B B A

ACDC A B )(

(b) See Figure 4-6.

X = D AC B A D AC C B AC B A D AC B A )1(

(c) See Figure 4-7.

X = DC B B A No further simplification is possible.

FIGURE 4-5

FIGURE 4-6

FIGURE 4-7


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(d) See Figure 4-8.

X = D AC B A No further simplification is possible.

Section 4-6 Standard Forms of Boolean Expressions

23. (a) B A BC AC B A B B BC AC BC B A ))(((b) C B AC CC B AC C C B A )((c) ( A + C )( AB + AC) = AAB + AAC + ABC + ACC = AB + AC + ABC + ACC

= ( AB + AC )(1 + C ) = AB + AC

24. (a) CDCD B A ABCDCDCD B A ABCD B ACD AB )(

= CD AB CD B A AB )1(

(b) ABD ABBDC B AB BDC B AB 0)( = ABD

(c) BDC B ABC A DC B AC B A )(])([

= )1()1( C BD A DC B BD BC A DC B BD ABC A = A + BD

25. (a) The domain is A, B, C The standard SOP is: BC A ABC C B AC B A

(b) The domain is A, B, C The standard SOP is: C B AC B A ABC

(c) The domain is A, B, C The standard SOP is: C B AC AB ABC

26. (a) AB + CD = CD B A BCD ACD B A DC AB DC AB D ABC ABCD (b) ABD = DC AB ABCD (c) A + BD = DC AB DC ABCD B A DC B A DC B A DC B A

+ BCD A DC B A ABCD D ABC

FIGURE 4-8


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27. (a) : BC A ABC C B AC B A 101 + 100 + 111 + 011(b) :C B AC B A ABC 111 + 101 + 001(c) :C B AC AB ABC 111 + 110 + 101

28. (a) :CD B A BCD ACD B A DC AB DC AB D ABC ABCD 1111 + 1110 + 1101 + 1100 + 0011 + 0111 + 1011

(b) : DC AB ABCD 1111 + 1101(c) DC AB DC ABCD B A DC B A DC B A DC B A

+ : BCD A DC B A ABCD D ABC 1000 + 1001 + 1010 + 1011 + 1100 + 1101 + 1110 + 1111 + 0101 + 0111

29. (a) ))()()(( C B AC B AC B AC B A

(b) ))()()()(( C B AC B AC B AC B AC B A

(c) ))()()()(( C B AC B AC B AC B AC B A

30. (a) ))()()()(( DC B A DC B A DC B A DC B A DC B A

))()()(( DC B A DC B A DC B A DC B A

(b) ))()()(( DC B A DC B A DC B A DC B A

( )( )( )( )( ) A B C D A B C D A B C D A B C D A B C D

))()()()(( DC B A DC B A DC B A DC B A DC B A

(c) ))()()(( DC B A DC B A DC B A DC B A

))(( DC B A DC B A

Section 4-7 Boolean Expressions and Truth Tables31. (a) Table 4-3

A B C X00001111

00110011

01010101

00100101

(b) Table 4-4 X Y Z Q00001111

00110011

01010101

11010110


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32. (a) Table 4-5 A B C D X0000000011111111

0000111100001111

0011001100110011

0101010101010101

1000011001000000

(b) Table 4-6W X Y Z Q0000000011111111

0000111100001111

0011001100110011

0101010101010101

0000000100010111

33. (a) C B AC B AC ABC B A BC AC B AC AC AB B A

(b) X Y Z WZ X YZ W XY Z W XYZ W XY Z W XYZ + Z Y X W Z Y X W Z XY W Z Y X W + WXYZ Z WXY Z Y WX YZ X W Z Y X W

Table 4-7 A B C X00001111

00110011

01010101

10110110

Table 4-8W X Y Z Q 0000000011111111

0000111100001111

0011001100110011

0101010101010101

1111011011110111


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34. (a) Table 4-9 A B C X00001111

00110011

01010101

01011110

(b) Table 4-10 A B C D X 0000000011111111

0000111100001111

0011001100110011

0101010101010101

1111100110011111

35. (a) Table 4-11 A B C X00001111

00110011

01010101

00011111

(b) Table 4-12 A B C D X 0000000011111111

0000111100001111

0011001100110011

0101010101010101

1011000010011111

36. (a) X = ABC C B AC B AC B A X = ))()()(( C B AC B AC B AC B A

(b) X = ABC C B AC AB X = ))()()()(( C B AC B AC B AC B AC B A

(c) X = DC AB DC B A D BC A DC B ACD B A DC B A DC B A X = ))()()()(( DC B A DC B A DC B A DC B A DC B A



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(d) X = ABCD DC ABCD B A BCD A DC B A DC B A DC B A X = ))()()()(( DC B A DC B A DC B A DC B A DC B A


Section 4-8 The Karnaugh Map

37. See Figure 4-9.

38. See Figure 4-10.


Section 4-9 Karnaugh Map SOP Minimization


FIGURE 4-9 FIGURE 4-10 FIGURE 4-11

FIGURE 4-12


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42. (a) ABC C B AC C AB ABC C B A AB )(

= ABC C B AC AB ABC

= C ABC B A ABC

(b) BC A AC C B A AB BC A AC C B B A BC A )())(()())((

= ABC BC AC B AC B AC AB ABC = BC AC B AC B AC AB ABC

(c) D BC A DC B D AC DC B A = D BC A DC B A ACD B B A DC B A )()( =

= D BC A DC B A DC AB DC B A D ABC DC B A

(d) ABCD DC BCD DC B A B A = ABCD DC B A ACD B B A A DC B A D DC C B A )())(())((

= BCD ACD B A ABCD DC B A ABCD D ABC DC B A DC B A ABCD DC B A DC ABCD B A

= DC B A DC ABCD B A BCD ACD B A ABCD D ABC DC B A DC B A = D ABC ABCD DC ABCD B A DC B A DC B A BCD A DC B ACD B A

F E F D X

FIGURE 4-13


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FIGURE 4-14

FIGURE 4-15


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45. Plot the 1s from Table 4-11 in the text on the map as shown in Figure 4-16 and simplify.

46. Plot the 1s from Table 4-12 in the text on the map as shown in Figure 4-17 and simplify.


FIGURE 4-16

FIGURE 4-17

FIGURE 4-18


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Section 4-10 Five-Variable Karnaugh Maps

48. . X AB CDE A BCDE See Figure 4-19.


FIGURE 4-20

FIGURE 4-19


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Section 4-11 Describing Logic with an HDL

51. entity AND_OR isport (A, B, C, D, E, F, G, H, I: in bit; X: out bit);

end entity AND_OR;architecture Logic of AND_OR is begin

X


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55. The standard SOP expression for segment c is:c = 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H This expression is minimized in Figure 4-22.

56. The standard SOP expression for segment d is:d = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H This expression is minimized in Figure 4-23.

FIGURE 4-23

FIGURE 4-22

The standard expression requires three 4-input AND gates, one 3-input OR gate, and 3 inverters.The minimum expression requires two 2-input AND gates, one 2 input OR gate, and 2 inverters.

The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.The minimum expression requires one 2-input AND gates, one 3-input AND gate, one 2-inputOR ate and 2 inverters.


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The standard SOP expression for segment e is:e = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H H H H H This expression is minimized in Figure 4-24.

The standard SOP expression for segment f is: f = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H This expression is minimized in Figure 4-25.

FIGURE 4-25

FIGURE 4-24

The standard expression requires five 4-input AND gates, one 5-input OR gate, and 3 inverters.The minimum expression requires one 3-input AND gate.

The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.The minimum expression requires one 2-input AND gate.


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The standard SOP expression for segment g is: g = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H This expression is minimized in Figure 4-26.

Special Design Problems

57. Connect the OR gate output for each segment to an inverter and then use the inverter output to

drive the segment with a HIGH.

58. See Figure 4-27. F = 1111The expression for segment a to include the letter F is:a = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H The expression is minimized in Figure 4-27.

FIGURE 4-26

FIGURE 4-27

The standard expression requires four 4-input AND gates, one 4-input OR gate, and 3 inverters.The minimum expression requires one 2-input AND gates, one 3-input AND gate, one 2 inputOR ate and 2 inverters.


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59. See Figure 4-28. Segment b is used for letters A and d .b = 3 2 1 0 3 2 1 0 H H H H H H H H

See Figure 4-29. Segment c is used for letters A, b, and d .c = 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H

FIGURE 4-28

FIGURE 4-29


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See Figure 4-30. Segment d is used for b, C , d , and E .d = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H

See Figure 4-31. Segment e is used for A, b, C , d , E , and F .e = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H H H H H H H H H

FIGURE 4-30

FIGURE 4-31

Since segment e is active-LOW for all letters, e = 0.


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See Figure 4-32. Segment f is used for A, b, C , E , and F . f = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H H H H H

See Figure 4-33. Segment g is used in A, b, d , E , and F . g = 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 H H H H H H H H H H H H H H H H H H H H

FIGURE 4-32

FIGURE 4-33


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Chapter 4

60. The invalid code detector must disable the display when any numerical input (0-9) occurs. AHIGH enables the display and a LOW disables it. A circuit that detects the numeric codes and

produces a LOW is shown in Figure 4-34.

Multisim Troubleshooting Practice

61. Input A inverter output open.

62. Input A of segment e OR gate open.

63. Segment b OR gate output open.

FIGURE 4-34

floyd chapter 4 model answers

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