fluxing_underfill

7/28/2019 Fluxing_Underfill

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Processing of Fluxing Underfills for Flip Chip-on-Laminate Assembly

Renzhe Zhao &

R. Wayne JohnsonLaboratory for Electronics

Assembly & Packaging Auburn University

162 Broun Hall, ECE Dept.

Auburn, AL 36489 USA334-844-1880

[email protected]

Greg Jones

KIC15950 Bernardo Center Dr.,

Suite ESan Diego CA 92127

775-322-0158

[email protected]

Erin Yaeger, Mark

Konarski, Paul Krug &Larry Crane

Henkel-Loctite Corporation15051 E. Don Julian Rd.

Industry, CA 91746

800-827-2207 [email protected]

Abstract

Fluxing underfill eliminates process steps in the assembly of flip chip-on-laminate(FCOL) when compared to conventional capillary flow underfill processing. In the

fluxing underfill process, the underfill is dispensed onto the board prior to die placement.

During placement, the underfill flows in a squeeze flow process until the solder ballscontact the pads on the board. The material properties, the dispense pattern, and resulting

shape, solder mask design pattern, placement force, placement speed, and hold time all

impact the placement process and the potential for void formation. A design of

experiments was used to optimize the placement process to minimize placement-inducedvoids. The major factor identified was board design, followed by placement acceleration.

During the reflow cycle, the fluxing underfill provides the fluxing action required

for good wetting and then cures by the end of the reflow cycle. With small,homogeneous circuit boards it is relatively easy to develop a reflow profile to achieve

good solder wetting. However, with complex SMT assemblies involving components

with significant thermal mass this is more challenging. To get the large thermal masscomponents to temperature, the small flip chip die will be at higher temperatures for

longer periods of time. Use of predictive software tools to optimize the reflow profile

and minimize temperature differences across the board is required. A series ofexperiments were performed using these tools to optimize the reflow profile of a complex

FCOL/SMT assembly. The profile obtained was used to successfully assemble flip chip

die with fluxing underfill.

In liquid-to-liquid thermal shock testing (-40oC to +125

oC, 5 minute hold times

and 1 minute transition), the characteristic life of the assembly was 1083 cycles and thefirst failure occurred at 992 cycles.

Index Terms: Flip chip, No-flow, fluxing underfill, assembly, DOE, SMT, reliability.


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Introduction

Flip chip on laminate (FCOL) provides advantages in size, weight andperformance for portable products. However, the industry has been slow in adopting

FCOL technology. One issue often cited is the equipment and time associated with

capillary underfill dispense, flow and cure. Fast flow, snap cure underfills are one

solution to decreasing dispense, flow and cure times in a high volume productionenvironment [1,2].

An alternate approach is to use fluxing underfills [3-8]. Fluxing underfills are

polymer systems that incorporate fluxing activity into an underfill. Fluxing underfillscontain three basic components, epoxy resins to provide the cured structure, fluxing

materials such as organic acids in sufficient quantity as to remove the oxides and a

catalyst to cure the material. The catalyst is chosen to provide latency until the solderstarts to melt.

Prior to assembly, the boards must be dehydrated to remove absorbed moisture

and to ensure the solder mask has been fully cured. Moisture and volatiles from undercured solder mask can cause bubbles (voids) in the fluxing underfill during the reflow

temperature cycle.The fluxing underfill is dispensed onto the dehydrated PWB at the flip chip site

and the die is placed through the fluxing underfill. During placement, the underfill flowsin a squeeze flow process until the solder balls contact the pads on the board. Ideally,

the fluxing underfill will make initial contact with the center of the die and flow radially

outward as the die is placed. This would happen if the bottom of the flip chip were a flatplate as is usually assumed in squeeze flow models. However, flip chip die have solder

balls that interfere with the ideal flow pattern. Voids (trapped air) can be created in the

underfill near the solder balls during placement. The viscosity, surface tension andwetting characteristics of the underfill along with the placement parameters of force,

velocity or acceleration and hold time affect the formation of these placement voids. Theoptimization of placement parameters through a design of experiments is discussed in a

later section.

The assembly is then sent through a reflow oven. The fluxing underfill providesthe necessary fluxing activity for good solder wetting. Depending on the cure kinetics,

the underfill may cure during the reflow cycle or a post reflow cure may be required.

The reflow profile and cure kinetics are important for high yield assembly. As the

underfill temperature increases during the reflow cycle, the viscosity of the underfilldecreases. However, as cure is initiated the viscosity of the underfill will increase. When

the solder melts and begins to wet to the substrate metallization, the viscosity of the

underfill must be low enough to allow collapse of the chip. Failure of the chip to collapsewill result in poor or open solder joints.

With small, homogeneous circuit boards it is relatively easy to develop a reflow

profile to achieve good solder wetting. However, with complex SMT assembliesinvolving components with significant thermal mass, this is more challenging. To get the

large thermal mass components to temperature, the small flip chip die will be at higher

temperatures for longer periods of time. Use of predictive software tools to optimize thereflow profile and minimize temperature differences across the board is required. A series

of experiments were performed using these tools to optimize the reflow profile of a

complex FCOL/SMT assembly. The details are presented in a later section.


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Test Vehicles

For the reflow profile studies when assembled with complex SMT, the test board

shown in Figure 1 was used. The board is 4.0 x 6.0 x 0.060. The components

assembled onto the board are listed in Table 1. Flip chips are assembled on the bonding

sites U261, U262, U232 and U233. The CBGA (U204) is a thick ceramic componentwith relatively large thermal mass.

Figure 1. Photograph of Test Vehicle Used in Reflow Profile Experiments.

Table 1. Components on Test Vehicle (Figure 1).

Description Pitch Ball Diameter Length x Width height Reference Designators

PBGA 352 I/O 0.050" (1.27mm) .030" (.75mm) 1.38" SQ .090" u201CBGA 360 I/O 0.050" (1.27mm) .035" (.89mm) .983" SQ .200" u204

Column Grid Array 360 I/O 0.050" (1.27mm) column .035 dia x .065 tall .983" SQ .120" u204

Flex PBGA 144 I/O (uBGA) 0.033" (.80mm) .020" (.5mm) .473" SQ .043" u205 - u208,u230,u231

DCA 96 I/o (flipchip) .017" (.45mm) .008" (.19mm) .500" SQ .030" u261, u262

DCA 48 i/o (flipchip) .017" (.45mm) .008" (.19mm) .250" SQ .030" u232, u233

Tape array BGA 96 I/O (CSP) .020" (.5mm) .012" (.3mm) .317" SQ .038" u251, u252

BGA 46 I/O .030" (.75mm) .012" (.3mm) .223" x .305" .033" u237 - u242

BGA 48 I/O .030" (.75mm) .020" (.5mm) .197" x .324" .030" u211 - u214, u218, u220

Mini BGA 48 I/O .030" (.75mm) .012" (.3mm) .275" SQ .044" u217, u219

Two types of PB8 2x2 test boards were used for the placement optimization

study. One is a finger pattern design and the other one is a trench pattern design, as

shown in Figures 2 and 3. The test boards have 10 die sites on each board. The boards arefour-layer constructions of FR-4 epoxy with glass fiber reinforcement. The board surface

finishes are electroless nickel/immersion gold. The PB8 22 die is 0.200 x 0.200 andhas solder balls on 0.008 pitch. All test dies are daisy-chained structures with eutectic

Sn-Pb solder bumps and silicon nitride passivation.Loctite FMD 806 and Loctite 3594 fluxing underfills were used for the process

development. These underfills cure during the reflow cycle, eliminating the need for a

post reflow cure.

U20

U20

U230

U26U232

U251 U241

U218

U217


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Figure 2. Photograph of Finger Board

Design.Figure 3. Photograph of Trench Board

Design.

Reflow Profile Development

The reflow profile experiments were performed in a Heller 1800 reflow oven with9 zones. For the profile development, a SlimKIC 2000 profiling system was used. This

automated prediction tool allows users to predict how changes to belt speed and oven set

points will affect a product profile. The software option can create and evaluate billionsof potential oven recipes, automatically selecting the recipe that best fits the process

window in about a minute. The automated predictive tool is designed to center the profile

in a process window designated by the user, who may set limits particular to their

processes.For the initial profile development, a maximum ramp rate, soak time between

140oC and 155

oC, time above 183

oC, and peak temperature were input into the software

based on the fluxing underfill processing recommendations. An initial profile was set intothe reflow oven based on past flip chip reflow experience. Thermocouples were located

underneath components U261 (flip chip), U207 (flex PBGA), U201 (PBGA), U204

(CCGA), U252 (TABGA), U237 (BGA), and U219 (mini BGA). Figure 4 shows theresults of the initial profile.


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Figure 4. Initial Reflow Profile.

The profile for the flip chip die was within an acceptable range. However, asexpected, the ceramic column grid array profile was on the low end and marginal. The

peak temperature was 208.8oC (11.3

oC cooler than the flip chip). The soak time for the

CCGA was only 37 seconds and the time above 183oC was 65.7 seconds.

The software identified the CCGA as not within specifications and provided

recommendations for new oven set points. Following an iterative process of profiling and

following refined recommendations from the software a profile was quickly achieved

with nearly equal soak times and times above 183o

C for all components. The differencein peak temperature between the flip chip and the CCGA was 9.4

oC, an acceptable

difference. The profile is shown in Figure 5.

Flip chip dies were assembled and reflowed using this profile. Fluxing underfillFMD-806 was used for the assembly. The electrical assembly yield was 0%. Figure 6

shows a cross section of one of the dies. There is no wetting of the solder to the copper

pad. In the preliminary tests, the underfill showed good fluxing activity and no diefloating. Thus, the reflow process likely caused the non-wetting of the solder. To verify

this, Differential Scanning Calorimetry (DSC) analysis was conducted. Figure 7 shows

DSC results for FMD-806 fluxing underfill at the heating rate of 20C/min. From the

DSC analysis, the onset temperature for curing is around 150C, and the curing reaction

peak is at 194C. It is obvious that the long time period between 140-183C of the profilein Figure 5 had initiated underfill gelation before the solder melts. In other words, thefluxing underfill had cross-linked and its viscosity increased sufficiently prior to melting

of the solder balls to prevent collapse.


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Figure 5. Optimized Reflow Profile Based on Initial User Inputs.

Figure 6. Cross-section Showing No Solder Wetting with the Profile in Figure 5.


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Figure 7. DSC Analysis for Fluxing Underfill FMD-806.

In reviewing the two profiles, the optimized profile is approximately 100

seconds longer than the original profile. This additional time prior to melting of thesolder was sufficient for significant cross-linking of the underfill. In the profile

optimization, no constraint was placed on profile length.The software allows time constraints, so a time constraint of 180-200 seconds

above 140oC was added to reduce the heating time prior to the melting point of the solder

alloy. The profile iteration was repeated with the additional constraint and the profileshown in Figure 8 was obtained. The soak time for all components was approximately the

same and the time above 183oC was only about 10 seconds less for the CCGA. The peak

temperature difference between the CCGA and the flip chip die was less than 8oC

(223.4oC vs. 215.5

oC).


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Figure 8. Final Reflow Profile.

Figure 9 is a cross-section of a flip chip solder joint reflowed with the finalprofile. Excellent wetting of the copper trace is observed.

Figure 9. Cross-section of Flip Chip Solder Joint Obtained with Final Reflow Profile.


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Placement Optimization

A Camalot 3700 dispense system, a Siemens F5 pick & place system and a Heller1800 reflow oven were used in the placement optimization study. The fluxing underfill

used was Loctite 3594. The experiment was designed using Taguchis parameter design

(PDE) method. The PDE is based on classical fractional factorial designs. In the factorial

design, the effects of the experimental noise factors are averaged out over all treatmentcombinations (TCs) through randomization. Unlike the factorial designs, Taguchis

method imbeds the noise factors in the design of the experiment so that randomization is

generally unnecessary. Experimental noise factor is defined as those variables that areeither too difficult or too expensive to control in Taguchis parameter design. For

example, environmental conditions, deterioration of parts, material and subcomponents,

and piece-to-piece variation belong to noise factors. Based on Taguchis parameterdesign, optimal factor levels can be selected in order to make the product more robust

against noise.

In a previous experiment [9], four controllable factors, underfill volume,placement acceleration, placement force and placement dwell time, were studied by

Taguchis design of L9(3

4

). Placement acceleration and placement force were identifiedas important parameters, and underfill volume and placement dwell time were less

important parameters.In this experiment, the objective was to refine the parameter range selected based

on the previous results. The board design was also studied. Taguchis L18(2137) design

was used. There were four controllable factors, board design, placement acceleration,

placement force and placement dwell time. The board design has two levels and all other

factors have three levels as shown in Table 2. Placement site (die site) was taken as anoise factor, referring to samples 1 to 4. The response variables are assembly yield and

placement underfill voids. The design layout is shown in Table 3.

Table 2. Controllable FactorsControllable Factor Level 1 Level 2 Level 3

A: Board Design Finger Trench -

B: Placement Acceleration 0.1g 1.3g 2.6g

C: Placement Force 1N 3N 5N

D: Placement Dwell Time 0s 1.5s 3s


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Table 3. The Design Layout and Experimental Results

Underfill VoidsExp.

No.

Board

Design

Placement

Acceleration

Placement

Force

Placement

Dwell Time

Pattern

Sample 1 Sample 2 Sample 3 Sample 4

A

Y

1 Finger 0.1 1 0 ---- 1 3 5 4

2 Finger 0.1 3 1.5 --00 3 0 3 1

3 Finger 0.1 5 3.0 --++ 2 1 1 4

4 Finger 1.3 1 0 -0-- 0 4 3 0

5 Finger 1.3 3 1.5 -000 4 2 3 6

6 Finger 1.3 5 3.0 -0++ 8 4 5 6

7 Finger 2.6 1 1.5 -+-0 3 8 10 16

8 Finger 2.6 3 3.0 -+0+ 2 12 8 8

9 Finger 2.6 5 0 -++- 22 29 7 14

10 Trench 0.1 1 3.0 +--+ 3 0 0 0

11 Trench 0.1 3 0 +-0- 1 1 2 2

12 Trench 0.1 5 1.5 +-+0 3 6 6 6

13 Trench 1.3 1 1.5 +0-0 2 8 7 5

14 Trench 1.3 3 3.0 +00+ 0 0 0 1

15 Trench 1.3 5 0 +0+- 0 0 1 0

16 Trench 2.6 1 3.0 ++-+ 1 1 0 0

17 Trench 2.6 3 0 ++0- 0 0 0 1

18 Trench 2.6 5 1.5 +++0 0 0 3 0


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The PB8 2x2 test vehicle was used in the experiment and the PWBs were

dehydrated at 125C for 24 hours before assembly. Quartz die were used initially toverify that voids observed after reflow were due to placement and not out gassing or

moisture generated/liberated during the reflow profile. The underfill volume used was

0.006ml. A single dot was dispensed in the center of the die site. The reflow profile used

matched the final profile developed in the reflow profile development study. Theassembly results are listed in Table 3.

The assembly yield was 100% yield for all placement conditions. That means the

factors at current levels do not affect the assembly yield. To examine the die forplacement voids, both C-SAM images and flat-sections (polish the die away) were

examined. Since the voids were near the edge of the die, flat-sectioning provided a better

method for identifying and counting voids. Figure 10 shows examples of placementvoids. For response variable underfill voids, the design type is smaller-the-better (STB)

because less underfill voiding is desired.

(a)

(b)

Figure 10. Examples of Placement Voids Seen in A Polished Flat-section.

(a) Finger design board, (b) Trench design board


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According to Taguchis design, the signal to noise (S/N) ratio, db , for STB was

calculated with this equation:

=

=n

i

idb yn 1

2

10

1log10

where, n is the total number of samples andyi is the value for response variable. In our

case,yi is the number of underfill voids and n = 4. Table 3 gives the db .

JMP 4.0.2 statistical analysis software was employed to analyze the data from

Table 3. Figure 11 shows the prediction profile for mean underfill voids and S/N ratio.The ANOVA table for mean voids is shown in Table 4. From Figure 11 and Table 4,

variable A (board design) is a strong factor, variables B (placement acceleration) and C

(placement force) are moderate factors, and variable D (placement dwell time) is a weak

factor. The prediction profile indicates that the board design has the strongest linear effectand the placement force has the strongest quadratic effect.

MeanUnderfillVoids 18

-8.22

-1.95833

SN

RatioUnderfillVoids 16.56

-30.82

3.292556

Board DesignFinger

Trench

Acceleration

0.1

1.3

2.6

Force

1 3 5

Dwell Time

01.5

3.0

Figure 11. The Prediction Profile for Mean Underfill Voids and S/N Ratio

Table 4. ANOVA Table of Mean Voids

Source DF SS MS Ranks

Board Design 1 80.2222 80.2222 1

Placement Acceleration 2 46.7569 23.3785 2

Placement Force 2 24.7778 12.3889 3

Placement Dwell Time 2 8.8819 4.4410 4


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Based on the analysis above, the optimal parameter level for voids reduction isA2B1C2D3. In other words, the optimal combination is board design at level 2 (trench),

placement acceleration at level 1 (0.1g), placement force at level 2 (3N), and placement

dwell time at level 3 (3s).

After determining the optimal parameter combination, experiments wereconducted to verify the best condition. Figure 12 shows that void-free assembly was

achieved with the optimized parameters. The assembly yield was 100% and excellent

solder wetting is shown in Figure 13.

(a)

(b)

Figure 12. Void Free Assembly with Optimized Placement Parameters.


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Figure 13. Cross-section Showing Excellent Wetting with Optimized Assembly Process.

Reliability Test

A liquid-to-liquid thermal shock test was conducted to evaluate the reliability ofthe assembly with fluxing underfill Loctite FMD-806. The PB8 finger design boards

were used in the assemblies. Two boards (20 dies) were tested. All assemblies were void-

free and with excellent solder wetting onto the substrate pads. The cycle was from -40C

to +125C with 5 minutes at each temperature extreme and 1-minute transition time. Theresistance of the daisy chain was monitored in-situ to accurately determine the cycles-to-

failure.

The failure of an assembled die was defined as a resistance increase of 3 over

the initial resistance of the flip chip daisy chain and measurement wiring (nominally 4).The tests were terminated at 1300 cycles. After the test vehicles were removed from the

thermal chamber, a series of examinations were performed to investigate the failure

mode, including visual inspection for underfill fillet and die cracking, C-SAM forunderfill delamination, X-ray and flat polishing for solder ball shorting, and cross-section

for solder fatigue crack.

Figure 14 shows the Weibull plot of the thermal test results. The characteristic lifewas 1083 cycles and the first failure occurred at 992 cycles.


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Figure 14. Weibull plot of the thermal shock test data.

At most of the die sites, a number of underfill fillet cracks were observed, as

shown in Figures 15. It can be seen that most of the cracks are vertical fillet cracks. Some

of these cracks extended into the PWB, so board cracks were expected. The flat polishingalso revealed underfill bulk cracks existed. Solder had intruded into the bulk cracks and

solder shorting between solder balls had occurred.

Figure 15. An Example of Underfill Fillet Cracks.


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A typical C-SAM image is shown in Figure 16. There is significant delamination

observed at the edges of the die. The SEM picture of a cross-section, as shown in Figure17, also verifies this delamination.

Underfill delamination is the phenomena of underfill losing adhesion to the

silicon die. It is usually initiated at the corner of dies. After initiation, the delamination

can rapidly spread over the chip surface toward the center of die. This will degrade theperformance of the assembly. As a result, solder joints will undergo a larger amount of

shear stress due to the mismatch of CTEs between the chip and PWB. This shear stress

would greatly impact the solder joint life and cause solder fatigue.

Figure 16. Typical C-SAM Image Showing delamination.

Figure 17. Cross-section Showing Underfill Delamination.

Silicon Die

Underfill

Underfill

Delamination


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A few dies were cross-sectioned to identify the solder fatigue cracks. A typical

cross-section SEM picture of a failed solder joint with fatigue cracks is shown in Figure18. The SEM image indicates the solder fatigue cracks appear not only near the UBM,

but also other regions of the solder joint. In the assemblies, bulk underfill cracks, PWB

cracks and underfill delamination were also observed after the thermal shock test cycles.

Solder can extrude into these cracks and delaminated regions. Because of the solderextrusion, the solder joints lost volume, resulting in faster fatigue or creep behavior. The

solder extrusion into underfill bulk cracks between adjacent solder balls can also cause

solder shorts. Figure 19 shows an example of the solder shorts. From the previousexperiments, the open failure of the PB8 assemblies always occurs earlier than the solder

shorts.

Figure 18. Cross-section of Solder Joint Showing Solder Fatigue Crack.

Figure 19. X-ray analysis showing solder shorts.


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Summary

Fluxing underfills offer an alternative to capillary flow underfills in the assembly

of flip chip on laminate. Successful assembly requires development of optimized

placement parameters to eliminate placement-induced voids. The parameters will be a

function of the specific die and underfill used.The reflow profile can be optimized using predictive software for complex PWBs

with a wide range of component sizes and thermal masses. Care must be used to establish

the proper constraints for the software.

References

1. Daniel Baldwin, Paul N. Houston, M. Deladisma, Larry Crane, and Mark, M.Kornaski., Processing and Reliability of Fast Flow, Snap-Cure UnderfillsPart I:Processing and Moisture Sensitivity, IEEE Transaction on Electronics Packaging

Manufacturing, Vol. 23, No. 4 October 2000, pp 259-266

2. Jing Qi, R. Wayne Johnson, Erin Yaeger, Mark Konarski, Todd Doody, Z. AndrewSzczepaniak, and Larry Crane, Manufacturability Issues in Flip Chip on Laminate

Assembly, International Journal of Microcircuits and Electronic Packaging, Vol. 22,No. 3, 3rd Qtr., 1999, pp. 270--279.3. R. Pennisi, Adhesive and Encapsulating Material with Fluxing Properties, U. S.

Patent 5 128 746

4. D. R. Gamota and C. M. Melton,, The Development of Reflowable MaterialsSystems to Integrate the Reflow and Underfill Dispensing Processes for DCA/FCOBAssembly, IEEE Transactions on Components, Packaging, and Manufacturing

Technology, Part C: Manufacturing, Vol. 20, No. 3, 1997, pp. 183-187.

5. D. R. Gamota and C. M. Melton, Materials to Integrate the Solder Reflow andUnderfill Encapsulation Processes for Flip Chip on Board Assembly,IEEE

Transactions on Components, Packaging, and Manufacturing Technology, Part C:Manufacturing, Vol. 21, No. 1, 1998, pp. 57-65.

6. Doug Katze, No-Flow Fluxing Underfill Process Characterization, Proceedings ofthe 2001 APEX Conference, San Diego, CA, January 14-18 2001, pp. MT2-2 1 toMT2-2 9.

7. Michael A. Previti, No-Flow Underfill: A Reliability and Failure Mode Analysis,Proceedings of the 2001 APEX Conference, San Diego, CA, January 14-18 2001, pp.MT2-1 1 to MT2-1 5.

8. N. W. Pascarella and D. F. Baldwin, Cost Analysis for Low Cost High ThroughputNext Generation Flip Chip Assembly, International Journal of Microcircuits &

Electronic Packaging, Vol. 20, No. 4, 1997, pp. 571-577.9. Renzhe Zhao, Prasanna Kulkarni, Yun Zhang, R. Wayne Johnson, Paul Krug, Erin

Yaeger and Larry Crane, Assembly with Fluxing Underfills: Modeling and

Experimentation, presented at the IMAPS Topical Workshop on Flip ChipTechnology, Austin TX, June 18-20 2001.

AcknowledgementsThe authors would like to recognize Siemens Dematic, Speedline Camalot and

Heller Industries for providing equipment used in this research. The project is funded by

NIST ATP program under Cooperative Agreement #70NANB8H007.

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