July 2004

Designing an off-line power supply involves many aspects ofelectrical engineering: analog and digital circuits, bipolar andMOS power device characteristics, magnetics, thermalconsiderations, safety requirements, control loop stability, etc.This represents an enormous challenge involving complextrade-offs with a large number of design variables. As a result,new off-line power supply development has always been tediousand time consuming even for the experts in the field. Thisapplication note introduces a simple, yet highly efficientmethodology for the design of TOPSwitch-GX family basedoff-line power supplies. For TOPSwitch-GX Flyback designs,Power Integrations recommends the use of PI Expert whichimplements this design methodology and also includes aknowledge base and optimization feature for making key designchoices, further reducing design time.

IntroductionThe design of a switching power supply, by nature, is aniterative process with many variables requiring adjustment tooptimize the design. The design method described in thisdocument consists of two major sections: A design flow chart

and a step-by-step design procedure. The flow chart shows thedesign sequence at a conceptual level for TOPSwitch-GXflyback power supply design. The step-by-step procedure givesdetails within each step of the design flow chart, includingempirical design guidelines and look-up tables. All key equationsand guidelines are provided wherever possible to assist thereaders in better understanding and/or further optimization.

Basic Circuit Configuration

Because of the high level integration of TOPSwitch-GX, manypower supply design issues are resolved in the chip. Far fewerissues are left to be addressed externally, resulting in onecommon circuit configuration for all applications. Differentoutput power levels may require different values for somecircuit components, but the circuit configuration staysunchanged. TOPSwitch-GX is a feature-rich product family.Advanced features like under-voltage, overvoltage, externalILIMIT, line feed forward, and remote ON/OFF are easilyimplemented with a minimal number of external components,but do involve additional design considerations. Please refer tothe TOPSwitch-GX data sheet for details. Other application

Figure 1. Typical TOPSwitch-GX Flyback Power Supply.

D

S

CCONTROL

L

FX

+VD-

VAC+VDB-

Clamp Zener

PI-3038-091102

VO

CIN

VB+

-

Output Capacitor Output Post Filter L, C

Bias Capacitor

Blocking Diode

CONTROL Pin Capacitor and Series Resistor

External ILIMIT Resistor(optional)

Line SenseResistor

fS = 132 kHz if connected as shown.For fS = 66 kHz, connect "F" Pin to "C" Pin(fS option not available with P or G package)

Feedback Circuit

CONTROLCONTROL

TOPSwitch-GX

+

-

+

TOPSwitch-GX FlybackDesign MethodologyApplication Note AN-32

AN-32

2 C7/04

specific issues such as constant current, constant power outputs,etc. are beyond the scope of this application note. However,such requirements may be satisfied by adding additional circuitryto the basic converter configuration. The only part of the circuitconfiguration that may change from application to applicationis the feedback circuitry. Depending on the power supply outputspecifications, one of the four feedback circuits, shown inFigures 3, 4, 5 and 6, will be chosen for the application.

The basic circuit configuration used in TOPSwitch-GX flybackpower supplies is shown in Figure 1, which also serves as thereference circuit for component identifications used in thedescription throughout this application note.

Design Flow

Figures 2A, 2B and 2C present a design flow chart showing thecomplete design procedure in 37 steps. With the basic circuitconfiguration shown in Figure 1 as its foundation, the logicbehind this design approach can be summarized as follows:

1. Determine system requirements and decide on feedbackcircuit accordingly.

2. Choose the smallest TOPSwitch-GX capable of therequired output power.

3. Design the smallest transformer for the TOPSwitch-GXchosen.

4. Select all other components in Figure 1 to complete thedesign.

Figure 2A. TOPSwitch-GX Design Flow Chart. Step 1 to 11.

1. System RequirementsVACMIN, VACMAX, fL, VO, PO, , Z

2. Choose Feedback Circuit & VB

3. Determine CIN, VMIN, VMAX

4. Determine VOR, VCLO

6. Determine DMAX

5. Set KP

9. Choose TOPSwitch-GX & fS Using AN-29

10. Set ILIMIT Reduction Factor KI Calculate ILIMIT (min) & ILIMIT (max)

N

Y

8. Calculate Primary RMS Current IRMS

To Step 12

Step 1-2Determine System Level Requirements

and Choose Feedback Circuit

11. IP ILIMIT (min)

Step 3-11Choose The Smallest TOPSwitch-GX

For The Required Power

PI-3039-080502

7. Calculate Primary Peak Current IP

From Step 23

AN-32

3C7/04

Figure 2B. TOPSwitch-GX Design Flow Chart. Step 12 to 28.

13. Choose Core & Bobbin Determine A

e, L

e, AL, BW

14. Set NS, L

15. Calculate NP, NB

Y

22. NS, L Iterated

17. Calculate BM

To Step 28

Step 12-28 Design the Smallest Transformer

to work with the TOPSwitch-GX Chosen

24. Calculate ISP

N

12. Determine LP

N

Y

Y

Y

N

N

Y

18. BM 3000

19. Calculate Lg, CMA

20. Lg 0.10 mm

16. Calculate OD, DIA, AWG

N

23. BP 4200

From Step 11

To Step 10

PI-3040-091802

21. 200 CMA 500

25. Calculate ISRMS

26. Calculate ODS, DIAS, AWGS

To Step 29

28. Calculate PIVS, PIVB

27. Calculate IRIPPLE

AN-32

4 C7/04

Figure 2C. TOPSwitch-GX Design Flow Chart. Step 29 to 37.

Step 29-37Select Other Components

From Step 28

29. Select Clamp Zener & Blocking Diode

31. Select Output Capacitor

32. Select Output Post Filter L, C

33. Select Bias Rectifier

34. Select Bias Capacitor

35. Select CONTROL Pin Capacitor& Series Resistor

36. Select Feedback Circuit CompenentsAccording to Reference Feedback Circuits

in Figures 3, 4, 5 and 6

37. Select Bridge Rectifier

Design Complete

30. Select Output Rectifier

PI-2584-091402

The overriding objective of this procedure is design for costeffectiveness. Using smaller components usually leads to aless expensive power supply. However, for applications withstringent size or weight limitations, the designer may need to

strike a compromise between cost and specific designrequirements in order to achieve the optimum cost effectivenessfor the end product.

AN-32

5C7/04

Power supply efficiency, : 0.8 if no better reference dataavailable. (Refer to AN-29)

Loss allocation factor, Z: If Z = 1, all losses are on thesecondary side. If Z = 0, all losses are on the primary side.Set Z = 0.5 if no better reference data is available.

Step 2. Choose feedback circuit and bias voltage VB basedon output requirements

Feedback VB Circuit Load* Line TotalCircuit (V) Tolerance Reg. Reg. Reg.Pri./Basic 5.8 10% 5% 1.5% 16.5%

Pri./Enhan. 27.8 5% 2.5% 1.5% 9%

Opto/Zener 12 5% 1% 0.5% 6.5%

Opto/TL431 12 1% 0.2% 0.2% 1.4%*Over 10% to 100% Load Range.Table 2.

Use primary feedback for lowest cost (for low powerapplications only).

Use Opto/Zener for low cost, good output accuracy. Use Opto/TL431 for best output accuracy. Set bias voltage VB according to Table 2. Choose optocoupler from Table 3.

Step-by-Step Design ProcedureThis design procedure uses the PI Expert design software (availablefrom Power Integrations), which contains all the importantequations required for a TOPSwitch-GX flyback power supplydesign, and automates most calculations. Designers are, therefore,relieved from the tedious calculations involved in the complicatedand highly iterative design process. Look-up tables and empiricaldesign guidelines are provided in this procedure where appropriateto facilitate the design task.

Step 1. Determine system requirements: VACMAX, VACMIN,fL, VO, PO, , Z

Minimum AC input voltage, VACMIN: in volts. Maximum AC input voltage, VACMAX: in volts. Recommended AC input ranges:

Input (VAC) VACMIN (VAC) VACMAX (VAC)

Universal 85 265

230 or 115 with doubler 195 265

Table 1.

Line frequency, fL: 50 Hz or 60 Hz. Output voltage, VO: in Volts. Output power: PO: in Watts.

Figure 3. Primary/Basic Feedback Circuit.

PI-3331-112202

D

S

C

TOPSwitch-GX

CONTROLL

+

-

FX

VAC

CIN

VO

15

Feedback Circuit

+

CIRCUIT PERFORMANCECircuit Tolerance 10% Load Regulation 5% Line Regulation 1.5%

AN-32

6 C7/04

Figure 4. Primary/Enhanced Feedback Circuit.

Figure 5. Opto/Zener Feedback Circuit.

PI-3330-091102

D

S

C

TOPSwitch-GX

CONTROLL

+

-

FX

VAC

CIN

VO

15

Feedback Circuit

1N5251D22 V1%

100 nF50 V

+

CIRCUIT PERFORMANCECircuit Tolerance 5% Load Regulation 2.5% Line Regulation 1.5%

PI-3328-112202

D

S

C

TOPSwitch-GX

CONTROLL

+

-

FX

VAC

CIN

Zener, 2%

LTV817A

470

VO

47

Feedback Circuit

+

CIRCUIT PERFORMANCECircuit Tolerance 5% Load Regulation 1% Line Regulation 0.5%

470 is good for Zeners with IZT = 5 mA. Lower values are needed for Zeners with higher IZT. (E.g. 150 for IZT = 20 mA).47 is suitable for VO up to 7.5V. For VO > 7.5V, a higher value may be required for optimum transient response.

AN-32

7C7/04

Figure 6. Opto/TL431 Feedback Circuit.

P/N CTR(%) BVCEO Manufacturer4 Pin DIPPC123Y6 80-160 70 V SharpPC817X1 80-160 70 V SharpSFH615A-2 63-125 70 V Vishay, IsocomSFH617A-2 63-125 70 V Vishay, IsocomSFH618A-2 63-125 55 V Vishay, IsocomISP817A 80-160 35 V Vishay, IsocomLTV817A 80-160 35 V LiteonLTV816A 80-160 80 V LiteonLTV123A 80-160 70 V LiteonK1010A 60-160 60 V Cosmo6 Pin DIPLTV702FB 63-125 70 V LiteonLTV703FB 63-125 70 V LiteonLTV713FA 80-160 35 V LiteonK2010 60-160 60 V CosmoPC702V2NSZX 63-125 70 V SharpPC703V2NSZX 63-125 70 V SharpPC713V1NSZX 80-160 35 V SharpPC714V1NSZX 80-160 35 V SharpMOC8102 73-117 30 V Vishay, IsocomMOC8103 108-173 30 V Vishay, IsocomMOC8105 63-133 30 V Vishay, IsocomCNY17F-2 63-125 70 V Vishay, Isocom,

Liteon

Table 3. Optocoupler

Step 3. Determine minimum and maximum DC inputvoltages VMIN, VMAX and input storage capacitance CIN basedon AC input voltage and PO (Figure 7)

Choose input storage capacitor, CIN per Table 4.

Input (VAC) CIN (F/Watt of PO) VMIN (V)

Universal 2 ~ 3 90

230 or 115 with doubler 1 240

Table 4

Set bridge rectifier conduction time, tC = 3 ms. Derive minimum DC input voltage VMIN

where units are volts, watts, Hz, seconds and farads

Calculate maximum DC input voltage VMAX:

V VP f t

CMIN ACMINO

LC

IN

=

( )2

2 122

PI-3329-112202

D

S

C

TOPSwitch-GX

CONTROLL

+

-

FX

VAC

CIN

TL431

UTV817A

VO

470 (VO = 12 V)

1 k

3.3 k 100 nF

10 k

R = VO - 2.5 2.5

X10 k

Feedback Circuit

+

100 (VO = 5 V)CIRCUIT PERFORMANCECircuit Tolerance 1% Load Regulation 0.2% Line Regulation 0.2%

V VMAX ACMAX= 2

AN-32

8 C7/04

Step 4. Determine reflected output voltage VOR and clampZener voltage VCLO (Figure 8)

Set reflected output voltage, VOR = 100 V for multipleoutput, 120 V for single output. These values optimizecross-regulation and efficiency. To obtain the maximumoutput power from a given TOPSwitch-GX device, setVOR = 135 V.

RCD (Resistor/Capacitor/Diode) clamp may be used with

TOPSwitch-GX when and only when current limit is setexternally with current limit reduction as a function of linevoltage. Compared to Zener clamps, designs using RCDclamps usually have lower efficiency at light load. Inaddition, great care must be taken in RCD clamp design.Because of its inherent variation in clamp voltage acrossload range, if not designed properly, an RCD clamp mayfail to protect TOPSwitch-GX, especially under startup oroutput overload conditions.

Figure 7. Input Voltage Waveform.

Figure 8. Reflected Voltage VOR and Clamp Zener Voltage VCLO.

tC

PO = Output Power

fL = Line Frequency (50 or 60 Hz)

tC = Conduction Angle Use 3 ms if unknown

= Efficiency

VV

ACMIN

MIN

2

PI-2585-012500

V+

Universal/230 VAC Input Use VOR = 120 V (100 V) and 180 V (150 V) Zener Clamp

For Single (Multiple) OutputPI-3336-091402

BVDSS

VOR = 120 V (100 V)

Margin = 53 V (95 V)Blocking Diode Forward Recovery = 20 V

700 V

495 V (475 V)

375 V

0 V0 V

VCLO = 1.5 x VOR

= 180 V (150 V)

VCLM = 1.4 x VCLO = 252 V (210 V)

VCLM VCLO

VMAX

555 V (525 V)627 V (585 V)647 V (605 V)

AN-32

9C7/04

Step 5. Set current waveform parameter KP for desiredmode of operation and current waveform: KP KRP for KP 1.0 and KP KDP for KP 1.0 (Figures 9 and 10)

For KP 1.0, KP KRP, continuous mode (see Figure 9)

where IR is primary ripple current and IP

is primary peak current. For KP 1.0, KP KDP, discontinuous mode (see Figure 10)

For continuous mode design, set KP = 0.4 for universal input

0.6 for 230 VAC or 115 VAC with doubler. For discontinuous mode design, set KP = 1.0. KP must be kept within the range specified in Table 5.Figure 9. Continuous Mode Current Waveform, KP 1.

IR

KP KRP =IR

IP

(a) Continuous, KP < 1

(b) Borderline Continuous/Discontinuous, KP = 1

Primary

Primary

IR

IP

IP

PI-2587-011400

KDP =KP (1-D) x Tt

(b) Boarderline Discontinuous/Continuous, KP = 1

(a) Discontinuous, KP > 1

Secondary

Primary

Primary

Secondary

PI-2578-011800

D x T

D x T

t

(1-D) x T

(1-D) x T = t

T = 1/fS

T = 1/fS

Figure 10. Discontinuous Mode Current Waveform, KP 1.

K K IIP RP

R

P

=

K K V DV V DP DP

OR MAX

MIN DS MAX

=

( )( )

1

AN-32

10 C7/04

Step 9. Choose TOPSwitch-GX

based on AC input voltage,VO, PO and using AN-29 selection curves

Choose the smallest TOPSwitch-GX using TOPSwitch-GXSelection Curves in AN-29.

Identify appropriate selection curves according to ACinput voltage and output voltage, VO.

Continuous mode: Use selection curves as is. Discontinuous mode: Use selection curves with the output

power derated by 33%. This effectively makes a 10 Wdiscontinuous design equivalent to a 15 W continuousdesign in TOPSwitch-GX selection.

Switching Frequency fS: For DIP and SMP packages, setfS = 132 kHz. For TO-220 package, choose between66 kHz and 132 kHz.

Step 10. Set ILIMIT reduction factor KI for External ILIMIT

where 0.3 KI 1.0

KI is set by the value of the resistor connected between Mpin and SOURCE pin (Refer to TOPSwitch-GX data sheet).

For applications demanding very high efficiency, aTOPSwitch-GX bigger than necessary may be used bylowering ILIMIT externally to take advantage of the lowerRDS(ON).

If no special requirement, set KI = 1.0. Calculate ILIMIT(min) and ILIMIT(max)

Step 11. Validate TOPSwitch-GX selection by checking IPagainst ILIMIT(min)

For KI = 1.0, check IP 0.96 x ILIMIT(min). For KI < 1.0, check IP 0.94 x ILIMIT(min). Choose larger TOPSwitch-GX if necessary.

Step 12. Calculate primary inductance LP

Continuous mode

where units are H, watts, amps and Hz

Discontinuous mode.

where units are H, watts, amps and Hz

KPContinuous Discontinuous

Mode Mode

Universal 0.4~1.0 1.0

230 0.6~1.0 1.0

Table 5

Step 6. Determine DMAX based on VMIN and VOR

Continuous mode

Discontinuous mode

Set TOPSwitch-GX Drain to Source voltage, VDS = 10 V.

Step 7. Calculate primary peak current IP

Continuous mode (KP 1.0)

Discontinuous mode (KP 1.0)

Input average current

Step 8. Calculate primary RMS current IRMS

Continuous mode

Discontinuous mode

Input (VAC)

I default I KLIMIT LIMIT I(min) (min)= I default I KLIMIT LIMIT I(max) (max)=

I IK DP

AVG

PMAX

=

1 2

I IDP

AVG

MAX

=2

I PVAVG

O

MIN

=

K external Idefault II

LIMIT

LIMIT

=

D VV V VMAX

OR

MIN DS OR

= +( )

D VK V V VMAX

OR

P MIN DS OR

= +

( )

I D IRMS MAX P= 2

3

I I D K KRMS P MAX P P= +

2

31

L P

I K K fZ

PO

P PP

S

=

+10

12

16

2

(min)( )

L P

I fZ

PO

P S

=

+1012

16

2

(min)( )

AN-32

11C7/04

Step 14. Set value for number of primary layers L andnumber of secondary turns NS (may need iteration)

Starting with L = 2 (Keep 1.0 L 2.0 throughoutiteration).

Starting with NS = 0.6 turn/volt. Both L and NS may need iteration.

Step 15. Calculate number of primary turns NP and numberof bias turns NB

Diode forward voltages: 0.7 V for ultra-fast P/N diode and0.5 V for Schottky diode.

Set output rectifier forward voltage, VD. Set bias rectifier forward voltage, VDB. Calculate number of primary turns.

Calculate number of bias turns NB.

Step 16. Determine primary winding wire parameters OD,DIA, AWG

Primary wire outside diameter in mm.

where L is number of primary layers,BW is bobbin width in mm,M is safety margin in mm.

Determine primary wire bare conductor diameter DIA andprimary wire gauge AWG.

Step 17 to Step 22. Check BM, CMA and Lg. Iterate ifnecessary by changing L, NS or core/bobbin until withinspecified range

Set safety margin, M. Use 3 mm (118 mils) for marginwound and zero for triple insulated secondary.

Maximum flux density: 3000 BM 2000, in gauss or0.3 BM 0.2, in tesla.

where units are gauss, amps, H and cm2

Z is loss allocation factor and is efficiency from Step 1.

Step 13. Choose core and bobbin based on fS and PO usingTable 6 and determine A

e, L

e, AL and BW from core and

bobbin catalog

Core effective cross-sectional area, Ae: in cm2.

Core effective path length, Le: in cm.

Core ungapped effective inductance, AL: in nH/turn2. Bobbin width, BW: in mm. Choose core and bobbin based on fS, PO and construction

type.

Triple TripleInsulated Insulated

Wire WireEF12.6 EI22 EF12.6 EI22EE13 EE19 EE13 EE19EF16 EI22/19/6 EF16 E122/19/6EE16 EEL16 EE16 EEL16EE19 EF20EI22 EI25

EI22/19/6 EEL19EF20 EI28 EE19 EF20

EEL22 EI22 EI25EF25 EI22/19/6 EEL19

EF20EF25 EI30 E128

EPC30EEL25

EI28 E30/15/7 EF25 EEL22EI30 EER28 EF25

E30/15/7 ETD29 EI30EER28 EI35 EPC30

EI33/29/13-Z

EER28LETD29 EF32 EI28 EEL25EI35 ETD34 E30/15/7EF32 EER28

ETD34 EI40 EI30 ETD29E36/18/11 E36/18/11 E30/15/7 EI35

EI40 EER35 EER28 EI33/29/ETD29 13-Z

EER28LEF32

ETD39 ETD39 EI35 ETD34EER40 EER40 EF32 EI40

E42/21/15 ETD34 E36/18/11EER35

E42/21/15 E42/21/20 E36/18/11 ETD39E42/21/20 E55/28/21 EI40 EER40E55/28/21 ETD39 E42/21/15

EER40 E42/21/20E42/21/15 E55/28/21E42/21/20E55/28/21

Table 6. Transformer Core.

66 kHz 132 kHzOutputPower

0-10 W

10 W-20 W

20 W-30 W

30 W-50 W

50 W-70 W

70 W-100 W

100 W-150 W

>150W

MarginWound

MarginWound

N N VV VP S

OR

O D

= +

N N V VV VB S

B DB

O D

= ++

OD L BW MNP

= ( )2

B I LN AM

P P

P e

=

100

AN-32

12 C7/04

Gap length in mm: Lg 0.1

where Lg in mm, Ae in cm2, AL in nH/turn2 and LP in H

Primary winding current capacity in circular mils per amp:500 CMA 200

where DIA is the bare conductor diameter in mm

Iterate by changing L, NS, core/bobbin according to Table 7.

BM Lg CMA

L - -

NS

Table 7.

Step 23. Check BP 4200 . If necessary, reduce currentlimit by lowering ILIMIT reduction factor KI

Check BP 4200 gauss (0.42 tesla) to avoid transformersaturation at startup and output over load.

Decrease KI, if necessary, until BP 4200.

Step 24. Calculate secondary peak current ISP

Step 25. Calculate secondary RMS current ISRMS

Continuous mode

Discontinuous mode

Step 26. Determine secondary winding wire parametersODS, DIAS, AWGS

Secondary wire outside diameter in mm

Secondary wire bare conductor diameter in mm

where CMAS is secondary winding current capacityin circular mils per amp. Minimum wire diameter iscalculated by using a CMAS of 200.

Determine secondary winding wire gauge AWGS based onDIAS. If the bare conductor diameter of the wire is largerthan that of the 27 AWG for 132 kHz or 25 AWG for66 kHz, a parallel winding using multiple strands of thinnerwire should be used to minimize skin effect.

Step 27. Determine output capacitor ripple current IRIPPLE

Output capacitor ripple current

where IO is the output DC current

Step 28. Determine maximum peak inverse voltages PIVS,PIVB for secondary and bias windings

Secondary winding maximum peak inverse voltage.

Bias winding maximum peak inverse voltage.

Step 29. Select clamp Zener and blocking diode per Table 8for primary clamping based on VOR and the type of output

Table 8.

coresize

Blocking Clamp Diode ZenerBYV26CMUR160 P6KE150UF4005BYV26CMUR160 P6KE180UF4005

PS Output VOR

Multiple Output 100 V

Single Output 120 V

L A NL Ag e

P

P L

=

40

100012

CMADIA

I RMS=

1 274 1000

25 4

22.

.

B II

BP LIMITP

M= (max)

I I NNSP P

P

S

=

I I D K KSRMS SP MAX P P= ( ) +

1

31

2

I I DKSRMS SP

MAX

P

=

13

OD BW MNS S

= ( )2

DIA CMA IS S SRMS=

41 27

25 41000

.

.

I I IRIPPLE SRMS O= 2 2

PIV V V NNS O MAX

S

P

= + ( )

PIV V V NNB B MAX

B

P

= + ( )

AN-32

13C7/04

Step 30. Select output rectifier per Table 9

VR 1.25 x PIVS; where PIVS is from Step 28 and VR is therated reverse voltage of the rectifier diode.

ID 3 x IO; where ID is the diode rated DC current andIO = PO / VO.

Rec. Diode VR(V) ID(A) Package ManufacturerSchottky1N5819 40 1 Axial General SemiSB140 40 1 Axial General SemiSB160 60 1 Axial General SemiMBR160 60 1 Axial IR11DQ06 60 1.1 Axial IR1N5822 40 3 Axial General SemiSB340 40 3 Axial General SemiMBR340 40 3 Axial IRSB360 60 3 Axial General SemiMBR360 60 3 Axial IRSB540 40 5 Axial General SemiSB560 60 5 Axial General SemiMBR745 45 7.5 TO-220 General Semi

IRMBR760 60 7.5 TO-220 General SemiMBR1045 45 10 TO-220 General Semi

IRMBR1060 60 10 TO-220 General SemiMBR10100 100 10 TO-220 General SemiMBR1645 45 16 TO-220 General Semi

IRMBR1660 60 16 TO-220 General SemiMBR2045CT 45 20(2x10) TO-220 General Semi

IRMBR2060CT 60 20(2x10) TO-220 General SemiMBR20100 100 20(2x10) TO-220 General Semi

IRUFRUF4002 100 1 Axial General SemiUF4003 200 1 Axial General SemiMUR120 200 1 Axial General SemiEGP20D 200 2 Axial General SemiBYV27-200 200 2 Axial General Semi

PhilipsUF5401 100 3 Axial General SemiUF5402 200 3 Axial General SemiEGP30D 200 3 Axial General SemiBYV28-200 200 3.5 Axial General Semi

PhilipsMUR420 200 4 TO-220 General SemiBYW29-200 200 8 TO-220 General Semi

PhilipsBYV32-200 200 18 TO-220 General Semi

PhilipsTable 9.

Step 31. Select output capacitor

Ripple current specification at 105 C, 100 kHz: Must beequal to or larger than IRIPPLE, where IRIPPLE is from Step 27.

ESR specification: Use low ESR, electrolytic capacitor.Output switching ripple voltage is ISP x ESR , where ISP isfrom Step 24.

Examples:

Output Output Capacitor

5 V to 24 V, 1 A 330 F, 35 V, low ESR, electrolyticUnitedChemiconLXZ35VB331M10X16LLRubycon 35YXG330M10x16Panasonic EEUFC1V331

5 V to 24 V, 2 A 1000 F, 35 V, low ESR, electrolyticUnited ChemiconLXZ35VB102M12X25LLRubycon 35YXG1000M12.5x25Panasonic EEUFC1V102

Step 32. Select output post filter L, C

Inductor L: 2.2 H to 4.7 H. Use ferrite bead for lowcurrent (1A) output and standard off-the-shelf choke forhigher current output. Increase choke current rating or wiresize, if necessary, to avoid significant DC voltage drop.

Capacitor C:100 F to 330 F, 35 V, electrolyticExamples for 100 F, 35 V, electrolytic:United Chemicon KMG35VB101M6X11LLRubycon 35YXA100M6.3x11Panasonic ECA1VHG101

Step 33. Select bias rectifier from Table 10

VR 1.25 x PIVB; where PIVB is from Step 28 and VR is therated reverse voltage of the rectifier diode.

Rectifier VR (V) ManufacturerBAV21 200 PhilipsUF4003 200 General Semi1N4148 75 Motorola

Step 34. Select bias capacitor

Use 0.1 F, 50 V, ceramic.

Step 35. Select CONTROL pin capacitor and series resistor

CONTROL pin capacitor: 47 F, 10 V, low cost electrolytic(Do not use low ESR capacitor).

Table 10.

AN-32

14 C7/04

Series resistor: 6.8 , 1/4 W (Not needed if KP 1, i.e.discontinuous mode).

Step 36. Select feedback circuit components according toapplicable reference feedback circuits shown in Figures 3,4, 5 and 6

Applicable reference circuit: Identified in Step 2.

Step 37. Select input bridge rectifier

VR 1.25 x x VACMAX; where VACMAX is from Step 1. ID 2 x IAVE; where ID is the bridge rectifier rated current

and IAVE is average input current.

Note: ;

where VMIN is from Step 3 and from Step 1.

2

I PVAVE

OUT

MIN

=

AN-32

15C7/04

Customization of secondary designs for each outputThe turns for each secondary winding are calculated based onthe respective output voltage VO(n):

Output rectifier maximum inverse voltage is

With output RMS current ISRMS(n), secondary number of turnsNS(n) and output rectifier maximum inverse voltage PIVS(n)known, the secondary side design for each output can now becarried out exactly the same way as for the single output design.

Secondary winding wire sizeThe TOPSwitch-GX design spreadsheet assumes a CMA of 200when calculating secondary winding wire diameters. This givesthe minimum wire sizes required for the RMS currents of eachoutput using seperate windings. Designers may wish to uselarger size wire for better thermal performance. Otherconsiderations such as skin effect and bobbin coverage maysuggest the use of a smaller wire by using multiple strandswound in parallel. In addition, practical considerations intransformer manufacturing may also dictate the wire size.

I n I n IISRMS OSRMS

O

( ) ( )=

Appendix AMultiple Output Flyback PowerSupply DesignThe only difference between a multiple output flyback powersupply and a single output flyback power supply of the sametotal output power is in the secondary side design. Instead ofdelivering all power to one output as in the single output case,a multiple output flyback distributes its output power amongseveral outputs. Therefore, the design procedure for the primaryside stays the same, while that for the secondary side demandsfurther considerations.

Design with lumped output powerOne simple way of doing multiple output flyback design isdescribed in detail in AN-22, Designing Multiple OutputFlyback Power Supplies with TOPSwitch. The design methodstarts with a single output equivalent by lumping output powerof all outputs to one main output. Secondary peak current ISP andRMS current ISRMS are derived. Output average current IOcorresponding to the lumped power is also calculated.

Assumption for simplificationThe current waveforms in the individual output windings aredetermined by the impedance in each circuit, which is a functionof leakage inductance, rectifier characteristics, capacitor valueand most importantly, output load. Although this currentwaveform may not be exactly the same from output to output,it is reasonable to assume that, to the first order, all outputcurrents have the same shape as for the single output equivalentof lumped power.

Output RMS current vs. average currentThe output average current is always equal to the DC loadcurrent, while the RMS value is determined by current waveshape. Since the current wave shapes are assumed to be thesame for all outputs, their ratio of RMS to average currents mustalso be identical. Therefore, with the output average currentknown, the RMS current for each output winding can becalculated as

where ISRMS(n) and IO(n) are the secondary RMS current andoutput average current of the nth output and ISRMS and IO are thesecondary RMS current and output average current for thelumped single output equivalent design.

N n N V n V nV VS S

O D

D

( ) ( ) ( )= ++

PIV n V N nN

V nS MAX SP

O( )( ) ( )= +

AN-32

16 C7/04

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POWER INTEGRATIONS' PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMSWITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. Life support devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, whenproperly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety or effectiveness.

The PI logo, TOPSwitch, TinySwitch, LinkSwitch and EcoSmart are registered trademarks of Power Integrations.PI Expert and DPA-Switch are trademarks of Power Integrations. Copyright 2004, Power Integrations

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Notes

1) Final release.1) Minor revision.1) Minor revision: Corrected VMAX equation.

Date

9/0212/027/04

Revision

AB

C