formalizing the arts mpsoc model in uppaal jan madsen embedded systems engineering group informatics...

Formalizing the ARTS MPSoC Model in UPPAAL

Jan Madsen

Embedded Systems Engineering Group

Informatics and Mathematical ModelingTechnical University of Denmark

ARTIST2

ARTIST2 Clustermeeting, Linkoping, May 14, 2007 Jan Madsen [2]

System Modelling Infrastructure

MPARM

DES

ARTS UPPAAL

Holistic

MPA SymTA/S

Simulation-based Formal-based

Execution Platforms Execution Platforms

Test & Verification

DTU

UoB

Linkoping

TUBETHZ

Linkoping

AAU


Outline

The ARTS framework Formalizing ARTS MOVES Example

1 2 os

3

4

a b c

L1 L2

L3

R1 R2 R3

Model of system implementation


ARTS objectives

System-level modeling framework Bridging,

Application RTOS Execution platform

Processing elements NoC

Supporting System-level analysis Early design space exploration

1 2 os

3

4

a b c

L1 L2

L3

R1 R2 R3


Cross-layer optimization


ARTS framework

1 2 os

3

4

a b c

L1 L2

L3

R1 R2 R3


Intermediate adapter1


Intermediate adapterN

SoC allocator

SoC scheduler

SoCresource buffer

OCP IO port1

OCP IO port2

OCP IO portN

. . .

SoC communication layer model

IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

SoC comm. interface

PE1 PE2 PEN

ARTS model in SystemC





SoC allocator

SoC scheduler

SoCresource buffer

OCP IO port1

OCP IO port2

OCP IO portN

. . .


IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

SoC comm. interface

PE1 PE2 PEN




SoC allocator

SoC scheduler

SoCresource usage

buffer

IO port1 IO port2 IO portN

SoC communication interface (i.e. OCP 2.0)

. . .


IO a

dapt

or m

odel

IO a

dapt

or m

odel

IO a

dapt

or m

odel

ARTS Framework

ARTS Simulation framework based on SystemC

ARTS PE module: Application OS IO ports (OCP 2.0 interface) IO device drivers

ARTS Communication module: Network topology and protocol Network adapters IO ports (OCP 2.0 interface)

Applications of ARTS: MPSoC (NoC exploration) Wireless sensor networks Automotive systems (TT vs. ET) Dynamic reconfiguration

tIO

Master

OCP IO device

Slave

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1

tn

. . .

App

licat

ion

RT

OS

SoC communication interface (OCP)


Formalizing ARTS


Timed Automata for a task


MOVES: Hiding UPPAAL!

a b c


1 2 os

3

4

L1 L2

L3

R1 R2 R3

1

34

2

Application model

a b c

System platform

System-leveldesign tasks

os os


a b c


MOVES

1 2 os

3

4

L1 L2

L3

R1 R2 R3

Model checking

Required specification

E<>missedDeadline E<>totalCostUsed(Memory)>=23

E<>totalCostUsed(Energy)>=15


Example: MPSoC specification


Specifying the application

Task t1 = new Task(1, 3, 10, 10, 0, 1);Task t2 = new Task(2, 2, 8, 10, 0, 2);Task t3 = new Task(2, 2, 10, 10, 0, 3);Task t4 = new Task(1, 1, 5, 10, 0, 4);


Execution platform

Processor p1 = new Processor(1, Processor.RM);Processor p2 = new Processor(1, Processor.RM);Processor p3 = new Processor(1, Processor.RM);Processor pm = new Processor(1, Processor.RM);Resource r1 = new Resource();


Mapping application onto platform

Task[][] tasks = {{t1},{t2,t3},{t4},{tm1,tm2}};

Task tm1 = new Task(3, 3, 10, 5);Task tm2 = new Task(1, 1, 10, 6);

apps.useResource(tm1,r1);apps.useResource(tm2,r1);

apps.addDep(t1,tm1);apps.addDep(tm1,t2);apps.addDep(t3,tm2);apps.addDep(tm2,t4);

3 1τm1τm2


e(τ1)= [3]

Traces

e(τ1)= [1:3]


Handling realistic applications?

t0

t1t10 t7t13t16

t9t12t15t18 t2

t3

t4

t5

t6

t8

t20t21t22t23t24

t25 t26 t27

t28t29t30t31t32

t33

t38t39t40

t41 t42 t43

t44t45t46t47t48

t49 t50 t51 t52

t19

t17

t37 t36

t34 t35 t11

GSM Encoder

t0

t30 t27 t24 t21 t8t23

t11t22

t33

t25t28t19

t14

t1

t7

t6

t2

t9

t10

t3

t5

t13

t12

t17 t4

t16

t15

t20

t18t29

t26

t32

t31

t30

GSM DecoderJPEG Encoder

t1

t2

t3

t0

t4

t0

t1

t2

t3

t4

t5

JPEG Decoder

t0

t2 t1

t4 t3

t6 t5

t7

t8 t9

t10 t11

t12 t13

t14 t15

MP3 Decoder

[Application from Marcus Schmitz, TU Linkoping]

Smart phone:


Smart phone

Tasks: 114 Deadlines: [0.02: 0.5] sec Execution: [52 : 266.687]

cycles Hyperperiod: 12.500.000

cycles ~2.500 task executions Platform:

6 processors, 25 MHz 1 bus

Verified in 2.5 hours! Using a granularity of 400 cycles

t0

t1t10 t7t13t16

t9t12t15t18 t2

t3

t4

t5

t6

t8

t20t21t22t23t24

t25 t26 t27

t28t29t30t31t32

t33

t38t39t40

t41 t42 t43

t44t45t46t47t48

t49 t50 t51 t52

t19

t17

t37 t36

t34 t35 t11

GSM Encoder

t0

t30 t27 t24 t21 t8t23

t11t22

t33

t25t28t19

t14

t1

t7

t6

t2

t9

t10

t3

t5

t13

t12

t17 t4

t16

t15

t20

t18t29

t26

t32

t31

t30

GSM DecoderJPEG Encoder

t1

t2

t3

t0

t4

t0

t1

t2

t3

t4

t5

JPEG Decoder

t0

t2 t1

t4 t3

t6 t5

t7

t8 t9

t10 t11

t12 t13

t14 t15

MP3 Decoder


Acknowledgements

MOVES Michael R. Hansen Aske Brekling Jens Ellebæk Kristian S. KnudsenARTS Shankar Mahadevan Kehuai Wu Kashif Virk Michael Storgaard Mercury Gonzalez

formalizing the arts mpsoc model in uppaal jan madsen embedded systems engineering group informatics...

Documents

artist2 clustermeeting

formalizing arts slide

task slide

arts mpsoc model

systemc slide

mpsoc specification

interface applications

new processor1