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TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Three Independent Step-Down DC/DCControllers and One 12-V Boost DC/DCConverter
4.5 V – 28 V Input Voltage Range
Step-Down Controller Output VoltagesAdjustable Down to 1.2 V
Synchronous-Buck Operation for HighEfficiency
PWM Mode Control
Auto PWM/SKIP Mode for HighEfficiency Under All Load Conditions
High Speed Error Amplifier
Separate Standby Control and Over Current Protection for Each Channel
Over Voltage and Under Voltage Protection
Programmable Short Circuit Protection
Power Good With Programmable DelayTime
5 V and 3.3 V Linear Regulators
description
The TPS5140 is a dc/dc controller that incorporates three synchronous-buck controllers and onenonsynchronous 12-V boost converter on one chip to power the voltage rails needed by notebook peripheralcomponents. On-chip high-side and low-side synchronous rectifier drivers are integrated to drive less expensiveN-channel power MOSFETs. The nonsynchronous boost converter includes the N channel power MOSFET andsupports 120 mA for the PCMCIA power supply. The outputs are controlled independently and two of thesynchronous-buck controllers operate 180 degrees out of phase, with the third lowering the input current rippleand allowing a smaller input capacitance to reduce power supply cost. For higher efficiency under all loadconditions, the TPS5140 automatically adjusts each channel from the PWM mode to the skip modeindependently. The skip mode enables a lower operating frequency and shortens the pulse width to the low sideMOSFETs, thereby increasing the efficiency under light load conditions. To further extend battery life, theTPS5140 features dead-time control and very low quiescent current. Resistorless current protection and thefixed high-side driver voltage simplify the system design and reduce the external parts count.
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
17 18
5712345678910111213141516
19
LH2NCVCCNCVREF3.3VREF5REG5V_INNCGND_UPLL_UPIN_12VOUT_12VNCVCC_SENSE3TRIP3NC
48474645444342414039383736353433
20
FB1SOFTSTART1
NCINV2FB2
SOFTSTART2PWM_SEL
CtGNDREF
STBY_VREF3.3STBY_VREF5
STBY1STBY2
STBY12VSTBY3
21 22 23 24
LL2
V
_S
EN
SE
12
63 62 61 60 5964 58
NC
LH1
OU
T1_
uLL
1N
CO
UT
1_d
OU
TG
ND
1IN
V3
NC
LH3
OU
T3_
u
PG
–DE
LAY
NC
EX
T_P
GO
FT
STA
RT
_12V
PH
AS
E_1
2VS
OF
TS
TAR
T3
FB
3
56 55 54
25 26 27 28 29
53 52
SC
P
TR
IP2
OU
TG
ND
2
51 50 49
30 31 32
LL3
OU
T3_
dO
UT
GN
D3
OU
T2_
d
TR
IP1
OU
T2_
u
INV
1N
CP
GO
UT
CC
PAG PACKAGE(TOP VIEW)
PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
typical design schematic
INV2
FB2
SOFTSTART2
CT
GND
REF
SCP
SOFTSTART1
FB1
INV
1LH
1O
UT
1_u
LL1
OU
T1_
dO
UT
GN
D1
TR
IP1
VC
C_S
EN
SE
12T
RIP
2O
UT
GN
D2
OU
T2_
d
LL2
OU
T2_
u
LH2
VCC
VREF5
OUT_12V
GND_UP
LL_UP
IN_12V
VCC_SENSE3
TRIP3
OU
TG
ND
3
SO
FT
STA
RT
3F
B3
INV
3
LH3
OU
T3_
u
LL3
OU
T3_
d
V
GND
U1TPS5140IPAG
C1
C2
C3
C4
C5
C6
C8C9
C10
C11
C12
C13
C14
C15
C16
C17
C18R1
R2 R3
R4
R5 R6
R7
R8
D1
D2
D4
D3
L1
L2
L3
L4
Q1 Q2
Q3
Q4
Q5
Q6
VREF3.3
C19
R9
R10R11
R12
C20
C21
O1
VO2
VO3
VO4
VO5
VI
R14 C23
R1
C22
R18
C26C27
R17
C25
R16
R15 C24
AVAILABLE OPTIONS
TAPACKAGE
TAPAG EVM
–20°C to 85°C TQFP64 (PAG)
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram—whole block
SBRC Ch1 SBRC Ch2 SBRC Ch3
PhaseInverter
Oscillator
Timer
12-V BoostConverter
Ch4
5-V Switch
5-V SeriesRegulator
50 mA
3.3-V SeriesRegulator
Vref 1.185 V
OUT_12 V
REG5V_IN
VREF3.3VREF5
VCC
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram—SMPS block
+
Skip Comparator
PWM Comparator
Error Amplifier
Phase Inverter
Oscillator
+
MOSFETDriver
CurrentLimit
Timer
OVP (1.185 V + 12 %)
OVP (1.185 V – 18 %)
PG Comparator
Softstart
Standby
OUT_u
OUT_d
TRIP
INV1
Ct
SCP
SOFTSTART
STBY
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram—boost 12-V block
_
++
_+
+
Softstart 12 V
OSC
Error AmplifierPWM Comparator
CurrentLimit
MOSDriver
Timer
OVPUVP
REG5V_INOVP
_
++
VREF5PMOS
PMOS
NMOS
OUT_12 V
LL_UP
GND_UP
IN_12V
OUT_12V
SFT_12V
SCP
REG5V_IN
STBY_12V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram—power good block
PG Comp.1PG Comp.2PG Comp.3
OR Logic
_
+ +
4.5 V
5-V SeriesRegulator
50 mA Max.
UVLO
3.3-V SeriesRegulator
Vref1.185 V
Timer
STBY_VREF5 STBY_VREF3.3
VREF3.3
VREF5
REG5V_IN
EXT_PG
PGOUT(open drain)
PG_DELAY
REF
VCC
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINALI/O DESCRIPTION
NAME NO.I/O DESCRIPTION
Ct 8 I/O External capacitor from Ct to GND used for adjusting the triangle oscillator.
EXT_PG 21 I External power good signal input
FB1 1 O Feedback output of CH1 error amplifier
FB2 5 O Feedback output of CH2 error amplifier
FB3 25 O Feedback output of CH3 error amplifier
GND 9 Control GND
GND_UP 40 Ground for 12-V boost converter
INV1 64 I Inverting input of CH1 error amplifier, skip comparator and OVP1/UVP1, PG comparator
INV2 4 I Inverting input of CH1 error amplifier, skip comparator and OVP2/UVP2, PG comparator
INV3 26 I Inverting input of CH1 error amplifier, skip comparator and OVP3/UVP3, PG comparator
IN_12V 38 I Input of PMOS switch for 12-V boost output. Connecting to cathode of the external Schottkydiode.
LH1 61 I/O Bootstrap capacitor connection for CH1 high side gate drive
LH2 48 I/O Bootstrap capacitor connection for CH2 high side gate drive
LH3 28 I/O Bootstrap capacitor connection for CH3 high side gate drive
LL1 59 I/O Bootstrap low for CH1 high side gate driving return and output current protection. Connect tothe junction of the high side and low side FETs for floating drive configuration.
LL2 50 I/O Bootstrap low for CH2 high side gate driving return and output current protection. Connect tothe junction of the high side and low side FETs for floating drive configuration.
LL3 30 I/O Bootstrap low for CH3 high side gate driving return and output current protection. Connect tothe junction of the high side and low side FETs for floating drive configuration.
LL_UP 39 I/O Open drain output of internal NMOS switch for 12-V boost converter. Connect between exter-nal inductor and the anode of the schottky diode.
NC 3,20,27,33,36,41,45,47
58,62,63
No connect
OUT1_d 57 O Gate drive output for CH1 low side gate drive
OUT2_d 51 O Gate drive output for CH2 low side gate drive
OUT3_d 31 O Gate drive output for CH3 low side gate drive
OUT1_u 60 O Gate drive output for CH1 high side switching FETs
OUT2_u 49 O Gate drive output for CH2 high side switching FETs
OUT3_u 29 O Gate drive output for CH3 high side switching FETs
OUT_12V 37 O Output of PMOS switch for 12-V boost output. Connect to the output capacitor for 12-V boostoutput.
OUTGND1 56 Ground for CH1 FETs drivers. It is connected to one of the current limiting comparator input.
OUTGND2 52 Ground for CH2 FETs drivers. It is connected to one of current limiting comparator input.
OUTGND3 32 Ground for CH3 FETs drivers. It is connected to the one of current limiting comparator input.
PGOUT 18 O Open drain output for power good signal
PG_DELAY 19 I/O Programmable delay for power good. Connect to the external capacitor for timer delay.
PHASE_12V 23 I Phase compensation for the12-V boost converter. Connect to an external capacitor.But normally it is not connected.
PWM_SEL 7 I PWM or auto PWM/SKIP modes selectL: PWM fixed H: auto PWM/SKIP
REF 10 O 1.185 V reference voltage output
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions(Continued)
TERMINALI/O DESCRIPTION
NAME NO.I/O DESCRIPTION
REG5V_IN 42 I External 5 V input
SCP 17 I/O Short circuit protection terminal. An external capacitor is connected between SCP and GND toset the SCP enable time up.
SOFTSTART1 2 I/O External capacitor from SOFTSTART1 to GND for CH1 soft starts control.
SOFTSTART2 6 I/O External capacitor from SOFTSTART2 to GND for CH2 soft starts control.
SOFTSTART3 24 I/O External capacitor from SOFTSTART3 to GND for CH3 soft starts control.
SOFTSTART_12V 22 I/O External capacitor from SOFTSTART_12V to GND for CH4 (12-V boost converter) soft startscontrol.
STBY1 13 I Stand by control for CH1
STBY2 14 I Stand by control for CH2
STBY3 16 I Stand by control for CH3
STBY12V 15 I Stand by control for 12-V boost converter
STBY_VREF3.3 11 I Stand by control for 3.3-V linear regulator
STBY_VREF5 12 I Stand by control for 5-V linear regulator
TRIP1 55 I External resistor connection for CH1 output current protection control
TRIP2 53 I External resistor connection for CH2 output current protection control
TRIP3 34 I External resistor connection for CH3 output current protection control
VCC 46 Supply voltage input
VCC_SENSE12 54 I Supply voltage input and input voltage terminal for CH1/2 output current sense
VCC_SENSE3 35 I Supply voltage input and input voltage terminal for CH3 output current sense
VREF3.3 44 O 3.3-V linear regulator output
VREF5 43 O 5-V linear regulator output
detailed description
REF (1.185 V)
The reference voltage is used for setting the output voltage and voltage protection. This reference voltage isdropped down from the 5-V regulator. The tolerance is 1.5 % over the entire temperature range.
CH1, 2, 3 (synchronous buck controller)
The TPS5140 includes three synchronous buck controllers. CH2 and CH3 (5 V and 2.5 V) are operated in phase,but CH1 (3.3 V) is operated 180° out of phase from CH2 and CH3, but at the same frequency. All channels haveseparate standby and softstart control.
12-V boost converter
OUT_12V is a 12-V boost converter output . It can isolate VI (5 V) and VO fully.
5-V regulator
An internal linear voltage regulator is used for the high-side driver bootstrap voltage and as the source of Vref.When the 5-V regulator is disconnected from the MOSFET drivers, it is used only for the source of Vref. Sincethe input voltage is from 4.5 V to 28 V, this feature offers a fixed bootstrap voltage to simplify the drive design.The 5-V regulator is also used for powering the low side driver. The 5-V regulator is active if STBY_VREF5 ishigh and has a tolerance of 4%.
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
3.3-V regulator
TPS5140 has a 3.3-V linear regulator. The output is made from the internal 5 V regulator or external 5 V fromREG5V_IN. The 3.3-V regulator has an output current limit. The maximum output current is 30 mA.
5-V switch
If the internal 5-V switch senses a 5-V input from the REG5V_IN terminal, the internal 5-V linear regulator willbe disconnected from the MOSFET drivers. The external 5 V will be used for both the low-side driver and thehigh-side bootstrap, thus increasing the efficiency.
auto PWM/SKIP
The PWM_SEL terminal selects either the auto PWM/SKIP or fixed PWM mode. If this terminal is lower than0.5 V, the outputs operate in the fixed PWM mode. If 2.5 V (minimum) is applied, the outputs operate in autoPWM/SKIP mode. In the auto PWM/SKIP mode, the operation changes from the PWM mode to the SKIP modeautomatically under light load conditions. Avoid using a MOSFET with very low rDS(on) if the auto SKIP functionis implemented.
error amp
All three synchronous buck channels have their own error amplifier to regulate the output. The error amplifieris used in the PWM mode for high output current conditions (> 0.2 A). Voltage mode control is implemented.
skip comparator
In skip mode, all three synchronous buck channels have their own hysteresis comparator to regulate the outputvoltages. The hysteresis voltage is set internally and typically at 8.5 mV. The delay from the comparator inputto the driver output is typically 1.2 µs.
low-side driver
The low-side driver is designed to drive low-rDS(on) n-channel MOSFETs. The maximum drive voltage is 5 V fromVREF5. Ch1, 2, and 3 MOSFET driver capability is 1.5 A, source and sink.
high-side driver
The high-side driver is designed to drive low-rDS(on) n-channel MOSFETs. CH1 and CH2 MOSFET drivers have1.2 A capability, source and sink. When configured as a floating driver, the bias voltage to the driver is developedfrom VREF5, limiting the maximum drive voltage between OUT_u and LL to 5 V. The maximum voltage that canbe applied between LHx and OUTGND is 33 V.
dead time
Dead time prevents shoot-through current from flowing through the main power MOSFETs during switchingtransitions by actively controlling the turnon time of the MOSFETs drivers.
current protection
Current protection is achieved by sensing the drain-to-source voltage drop of the low-side power MOSFETduring the low-side MOSFET’s on time at OUTGND and LL. An external resistor between VCC_ SENSE andTRIP terminal in series with the internal current source adjusts the current limit. When the voltage drop duringthe low-side MOSFET on-time is high enough, the current comparator triggers the current protection and theMOSFET drivers are turned off. After a programmable time delay, the SCP circuit latches off all MOSFETdrivers. The internal current source tolerance is ±10%. CH2 monitors both high-side and low-side MOSFETvoltage drops.
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
OVP
For over voltage protection, the TPS5140 monitors INV terminal voltage. When the INV voltage becomes higherthan 1.185 V (+12%), the OVP comparator output becomes high and the SCP timer starts to charge the SCPcapacitor. After a programmable time delay, the SCP circuit forces CH1, 2, 3 high-side MOSFET drivers to latchoff and the low-side MOSFET drivers to latch on.
UVP
For under voltage protection, the TPS5140 monitors INV terminal voltage. When the INV voltage becomes lowerthan 1.185 V (–18 %), the UVP comparator output becomes high and the SCP timer starts to charge the SCPcapacitor. Also, when the current comparator of CH1, 2, 3 triggers the OCP, the UVP comparator detects theunder voltage output and the SCP capacitor starts to charge. After the programmable time delay, the SCP circuitforces the CH1, 2, 3 MOSFET drivers to latch off.
SCP
When an OVP or UVP comparator output becomes high, the SCP circuit starts to charge the SCP capacitor.The charging source current value is different between OVP alert and UVP alert.
SCP source current (OVP) = SCP source current (UVP) × 5
The threshold voltage of SCP comparator is 1.185 V.
power good
The power good output reports the output fail condition. PG comparators monitor an under voltage or overvoltage of CH1, 2, 3, with a threshold of –7 % and 7 %. TPS5140 has an EXT_PG terminal, which can be usedfor the input of an external PG signal. Delay time is programmable by charging an external capacitor on thePG_DELAY terminal.
SOFTSTART1, 2, 3
Separate soft start terminals make it possible to customize the start-up time of each output. The voltage on thecharging softstart capacitor gradually raises, limiting the surge current and voltage. A soft start is initiated whenthe STBY terminals are switched.
STBY1, 2, 3, 12V
CH1, 2, 3 and 12V can be switched into standby mode separately by grounding the STBY terminal.
STBY_VREF3.3, 5V
STBY_VREF3.3 shuts down the 3.3-V regulator by grounding the STBY_VREF3.3 terminal. WhenSTBY_VREF5 is high, only the 5-V regulator is operating.
UVLO
When the input voltage exceeds 4 V, the IC is turned on and is ready to function. When the input voltage is lowerthan the turn on value, the IC is turned off. The typical hysteresis voltage is 40 mV.
phase inverter
The phase inverter controls the phase of CH1 and CH2, 3. CH2, 3 operate in the same phase as OSC. CH1operates 180° out of phase from OSC. Out-of-phase operation enables a smaller input capacitor.
OVP (12-V boost converter)
The TPS5140 monitors over voltage of the12-V boost converter. When an output over voltage is detected, thetimer starts to charge an external capacitor that is connected to the SCP terminal. After a programmable timedelay, the SCP circuit forces all (CH1, 2, 3 and 12 V) MOSFET drivers to latch-off.
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
UVP (12-V boost converter)
TPS5140 monitors output under voltage of the 12-V boost converter. When an output under voltage is detected,the timer starts to charge an external capacitor that is connected to the SCP terminal. After a programmabletime delay, the SCP circuit forces all (CH1, 2, 3, and 12 V) MOSFETs drivers to latch off.
SOFTSTART_12V
An internal capacitor exists for 12-V soft start. If the soft start time needs to be extended, an external capacitorshould be connected to this terminal. The12-V boost converter must start when REG5V_IN terminal is over4.5 V.
current limit of 12-V boost converter
The 12-V boost current limit monitors the current flowing through the internal MOSFET. When the voltage dropacross the internal N-channel MOSFET is high enough during its on time, the current limit circuit forces theinternal N-channel MOSFET to turn off.
PHASE_12V
The 12-V boost converter does not typically require phase compensation. If there is reason to change the phase,the 12-V boost converter can be phase compensated by inserting external resistors and capacitors to GND.Otherwise, the PHASE_12V terminal should be left open.
logic chartsTable 1. Logic Chart1
STBY1 STBY2 STBY3 CH1 CH2 CH3 PGOUT
L L L Disable Disable Disable N/A
L L H Disable Disable Enable Active†
L H L Disable Enable Disable Active†
L H H Disable Enable Enable Active†
H L L Enable Disable Disable Active†
H L H Enable Disable Enable Active†
H H L Enable Enable Disable Active†
H H H Enable Enable Enable Active†
† During softstart, PGOUT is active low.
Table 2. Logic Chart2
STBY_VREF5 STBY_VREF3.3 VREF5‡ VREF3.3
L L N/A Disable
H L Enable Disable
L H Enable Enable
H H Enable Enable‡ To disable VREF5, all STBY1, 2, 3, STBY_VREF3.3 and
STBY_VREF5 must be L.
Table 3. Logic Chart3
STBY12V REG5V_IN 12 VOUT
L L Disable
L H Disable
H L Disable
H H Enable
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PGOUT timing chart
PGOUT
PG_DELAY
STBY1
STBY2
INV1
INV2
td1
T(SS)
td2
H
L
H
LH
L1.185 VV(TH)
0 V1.185 VV(TH)
0 V
H
L
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage, VCC (see Note 1) –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage; INV1/2/3, CT, PWM_SEL, REG5V_IN, SOFTSTART1/2/3, SOFTSTART_12V –0.3 V to 7 V.
SCP, PG_DELAY, PHASE_12V, OUT1/2/3_d, VREF3.3/5, FB1/2/3 –0.3 V to 7 V. . . . . . . . . . . PGOUT, EXT_PG –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STBY1/2/3/12V, STBY_VREF3.3/5, TRIP1/2/3 –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . VCC_SENSE12/3, LL1/2/3 –0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LL_UP, OUT_12V, IN_12V –0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LH1/2/3, OUT1/2/3_u –0.3 V to 35 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REF –0.3 V to 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA (see Note 3) –20°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –55°C to 155°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.2. This rating is specified at duty = 10% on output rise and fall each pulse. Each pulse width (rise and fall) for the peak current should
not exceed 2 µs.3. See Dissipation Rating Table for free-air temperature range above 25°C.
DISSIPATION RATING TABLE
PACKAGETA ≤ 25°C
POWER DISSIPATIONDERATING FACTORABOVE TA = 25°C
TA = 85°CPOWER DISSIPATION
PAG 1811 mW 14.49 mW/°C 941.6 mW
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.5 28 V
INV1/2/3, CT, PG_DELAY, PWM_SEL SOFTSTART1/2/3 SOFT-START_12V, SCP PHASE_12V, PGOUT, EXT_PG,
6
I t lt VREG5V_IN –0.1 5.5
VInput voltage, VI STBY1/2/3/12V STBY_VREF3.3/5, TRIP1/2/3, VCC_SENSE12/3 –0.1 28V
OUT1/2/3_u, LH1/2/3 –0.1 33
LL_UP, OUT_12V, IN_12V –0.1 15
Oscillator frequency, fosc CT capacitance‡ 44 pF
Operation temperature range, TA –20 85 °C‡ The recommended maximum operating frequency is typically 300 kHz.
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V(unless otherwise noted)
reference voltagePARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Vref Reference voltage 1.185 V
V f(t l) Reference voltage toleranceTA = 25°C, I(vref) = 50 µA –1% 1%
Vref(tol) Reference voltage toleranceI(vref) = 50 µA –1.5% 1.5%
Line regulation VCC = 4.5 V to 28 V, I(vref) = 50 µA 0.05 3 mV
Load regulation I(vref) = 0.1 µA to 1 mA 0.15 5 mV
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V(unless otherwise noted) (continued)
oscillatorPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fosc Frequency PWM mode, CT = 56 pF, TA = 25°C 250 kHz
VOS(CH) High level output voltageDC 1 1.1 1.2
VVOS(CH) High-level output voltagefosc = 250 kHz 1.17
V
VOS(CL) Low level output voltageDC 0.4 0.5 0.6
VVOS(CL) Low-level output voltagefosc = 250 kHz 0.43
V
error amplifierPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIO Input offset voltage TA = 25°C 2 10 mV
A(V) Open-loop voltage gain 90 dB
G(B) Unity-gain bandwidth 2.5 MHz
I(snk) Output sink currentVO = 1 V
0.3 0.7mA
I(src) Output source currentVO = 1 V
0.4 0.9mA
duty controlPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CH1/3, fosc = 250 kHz 75%
Maximum duty cycle CH2, fosc = 250 kHz 85%
12V boost, fosc = 250 kHz 70%
controlPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage STBY1/2/3/12V, EXT_PGPWM_SEL, STBY_VREF5/3.3 2 V
VIL Low-level input voltage STBY1/2/3/12V, EXT_PGPWM_SEL, STBY_VREF5/3.3 0.3 V
5-V internal switchPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(TLH)Threshold voltage
High REG5V_IN 4.2 4.8V
V(THL)Threshold voltage
Low REG5V_IN 4.1 4.7V
Vhys Hysteresis 30 200 mV
VREF5PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Output voltageIO = 0 mA to 50 mA,TA = 25°C
VCC = 5.5 V to 28 V,4.8 5.2 V
Line regulation VCC = 5.5 V to 28 V, IO = 10 mA 20 mV
Load regulation IO = 1 mA to 10 mA, VCC = 5.5 V 40 mV
IOS Short circuit output current Vref = 0 V, TA = 25°C 65 mA
V(TLH)UVLO threshold voltage
HighVREF5 voltage
3.6 4.2V
V(THL)UVLO threshold voltage
LowVREF5 voltage
3.5 4.1V
Vhys Hysteresis VREF5 voltage 30 200 mV
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range, VCC = 7 V(unless otherwise noted) (continued)
VREF3.3PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO Output voltageIO = 0 mA to 30 mA,TA = 25°C
VCC = 5.5 V to 28 V,3.15 3.30 3.45 V
Line regulation VCC = 5.5 V to 28 V, IO = 10 mA 20 mV
Load regulation IO = 1 mA to 10 mA, VCC = 5.5 V 40 mV
IOS Short circuit output current Vref = 0 V, TA = 25°C –40 mA
outputPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUT uSink current VO = 3 V 1.2
AOUT_uSource current VO = 2 V –1.2
A
OUT dSink current VO = 3 V 1.5
AOUT_dSource current VO = 2 V –1.5
A
LL_UP Sink current VLL_UP = 0.3 V, OUT_12V = 12 V 0.65 A
OUT_12V Output impedance IN_12V = 12 V, IOUT_12V = 150 mA 1.1 Ω
I(TRIP) TRIP current TRIP1/2/3, TA = 25°C 11.5 13 15 µA
softstartPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I(CTRL) Soft start currentSoftstart1/2/3 –1.6 –2.3 –2.9
µAI(CTRL) Soft start currentSoftstart_12V –0.007
µA
output voltage monitorPARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OVP comparator threshold voltageCH1/2/3 1.28 1.33 1.38
VOVP comparator threshold voltage12 V boost 12.9 13.4 13.9
V
UVP comparator threshold voltageCH1/2/3 0.90 0.95 1
VUVP comparator threshold voltage12 V boost 9 9.5 10
V
PG comparator threshold voltagePG comparator1/2/3, upper threshold 1.22 1.27 1.32
VPG comparator threshold voltagePG comparator1/2/3, lower threshold 1.05 1.1 1.15
V
PG propagation delay from INV to INV = 0.985 V to 1.185 V, PG_DELAY = open 3.7µsPG ro agation delay from INV to
PG_OUT INV = 1.185 V to 0.985 V, PG_DELAY = open 8.9µs
IPG_DELAY) PG_DELAY source current 1.1 1.7 2.3 µA
I(SCP) SCP source currentUVP protection 1.5 2.3 3.1
µAI(SCP) SCP source currentOVP protection 8 11.5 15
µA
whole devicePARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Supply current 1.8 2.6 mA
IO(SD) Shutdown current STBY1/2/3/12V, STBY_VREF5/3.3 = 0 V 0.001 10 µA
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
1.55
1.60
1.65
1.70
1.75
1.80
1.85
–50 0 50 100 150
VCC = 28 V
VCC = 7 V
VCC = 4.5 V
QUIESCENT CURRENTvs
JUNCTION TEMPERATURE
– Q
uie
scen
t C
urr
ent
– m
AI C
C
TJ – Junction Temperature – °CFigure 1 Figure 2
0
50
100
150
200
250
–50 0 50 100 150
VCC = 28 V
VCC = 7 V
VCC = 4.5 V
QUIESCENT CURRENT (SHUTDOWN)vs
JUNCTION TEMPERATURE
– Q
uie
scen
t C
urr
ent
(Sh
utd
ow
n)
– n
AI C
C
TJ – Junction Temperature – °C
Figure 3
–2
–1.8
–1.6
–1.4
–1.2
–1
–0.8
–0.6
–0.40.5 1.5 2.5 3.5 4.5
I CC
– S
ou
rce
Dri
ve C
urr
ent
(OU
T_u
) –
A
SOURCE DRIVE CURRENT (OUT_u)vs
OUTPUT VOLTAGE
TJ = 85°C
TJ = –40°CTJ = –25°C
TJ = 25°C
TJ =125°C
VO – Output Voltage – V
Figure 4
0.25
0.50
0.75
1
1.25
1.50
0.5 1.5 2.5 3.5 4.5
I CC
– S
ink
Dri
ve C
urr
ent
(OU
T_u
) –
A
SINK DRIVE CURRENT (OUT_u)vs
OUTPUT VOLTAGE
TJ = 85°C
TJ = –40°C
TJ = –25°C
TJ = 25°C
TJ =125°C
VO – Output Voltage – V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
–1.6
–1.4
–1.2
–1
–0.8
–0.6
–0.40.5 1.5 2.5 3.5 4.5
I CC
– D
rive
cu
rren
t (O
UT
_d)
– A
DRIVE CURRENT (OUT_d)vs
OUTPUT VOLTAGE
PIN = OUT_d (Source)
TJ = 85°C
TJ = –40°C
TJ = –25°C
TJ = 25°C
TJ =125°C
VO – Output Voltage – V
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0.5 1.5 2.5 3.5 4.5
I CC
– S
ink
Dri
ve C
urr
ent
(OU
T_d
) –
A
SINK DRIVE CURRENT (OUT_d)vs
OUTPUT VOLTAGE
TJ = 85°C
TJ = –40°C
TJ = –25°C
TJ = 25°C
TJ =125°C
VO – Output Voltage – V
Figure 6
0
1
2
3
–50 0 50 100 150
OU
T_1
2V Im
ped
ance
–
OUT_12V IMPEDANCEvs
JUNCTION TEMPERATURE
Ω
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V,VCC = 28 V
Figure 7
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 8
1
1.05
1.10
1.15
1.20
–50 0 50 100 150
OSCILLATOR OUTPUT VOLTAGEvs
JUNCTION TEMPERATURE
– O
scill
ato
r O
utp
ut
Volt
age
– V
V(o
sch
)
TJ – Junction Temperature – °C
VCC = 4.5 V, 7 V, and 28 V
0.46
0.47
0.48
0.49
0.50
–50 0 50 100 150
OSCILLATOR OUTPUT VOLTAGEvs
JUNCTION TEMPERATURE
– O
scill
ato
r O
utp
ut
Volt
age
– V
V(o
scl)
TJ – Junction Temperature – °C
VCC = 4.5 V, 7 V, and 28 V
Figure 9
Figure 10
–5
–4
–3
–2
–1
0
1
2
3
4
5
–50 0 50 100 150
– E
rro
r A
mp
lifie
r In
pu
t O
ffse
t V
olt
age
– m
V
ERROR AMPLIFIER INPUT OFFSET VOLTAGEvs
JUNCTION TEMPERATURE
VIO
TJ – Junction Temperature – °C
VCC = 7 V
Figure 11
1.5
1.8
2
2.3
2.5
2.8
3
–50 0 50 100 150
– E
rro
r A
mp
lifie
r O
utp
ut
Vo
ltag
e –
V
ERROR AMPLIFIER OUTPUT VOLTAGEvs
JUNCTION TEMPERATURE
V O(+
)
TJ – Junction Temperature – °C
VCC = 4.5 V, 7 V, and 28 V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
19POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
0
1
2
3
4
–50 0 50 100 150
– E
rro
r A
mp
lifie
r O
utp
ut
Vo
ltag
e –
V
ERROR AMPLIFIER OUTPUT VOLTAGEvs
JUNCTION TEMPERATURE
V O(–
)
TJ – Junction Temperature – °C
VCC = 4.5 V, 7 V, and 28 V
Figure 13
0
0.5
1
1.5
2
–50 0 50 100 150
Sta
nd
by
Sw
itch
Th
resh
old
Vo
ltag
e –
V
STANDBY SWITCH THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
V(TLH)
V(THL)
VCC = 4.5 V, 7 V, and 28 V
Figure 14
4.2
4.3
4.4
4.5
4.6
4.7
–50 0 50 100 150
Th
resh
old
Vo
ltag
e (R
EG
5_IN
) –
V
THRESHOLD VOLTAGE (REG5_IN)vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
V(TLH)
V(THL)
Figure 15
5.04
5.05
5.06
5.07
5.08
5.09
5.10
5 10 15 20 25 30
– O
utp
ut
Vo
ltag
e (V
RE
F5)
– V
OUTPUT VOLTAGE (VREF5)vs
SUPPLY VOLTAGE
VCC – Supply Voltage – V
VO
TJ = 85°C
TJ = –40°C
TJ = –20°C
TJ = 25°C
TJ =125°C
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 16
ICC – Output Current – mA
5
5.02
5.04
5.06
5.08
5.10
0 10 20 30 40 50
– O
utp
ut
Vo
ltag
e (V
RE
F5)
– V
OUTPUT VOLTAGE (VREF5)vs
OUTPUT CURRENT
VO
TJ = 85°C
TJ = –40°CTJ = –20°C
TJ = 25°C
TJ =125°C
Figure 17
–150
–125
–100
–75
–50–50 0 50 100 150
VCC = 28 V
VCC = 7 V
VCC = 4.5 V
– S
ho
rt-C
ircu
it C
urr
ent
(VR
EF
5) –
V
SHORT-CIRCUIT CURRENT (VREF5)vs
JUNCTION TEMPERATURE
I OS
TJ – Junction Temperature – °C
Figure 18
3.60
3.65
3.70
3.75
3.80
3.85
3.90
–50 0 50 100 150
– U
VL
O T
hre
sho
ld V
olt
age
– V
UVLO THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
Vth
TJ – Junction Temperature – °C
V(TLH)
V(THL)
Figure 19
60
80
100
120
140
–50 0 50 100 150
– U
VL
O H
yste
resi
s V
olt
age
– m
V
UVLO HYSTERESIS VOLTAGEvs
JUNCTION TEMPERATURE
Vh
ys
TJ – Junction Temperature – °C
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
21POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 20
3.10
3.15
3.20
3.25
3.30
3.35
3.40
4.8 4.9 5.0 5.1 5.2
– O
utp
ut
Vo
ltag
e (V
RE
F3.
3) –
V
OUTPUT VOLTAGE (VREF3.3)vs
INPUT VOLTAGE (VREF5)
VO
VI – Input Voltage (VREF5) – V
TJ = –40°C,TJ = –20°C,TJ = 25°C,TJ = 85°C,TJ = 125°C
Figure 21
3
3.1
3.2
3.3
3.4
0 10 20 30 40 50
TJ = –40°C,TJ = –20°C,
TJ = 25°C
TJ = 85°C
TJ = 125°C
OUTPUT VOLTAGE (VREF3.3)vs
OUTPUT CURRENT
IO – Output Current – mA
– O
utp
ut
Vo
ltag
e (V
RE
F3.
3) –
VV
O
Figure 22
–90
–80
–70
–60
–50–50 0 50 100 150
– S
ho
rt-C
ircu
it (
VR
EF
3.3)
– m
A
SHORT-CIRCUIT (VREF3.3)vs
JUNCTION TEMPERATURE
I OS
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V,VCC = 2.8 V
Figure 23
–2.32
–2.30
–2.28
–2.26
–2.24
–2.22
–2.20
–2.18
–2.16–50 0 50 100 150
So
ftst
art
Cu
rren
t –
SOFTSTART CURRENTvs
JUNCTION TEMPERATURE
Aµ
TJ – Junction Temperature – °C
VCC = 7 V,VCC = 28 V
VCC = 4.5 V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 24
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0–50 0 50 100 150
12-V
Bo
ost
So
ftst
art
Cu
rren
t –
nA
12-V BOOST SOFTSTART CURRENTvs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V,VCC = 28 V
Figure 25
50
60
70
80
90
100
–50 0 50 100 150
CH2
CH1/3
CH4
Max
Du
ty –
%
MAX DUTYvs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
fosc = 250 kHz
Figure 26
1.20
1.25
1.30
1.35
1.40
–50 0 50 100 150
– O
VP
Th
resh
old
Vo
ltag
e –
V
OVP THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
Vth
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V,VCC = 28 V
Figure 27
13
13.2
13.4
13.6
13.8
14
–50 0 50 100 150
– 12
-V B
oo
st O
VP
Th
resh
old
Vo
ltag
e –
V
12-V BOOST OVP THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
Vth
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V,VCC = 28 V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
23POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 28
0.90
0.92
0.94
0.96
0.98
1
–50 0 50 100 150
– U
VP
Th
resh
old
Vo
ltag
e –
V
UVP THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
Vth
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V,VCC = 28 V
Figure 29
– 12
-V B
oo
st U
VP
Th
resh
old
Vo
ltag
e –
V
12-V BOOST UVP THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
Vth
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V,VCC = 28 V
Figure 30
1.05
1.10
1.15
1.20
1.25
1.30
–50 0 50 100 150
– P
ow
er G
oo
d T
hre
sho
ld V
olt
age
– V
POWER GOOD THRESHOLD VOLTAGEvs
JUNCTION TEMPERATURE
Vth
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V,VCC = 28 V
V(TLH)
V(THL)
Figure 31
0.6
0.7
0.8
0.9
1
–50 0 50 100 150
– T
hre
sho
ld V
olt
age
(EX
T_P
G)
– V
THRESHOLD VOLTAGE (EXT_PG)vs
JUNCTION TEMPERATURE
Vth
TJ – Junction Temperature – °C
VCC = 4.5 V
VCC = 7 V,VCC = 28 V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 32
–1.80
–1.75
–1.70
–1.65
–1.60–50 0 50 100 150
SOURCE CURRENT (PG_DELAY)vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
VCC = 7 V
– S
ou
rce
Cu
rren
t (P
G_D
EL
AY
) –
I SA
µ
Figure 33
–13
–12.5
–12
–11.5
–11
–10.5
–10–50 0 50 100 150
SC
P (
OV
P)
So
urc
e C
urr
ent
–
SCP (OVP) SOURCE CURRENTvs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
VCC = 4.5 V,VCC = 7 V
Aµ
VCC = 28 V
Figure 34
–2.40
–2.35
–2.30
–2.25
–2.20–50 0 50 100 150
SC
P (
UV
P)
So
urc
e C
urr
ent
–
SCP (UVP) SOURCE CURRENTvs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
VCC = 4.5 V
Aµ
VCC = 28 V
VCC = 7 V
Figure 35
VI – Trip Input Voltage – V
12.5
12.6
12.7
12.8
12.9
13.0
5 10 15 20 25 30
– Tr
ip S
ink
Cu
rren
t –
TRIP SINK CURRENTvs
TRIP INPUT VOLTAGE
I (si
nk)
Aµ TJ = 85°C
TJ = –40°C
TJ = –20°C
TJ = 25°C
TJ =125°C
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
25POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 36
285
290
295
300
305
–50 0 50 100 150
OSCILLATOR FREQUENCYvs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
VCC = 4.5 V
VCC = 28 V
VCC = 7 V
– O
scill
ato
r F
req
uen
cy –
KH
zf
osc
Figure 37
0
0.2
0.4
0.6
0.8
1
1.2
1.4
10 100 1000
VO(SCH)
VO(SCL)
Osc
illat
or
Ou
tpu
t V
olt
age
– V
f – Frequency – KHz
OSCILLATOR OUTPUT VOLTAGEvs
FREQUENCY
Figure 38
10
100
1000
0 50 100 150 200
– O
scill
ato
r F
req
uen
cy –
KH
z
OSCILLATOR FREQUENCYvs
CAPACITANCE
C – Capacitance – pF
fo
sc
Figure 39
1
10
100
1 k
10 k
100 k
10 100 1 k 10 k 100 k
UVP
OVP
– S
CP
Del
ay T
ime
–
C – Capacitance – pF
SCP DELAY TIMEvs
CAPACITANCE
t ds
µ
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
10
100
1 k
10 k
10 100 1 k 10 k
PG
_DE
LA
Y T
ime
–
PG_DELAY Capacitance – pF
PG_DELAY TIMEvs
PG_DELAY CAPACITANCE
sµ
VCC = 7 V
Figure 40
SOFTSTART TIMEvs
CAPACITANCE
10
100
1 k
10 k
100 k
10 100 1 k 10 k 100 k
VCC = 7 V
So
ftst
art
Tim
e –
C – Capacitance – pF
sµ
Figure 41
70
75
80
85
90
95
100
–50 0 50 100 150
t –
Dri
ver
Dea
d T
ime
(OU
T_u
FA
LL
) –
ns
DRIVER DEAD TIME (OUT_u FALL)vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
VCC = 7 V, 28 V
VCC = 4.5 V
Figure 42 Figure 43
140
142
144
146
148
150
152
154
–50 0 50 100 150
t –
Dri
ver
Dea
d T
ime
(OU
T_u
RIS
E)
– n
s
DRIVER DEAD TIME (OUT_u RISE)vs
JUNCTION TEMPERATURE
TJ – Junction Temperature – °C
VCC = 4.5 V
VCC = 7 V, 28 V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
27POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The design shown in this data sheet is a reference design for system power of notebook PC applications. Anevaluation module (EVM), TPS5140EVM-172 (SLVP172), is available for customer testing and evaluation. Theintent is to allow a customer to fully evaluate the given design using the plug-in EVM supply shown here. Forsubsequent customer board revisions, the EVM design can be copied onto the users’ PCB to shorten designcycle. The following key design procedures will aid in the design of the notebook PC power supply using theTPS5140.
EVM input and outputs
VO1 VO2 VO3 VO4
Output voltage VI range = 7 V ≈ 25 V 3.3 V 5 V 2.5 V 12 V
Maximum output current II(max) = 9 A 4 A 5 A 2 A 120 mA
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33343536373839404142434445464748
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
FB
1
SO
FT
STA
RT
1
NC
INV
2
FB
2
SO
FT
STA
RT
2
PW
M_S
EL
CT
GN
D
RE
F
ST
BY
_VR
EF
3.3
ST
BY
_VR
EF
5
ST
BY
1
ST
BY
2
ST
BY
12V
ST
BY
3 SCP
PGOUT
PG_DELAY
NC
EXT_PG
SOFTSTART_12V
PHASE_12V
SOFTSTART3FB3
INV3
NC
LH3
OUT_u
LL3
OUT_d
OUTGND3
NC
TR
IP3
VC
C_S
EN
SE
3
NC
OU
T_1
2V
IN_1
2V
LL_U
P
GN
D_U
P
NC
RE
G5V
_IN
VR
EF
5
VR
EF
3.3
NC
CC
V
NC
LH2
OUT2_u
LL2
OUT2_d
OUTGND2TRIP2
VCC_SENSE12
TRIP1
OUTGND1
OUT1_d
NC
LL1
OUT1_u
LH1
INV1
C18
R12
R11
A
R11
B
C27R
25R
10A
R10
B
C02
C03
R03
RO
1A
R01
BC
28
R26
R02
B
R02
A
C04
C05
R14R13
JP00
JP01
JP02
JP03
JP04
JP05
JP06
C06
R16
C22
C07
R17 C23
C08
R05
A
3 3 3 3 3 3
1 1 1 1 1 12 2 2 2 2 2
31 2
C19
R05
B
R04 C09
R06
B
R27
R06
A C29
D3
EX
T_P
G
TP
S51
401P
AG
Q05
Q06
D7
C10
C26
L3C
11A
C11
B
C20
VO
3–1
VO
3–2
R07 C
32
VR
EF
5
OU
T_1
2V
C01
AC
01B
VIN
–3
VIN
–2
L4
D4
C21
C12
C13
VR
EF
3.3
Q03
Q04
C25
D2
C14
U1
VO
2–1
VO
2–2
C15
AC
15B
JP08
L2
R08 C
30
R09C
31
Q01
Q02
C24
C16
AC
16B
L1V
01–1
V01
–2
R19
C17D1 NC
NC
R24
R22
D6
D5
Figure 44. EVM Schematic
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
29POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SMPS (synchronous mode power supply)
output voltage setpoint calculation
The reference voltage and the voltage divider set the output voltage. In the TPS5140, the reference voltage is1.185 V, and the divider is composed of two resistors in the EVM design that are R01A, R01B and R02A, R02B,or R10A, R10B and R11A, R11B, or R06A, R06B and R05A, R05B. The equation for the setpoint is:
R1 R2 VO– Vref
Vref
where R1 is the top resistor (kΩ) (R01A and R01B, R10A and R10B or R06A and R06B); R2 is the bottomresistor (kΩ) (R02A and R02B, R11A and R11B or R05A and R05B); VO is the required output voltage (V); Vrefis the reference voltage (1.185 V in TPS5140).
Example: R2 = 10 kΩ; Vref = 1.185 V; VO = 5 V, then R1 = 32.19 kΩ
Some of the most popular output voltage setpoints are calculated in the table below:
VO 1.3 V 1.5 V 1.8 V 2.5 V 3.3 V 5 V
R1 (top) (kΩ) 0.97 2.66 5.19 11.10 17.85 32.19
R2 (bottom) (kΩ) 10 10 10 10 10 10
If user changes the resistor value, the R2 (bottom) value should be over 10 kΩ due to the phase compensation.
output inductor ripple current
The output inductor current l(ripple) can affect not only the efficiency, but also the output voltage ripple. Theequation is exhibited below:
I(ripple) VI – VO– IOrDS(on) RL
L(out)
D ts
where ripple is the peak-to-peak ripple current (A) through the inductor; VI is the input voltage (V); VO is theoutput voltage (V); IO is the output current; rDS(on) is the on-time resistance of the MOSFET (Ω); RL is theparasitic resistance of the inductor; D is the duty cycle; and ts is the switching period (s). From the equation,it can be seen that the current ripple can be adjusted by changing the output inductor value.
Example: If VI = 10 V; VO = 5 V; IO = 5 A; rDS(on) = 26 mΩ; RL = 5 mΩ; D = 0.50; ts = 4 µs; L(out) = 6.1 µH, thenthe ripple current I(ripple) = 1.589 A.
output capacitor RMS current
Assuming the inductor ripple current goes completely through the output capacitor to ground, the RMS currentin the output capacitor can be calculated as:
IO(rms) I(ripple) x 3
6
where IO(rms) is the maximum RMS current in the output capacitor (A) and I(ripple) is the peak-to-peak inductorripple current (A).
Example: I(ripple)= 1.589 A, so IO(rms) = 0.459 A
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SMPS (synchronous mode power supply) (continued)
input capacitor RMS current
Assuming the input current goes completely into the input capacitor to the power ground, the RMS current inthe input capacitor can be calculated as:
II(rms) IO2 D (1–D)
where II(rms) is the input RMS current in the input capacitor (A), IO is the output current (A), and D is the dutycycle. From the equation, it can be seen that the highest input RMS current usually occurs at the lowest inputvoltage, so it is the worst case design for input capacitor ripple current.
Example: IO = 5 A; D = 0.50
Then, II(rms) = 2.5 A.
soft start
The soft start timing can be adjusted by selecting the soft start capacitor value. The equation is exhibited below:
C(soft) 2.3 T(soft)
1.185
where C(soft) is the soft start capacitor (µF) (C19, C03 or C08 in EVM design), and T(soft) is the start up time(s).
Example: T(soft) =5 ms, so C(soft) = 0.01 µF.
current limit protection
The current limit in the TPS5140 on each channel is set using an internal current source and an external resistor(R09, R08 or R07). The sensed low-side MOSFET drain-to-source voltage is compared to the set point. If thevoltage exceeds the limit, the internal oscillator is activated, and it continuously resets the current limit until theover-current condition is removed or SCP latches outputs off (see timer-latch SCP). The equation below shouldbe used for calculating the external resistor value for the current protection set point. Also, only CH2 monitorsboth high-side and low-side MOSFET drain-to-source voltage.
R(cl)
rDS(on)I(trip) I(ripple)
2 0.000013
where R(cl) is the external current limit resistor (R09, R08 or R07), and rDS(on) is the low side MOSFET (Q02,Q03 or Q05) on-time resistance. I(trip) is the required current limit and I(ripple) is the peak-to-peak output inductorcurrent.
Example: rDS(on) = 26 mΩ, I(trip) =7 A, I(ripple) = 1.589 A, so R(cl) = 16 kΩ.
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
31POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
SMPS (synchronous mode power supply) (continued)
timer-latch SCP
The TPS5140 includes the function of the fault latch with timer to latch the MOSFET driver after constant timepasses since the unusual condition of the output was detected. When the OVP or UVP comparator detects afault condition, the timer starts to charge the SCP capacitor (C06), which is connected to the SCP terminal. Ifthe SCP terminal goes up to 1.185 V, the fault latch is set.
over current protection and under voltage protection
When the current limit circuit limits the output current, then the output voltage will go below the target outputvoltage and the UVP comparator detects a fault condition. The timer starts to charge the SCP capacitor whenthe UVP comparator detects the output under voltage and the fault latch will be set after T(uvplatch) has past.When UVP is latched, all output MOSFET drivers of the TPS5140 turn OFF. The equation below should be usedfor calculating the T(uvplatch):
C(scp)2.3 T(uvplatch)
1.185
over voltage protection
When OVP comparator detects the output over voltage, the timer starts to charge the SCP capacitor, and thefault latch will be set after T(ovplatch) has past. In case of OVP-latch, the high-side drivers of both channels areforced OFF and the low-side drivers of both channels are forced ON. The equation below should be used forcalculating the T(ovplatch):
C(scp)11.5 T(ovplatch)
1.185
where C(scp) is the external capacitor, T(uvplatch) is time from the UVP detection to latch, and T(ovplatch) is thetime from OVP detection to latch.
Example: T(uvplatch) = 515 µs, T(ovplatch) = 103 µs, so C(scp) = 0.001 µF
notice—usage of timer-latch
The SCP should not be set to a lower voltage (or GND) while the device is holding the latch-off status of the OVPor UVP. If the SCP terminal is manually set to a lower voltage in this term, an output overshoot may occur. TheTPS5140 must be reset by grounding the STBY1,2,3 and STBY_VREF5,3.3 or by dropping the VCC below theUVLO voltage.
disablement the protection function
When debugging the circuit once preliminary calculations have been performed, the evaluation may behampered because the protection circuitry does not operate properly. In this case, the TPS5140 is able toinvalidated the protection circuits for debugging.
OCP: Removing the resistor for the current limit and opening the TRIP terminal can disable the OCP.OVP, UVP: Grounding the SCP terminal can disable the OVP and UVP.
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
3.3 V linear regulator
The VREF3.3 terminal is the output of the 3.3-V linear regulator. The VREF3.3 terminal should be connectedto an output capacitor. A ceramic capacitor of 4.7 µF is recommended for stability of the output voltage.
REG5V_IN
The REG5V_IN terminal should be connected to the external 5 V (output of CH2), to decrease the powerdissipation. Also, this terminal has an OVP comparator. If this terminal voltage exceeds a threshold voltage, thetimer starts to charge the SCP capacitor, and all of output is forced to OFF.
12 V boost up converter
The TPS5140 has a boost up converter (12 V). The inductor (L4) which uses this boost up converter should beconnected to the external 5 V. Also, the inductor value is recommended to be 22 µH. The OUT_12V terminalshould be connected to the output capacitor. A ceramic capacitor of 10 µF is recommended for stability of theoutput voltage. It is also recommended that a ceramic capacitor (around 0.1 µF) be connected between theIN_12V terminal and the GND_UP terminal.
soft start 12 V
This soft start terminal is connected to the internal capacitor. To extend the soft start time, this terminal shouldbe connected to the external capacitor. The equation is:
30 C(ext) x 1.185 3.8 x T(soft_12V)
where C(ext) is the 12-V soft start capacitor (pF) and T(soft_12V) is the start-up time (ms).
Example: C(ext) = 33 pF, so T(soft_12V) = 19.6 ms
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
33POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
phase compensation for 12-V boost
The 12-V boost up converter is compensated to the phase margin. If the output components are changed, thephase margin will change. Therefore, the phase margin needs to be compensated. A resistor and capacitorshould be connected in series from the PHASE_12V terminal to GND. If the inductor used is 22 µH and theoutput capacitor is 10 µF (ceramic), there is no need to compensate. The equivalent circuit of the 12-V boostis shown in Figure 45.
_
+
REF
+Gm
30 kΩ
275.5 kΩ80 pF
SS
Gm = 292 µS
18 kΩ
102 kΩ_+
CT
PWM COMP
5 V
5 V_IN_HSS_ Finish12 VSTBY
10 µF
LOAD
22 µH
5 V
0.1 µF
38
37
39
IN_12 V
40GND_UP
LL_UP
OUT_12 V
_
+
8 pF
3 kΩ3 kΩ3 kΩ
R1
R3
200 kΩ
23PHASE_12 V
I2
I1
60 pFC1
RP =R2+R3
R1CP
PHASE_12 VAC EquivalentCircuit
R2
RP = R2+R3 = 6 kR1 >> RPI1 x RP = I2 x R1I1 x 6 k = I2 x 200 kI1 = (200 k ÷ 6 k) x (I2 = 33.3 x I2)CP = (R1÷ RP) x (C1 – 33.3 x C1)CP = 33.3 x 60 p F= 1998 pF
Figure 45. THS5140 12-V boost circuit
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
auto PWM/SKIP
Auto PWM/SKIP function monitors the drain-source voltage of the low-side MOSFET.
In the PWM mode to SKIP mode, when output currents decrease, the negative voltage between LL to GND isdecreasing. If this voltage is positive voltage to GND, the auto SKIP circuit detects the SKIP mode. After a fixedtime, the controller changes to SKIP mode.
In the SKIP mode to PMW mode, when output currents increase, the positive voltage between LL to GND isdecreasing. In the SKIP mode, the auto PWM detect circuit has an offset voltage of about 20 mV. If the positivevoltage between LL to GND decreases and becomes negative beyond the offset voltage of the GND level, thenthe auto PWM circuit detects the PWM mode, and the controller changes to the PWM mode.
Detect Detect
GND
Detect
SKIP Mode
PWM ModeOne Fixed Time
PWM to SKIP
SKIP to PMW
Detect
20 mV
OffsetVoltage20 mV
Figure 46. Timing Chart for the Auto PWM/SKIP Mode Function
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
35POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout guidelines
Good power supply results will only occur when care is given to proper design and layout. Layout will affect noisepickup and generation yet cause a good design to perform with less than expected results. With a range ofcurrents from milliamps to tens of amps, good power supply layout is much more difficult than most general PCBdesigns. The general design should proceed from the switching node to the output, then back to the driversection and, finally, parallel the low-level components. Below are several specific points to consider before thelayout of a TPS5140 design begins.
ANAGND and DRVGND should be isolated as much as possible.
All sensitive analog components should reference to ANAGND. Terminals INV1/2/3, REF, CT, GND, SCP,and SOFTSTART1/2/3/12V should be placed in ANAGND.
Ideally, all of the area under TPS5140 is also ANAGND.
The source of the low-side MOSFETs should not be placed in the trace from ANAGND to DRVGNDotherwise ANAGND is under the influence of output noise.
The switch transitions in one channel may disturb the operation of other channels. So, the impedancebetween VCC and GND wiring pattern should be as small as possible.
The PCB is a four-layer pattern. This should be composed of power plane, power ground plane, signalground plane, and signal plane.
TPS5140
FB
SOFTSTART
CT
GND
REF
SCP
OUT_uINV OUT_d
From VO
DRVGNDOUT3_d
OUT3_uVREF5
TRIP3
OUT2_d
OUT2_u
TRIP2
VCC andVCC_SENSE
TRIP1
VO1
VIN
VO2
VO3
ANAGND
Figure 47. SLVP172 Four Layer PCB Diagram
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout guidelines (continued)
DRVGND will connect to the main ground plane, close to the source of the low-side MOSFET.
OUTGND1/2/3 should be placed close to the source of low-side MOSFET.
The parallel Schottky diode, the high frequency bypass capacitors for MOSFETs, and the source ofthe low-side MOSFETs should be placed as close to each other as possible.
TPS5140
FB
SOFTSTART
CT
GND
REF
SCP
OUT_uINV OUT_d
From VO
DRVGNDOUT3_d
OUT3_uVREF5
TRIP3
OUT2_d
OUT2_u
TRIP2
VCC andVCC_SENSE
TRIP1
VO1
VIN
VO2
VO3
ANAGND
OUTGND1
OUTGND2
OUTGND3
Figure 48. SLVP172 Low-Side MOSFETs Diagram
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
37POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout guidelines (continued)
Connections from the drivers to the gate of the power FETs should be as short and as wide as possible toreduce stray inductance. This becomes more critical if the external gate resistors are not being used. Inaddition, when dealing with current limit noise when using a MOSFET with a large input capacitance, a gateresistor should be inserted on the high side MOSFET to reduce the switching noise of the MOSFET.
The connection from LL to the power FETs should be as short as and wide as possible.
TPS5140
FB
SOFTSTART
CT
GND
REF
SCP
OUT_uINV
OUT_d
From VO
DRVGNDOUT3_d
OUT3_u
VREF5
OUT2_d
VCC andVCC_SENSE
VO1
VIN
VO2
VO3
ANAGND
OUT2_u
LL2
LL3
LH3
LH2
LL1LH1
OUT1_d
Figure 49. Connections From the Drivers to the Gate Diagram
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout guidelines (continued)
The bypass capacitor for VCC should be placed close to the TPS5140.
The bulk storage capacitors across VI should be placed close to the power FETs. High-frequency bypasscapacitors should be placed in parallel with the bulk capacitors and connected close to the drain of thehigh-side FET and to the source of the low-side FET.
Current limit set resistors must be connected to the drain of the high-side FET. A 0.1-µF capacitor shouldbe placed in parallel with these resistors to align the phase between the drain of high-side FETs and thetrip pin.
TPS5140
FB
SOFTSTART
CT
GND
REF
SCP
OUT_uINV OUT_d
From VO
DRVGNDOUT3_d
OUT3_uVREF5
TRIP3
OUT2_d
OUT2_u
TRIP2
VCC andVCC_SENSE
TRIP1
VO1
VIN
VO2
VO3
ANAGND
Figure 50. Bypass Capacitor Diagram
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
39POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout guidelines (continued)
The capacitor for VREF5 should be placed close to the TPS5140.
The bootstrap capacitor (connected from LH to LL) should be placed close to the TPS5140.
LH and LL should be routed close to each other to minimize differential mode noise coupling to these traces.
The VREF5 capacitor should be placed close to DRVGND.
LH and LL should not be routed near the control pin area. (ex. INV, FB, REF, etc.)
TPS5140
FB
SOFTSTART
CT
GND
REF
SCP
OUT_uINV
OUT_d
From VO
DRVGNDOUT3_d
OUT3_u
VREF5
OUT2_d
VCC andVCC_SENSE
VO1
VIN
VO2
VO3
ANAGND
OUT2_u
LL2
LL3
LH3
LH2
LL1LH1
OUT1_d
Figure 51. VREF5 Capacitor Diagram
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
40 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout guidelines (continued)
The output voltage sensing trace should be isolated by either ground trace.
The output voltage sensing trace should not be routed under the inductors on same layer of the PCB.
The feedback components should be isolated from the output components such as MOSFETs, inductors,and output capacitors. Otherwise noise from the output components may couple into the feedback signallines.
The resistors for the output voltage set point should be connected to ANAGND.
INV1/2/3 line should be as short as possible.
TPS5140
FB
SOFTSTART
CT
GND
REF
SCP
OUT_uINV
OUT_d
From VO
DRVGNDOUT3_d
OUT3_u
VREF5
OUT2_d
VCC andVCC_SENSE
VO1
VIN
VO2
VO3
ANAGND
OUT2_u
LL2
LL3
LH3
LH2
LL1LH1
OUT1_d
Figure 52. Output Voltage Diagram
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
41POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
50
60
70
80
90
100
0 0.5 1 1.5 2IO – Output Current – A
VI = 7 V,VO= 2.5 V
Eff
icie
ncy
%
FIXED PWM MODE EFFICIENCY
Figure 53
IO – Output Current – A
VI = 25 V,VO= 2.5 V
Eff
icie
ncy
%
FIXED PWM MODE EFFICIENCY
50
60
70
80
90
100
0 0.5 1 1.5 2
Figure 54
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
IO – Output Current – A
VI = 7 V,VO= 2.5 V
Eff
icie
ncy
%
AUTO/SKIP MODE EFFICIENCY
Figure 55
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
IO – Output Current – A
VI = 25 V,VO= 2.5 V
Eff
icie
ncy
%
AUTO/SKIP MODE EFFICIENCY
Figure 56
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
42 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 57
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3 3.5 4
IO – Output Current – A
VI = 7 V,VO = 3.3 V
Eff
icie
ncy
%
FIXED PWM MODE EFFICIENCY
Figure 58
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3 3.5 4
IO – Output Current – A
VI = 25 V,VO= 3.3 V
Eff
icie
ncy
%
FIXED PWM MODE EFFICIENCY
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
IO – Output Current – A
VI = 7 V,VO= 3.3 V
Eff
icie
ncy
%
AUTO/SKIP MODE EFFICIENCY
Figure 59 Figure 60
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
IO – Output Current – A
VI = 25 V,VO= 3.3 V
Eff
icie
ncy
%
AUTO/SKIP MODE EFFICIENCY
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
43POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 61
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VI = 7 V,VO = 5 V
IO – Output Current – A
Eff
icie
ncy
%
FIXED PWM MODE EFFICIENCY
Figure 62
50
60
70
80
90
100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VI =25 V,VO = 5 V
IO – Output Current – AE
ffic
ien
cy %
FIXED PWM MODE EFFICIENCY
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
IO – Output Current – A
VI = 7 V,VO = 5 V
Eff
icie
ncy
%
AUTO/SKIP MODE EFFICIENCY
Figure 63 Figure 64
50
60
70
80
90
100
0 0.25 0.5 0.75 1 1.25 1.5
IO – Output Current – A
VI = 25 V,VO = 5 V
Eff
icie
ncy
%
AUTO/SKIP MODE EFFICIENCY
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
44 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
50
60
70
80
90
100
0 0.025 0.050 0.075 0.100 0.125 0.150IO – Output Current – A
Eff
icie
ncy
%
12 V BOOST EFFICIENCY
Figure 65 Figure 66
2.530
2.532
2.534
2.536
2.538
2.540
5 10 15 20 25 30
IO = 2 A,VO = 2.5 V
– O
utp
ut
Vo
ltag
e –
V
OUTPUT LINE REGULATION
VO
VI – Input Voltage – V
3.300
3.302
3.304
3.306
3.308
3.310
5 10 15 20 25 30
IO = 4 A,VO = 3.3 V
– O
utp
ut
Vo
ltag
e –
V
OUTPUT LINE REGULATION
VO
VI – Input Voltage – V
Figure 67 Figure 68
5.070
5.072
5.074
5.076
5.078
5.080
5 10 15 20 25 30
IO = 5 A,VO = 5 V
– O
utp
ut
Vo
ltag
e –
V
OUTPUT LINE REGULATION
VO
VI – Input Voltage – V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
45POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 69
12.070
12.072
12.074
12.076
12.078
12.080
5 10 15 20 25 30
IO = 100 mA,VO = 12 V
– O
utp
ut
Vo
ltag
e –
V
OUTPUT LINE REGULATION
VO
VI – Input Voltage – V
Figure 70
2.50
2.52
2.54
2.56
2.58
2.60
0 0.5 1 1.5 2
OUTPUT LOAD REGULATION
VI = 7 V,VO = 2.5 V
– O
utp
ut
Vo
ltag
e –
VV
OIO – Output Current – A
Figure 71
2.50
2.52
2.54
2.56
2.58
2.60
0 0.5 1 1.5 2
OUTPUT LOAD REGULATION
VI = 25 V,VO = 2.5 V
– O
utp
ut
Vo
ltag
e –
VV
O
IO – Output Current – A
Figure 72
3.20
3.25
3.30
3.35
3.40
0 1 2 3 4
OUTPUT LOAD REGULATION
– O
utp
ut
Vo
ltag
e –
VV
O
IO – Output Current – A
VI = 7 V,VO = 3.3 V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
46 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 73
3.20
3.25
3.30
3.35
3.40
0 1 2 3 4
OUTPUT LOAD REGULATION
– O
utp
ut
Vo
ltag
e –
VV
O
IO – Output Current – A
VI = 25 V,VO= 3.3 V
Figure 74
5
5.05
5.10
5.15
5.20
0 1 2 3 4 5
OUTPUT LOAD REGULATION
– O
utp
ut
Vo
ltag
e –
VV
O
IO – Output Current – A
VI = 7 V,VO= 5 V
Figure 75
5
5.05
5.10
5.15
5.20
0 1 2 3 4 5
OUTPUT LOAD REGULATION
– O
utp
ut
Vo
ltag
e –
VV
O
IO – Output Current – A
VI = 25 V,VO = 5 V
12
12.05
12.10
12.15
12.20
0 0.025 0.05 0.075 0.1 0.125 0.15
OUTPUT LOAD REGULATION
– O
utp
ut
Vo
ltag
e –
VV
O
IO – Output Current – A
VO = 12 V
Figure 76
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
47POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 77
3.290
3.295
3.300
3.305
3.310
5 10 15 20 25 30
IO = 10 mA,VO = VREF 3.3 V
– O
utp
ut
Vo
ltag
e –
V
OUTPUT LINE REGULATION
VO
VI – Input Voltage – V
Figure 78
3.25
3.28
3.30
3.33
3.35
0 0.01 0.02 0.03 0.04
OUTPUT LOAD REGULATION
– O
utp
ut
Vo
ltag
e –
VV
OIO – Output Current – A
VI = 7 V,VO = VREF 3.3 V
Figure 79
3.25
3.28
3.30
3.33
3.35
0 0.01 0.02 0.03 0.04
OUTPUT LOAD REGULATION
– O
utp
ut
Vo
ltag
e –
VV
O
IO – Output Current – A
VI = 25 V,VO = VREF 3.3 V
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
48 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 80
2.5 V OUTPUT VOLTAGE RIPPLE
VI = 7 V IO = 0.5 A
IO = 2 A20 mV/div
2 µs/div
Figure 81
3.3 V OUTPUT VOLTAGE RIPPLE
VI = 7 V IO = 0.5 A
IO = 2 A
20 mV/div 2 µs/div
IO = 4 A
Figure 82
5 V OUTPUT VOLTAGE RIPPLE
VI = 7 V IO = 0.5 A
IO = 2 A
50 mV/div 2 µs/div
IO = 5 A
12 V OUTPUT VOLTAGE RIPPLE
VI = 7 V IO = 50 mA
2 µs/div
IO = 100 mA
Figure 83
20 mV/div
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
49POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 84
VI = 7 V
VO = 2.5 V
IO = 0 A to 2 A
100 µs/div
2.5 V OUTPUT VOLTAGELOAD TRANSIENT RESPONSE
20 mV/div
Figure 85
VI = 25 V
VO = 2.5 V
IO = 0 A to 2 A
100 µs/div
2.5 V OUTPUT VOLTAGELOAD TRANSIENT RESPONSE
20 mV/div
Figure 86
VI = 7 V
VO = 3.3 V
IO = 0 A to 4 A
100 µs/div
3.3 V OUTPUT VOLTAGELOAD TRANSIENT RESPONSE
50 mV/div
Figure 87
VI = 25 V
VO = 3.3 V
IO = 0 A to 4 A
100 µs/div
3.3 V OUTPUT VOLTAGELOAD TRANSIENT RESPONSE
50 mV/div
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
50 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 88
VI = 7 V
VO = 5 V
IO = 0 A to 5 A
100 µs/div
5 V OUTPUT VOLTAGELOAD TRANSIENT RESPONSE
50 mV/div
VI = 25 V
VO = 5 V
IO = 0 A to 5 A
100 µs/div
5 V OUTPUT VOLTAGELOAD TRANSIENT RESPONSE
50 mV/div
Figure 89
Table 4. Bill of Materials
REF. PN DESCRIPTION MFG. SIZE
C01 Open Capacitor, electrolytic, 330 µF, 35 V Sanyo 10x10 mm
C02 Standard Capacitor, ceramic, 2200 pF 805
C03 Standard Capacitor, ceramic, 0.01 µF 805
C04 Standard Capacitor, ceramic, 56 pF 805
C05 Standard Capacitor, ceramic, 0.1 µF 805
C06 Standard Capacitor, ceramic, 0.022 µF 805
C07 Standard Open 805
C08 Standard Capacitor, ceramic, 0.01 µF 805
C09 Standard Capacitor, ceramic, 2200 pF 805
C10 Standard Capacitor, ceramic, 1.0 µF 805
C11A 10TPB220M Capacitor, POSCAP, 220 µF, 10 V Sanyo 7.3x4.3 mm
C11B Open Open, Capacitor, POSCAP Sanyo 7.3x4.3 mm
C12 Standard Capacitor, ceramic, 0.1 µF 805
C13 TMK325BJ475MN–B Capacitor, ceramic, 4.7 µF 1210 (3225)
C14 Standard Capacitor, ceramic, 1.0 µF 805
C15A 6TPB150M Capacitor, POSCAP, 150 µF, 6.3 V Sanyo 7.3x4.3 mm
C15B 6TPB150M Capacitor, POSCAP, 150 µF, 6.3 V Sanyo 7.3x4.3 mm
C16A 10TPB220M Capacitor, POSCAP, 220 µF, 10 V Sanyo 7.3x4.3 mm
C16B Open Open, Capacitor, POSCAP Sanyo 7.3x4.3 mm
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
51POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 4. Bill of Materials (Continued)
REF. PN DESCRIPTION MFG. SIZE
C17 Standard Capacitor, ceramic, 1.0 µF 805
C18 Standard Capacitor, ceramic, 2200 pF 805
C19 Standard Capacitor, ceramic, 0.01 µF 805
C20 TMK432BJ106MN Capacitor, ceramic, 10 µF, 25 V, X5R Taiyo Yuden 1812 (432)
C21 TMK432BJ106MN Capacitor, ceramic, 10 µF, 25 V, X5R Taiyo Yuden 1812 (432)
C22 Standard Capacitor, ceramic, 0.01 µF 805
C23 Standard Open 805
C24 TMK432BJ106MN Capacitor, ceramic, 10 µF, 25 V, X5R Taiyo Yuden 1812 (432)
C25 TMK432BJ106MN Capacitor, ceramic, 10 µF, 25 V, X5R Taiyo Yuden 1812 (432)
C26 TMK432BJ106MN Capacitor, ceramic, 10 µF, 25 V, X5R Taiyo Yuden 1812 (432)
C27 Standard Capacitor, ceramic, 8200 pF 805
C28 Standard Capacitor, ceramic, 8200 pF 805
C29 Standard Capacitor, ceramic, 6800 pF 805
C30 Standard Capacitor, ceramic, 0.1 µF 805
C31 Standard Capacitor, ceramic, 0.1 µF 805
C32 Standard Capacitor, ceramic, 0.1 µF 805
D1 MBR0540T1 Diode, Schottky, 40 V, 500 mA Motorola 3.7x1.6 mm
D2 MBR0540T1 Diode, Schottky, 40 V, 500 mA Motorola 3.7x1.6 mm
D3 MBR0540T1 Diode, Schottky, 40 V, 500 mA Motorola 3.7x1.6 mm
D4 RB160L–40–TE25 Diode, Schottky, 40 V, 1 A Rohm 4.5x2.6 mm
D5 EC31QS04 Diode, Schottky, 40 V, 3 A Nihon Inter 5.0x2.5 mm
D6 EC31QS04 Diode, Schottky, 40 V, 3 A Nihon Inter 5.0x2.5 mm
D7 EC31QS04 Diode, Schottky, 40 V, 3 A Nihon Inter 5.0x2.5 mm
JP00~JP06 WL–8 Header, straight, 3–pin Mac8
JP8 WL–8 Header, straight, 3–pin Mac8
JP00~JP06 shunt JS–1 Jumper socket Mac8
JP8 shunt JS–1 Jumper socket Mac8
L1 CDRH127–100 Inductor, 10 µH, 5.4 A Sumida 12x12 mm
L2 CDRH127–6R1 Inductor, 6.1 µH, 6.6 A Sumida 12x12 mm
L3 CDRH125–100 Inductor, 10 µH, 4.0 A Sumida 12x12 mm
L4 CDRH5D28–220 Inductor, 22 µH, 0.9 A Sumida 5.7x5.7 mm
R01A Standard Resistor, 15 kΩ, 1% 805
R01B Standard Resistor, 18 kΩ, 1% 805
R02A Standard Resistor, 10 kΩ, 1% 805
R02B Standard Open 805
R03 Standard Resistor, 470 Ω, 5% 805
R04 Standard Resistor, 470 Ω, 5% 805
R05A Standard Resistor, 10 kΩ, 1% 805
R05B Standard Open 805
R06A Standard Resistor, 1.8 kΩ, 1% 805
R06B Standard Resistor, 10 kΩ, 1% 805
R07 Standard Resistor, 10 kΩ, 1% 805
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
52 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Table 4. Bill of Materials (Continued)
REF. PN DESCRIPTION MFG. SIZE
R08 Standard Resistor, 24 kΩ, 1% 805
R09 Standard Resistor, 18 kΩ, 1% 805
R10A Standard Resistor, 2 kΩ, 1% 805
R10B Standard Resistor, 16 kΩ, 1% 805
R11A Standard Resistor, 10 kΩ, 1% 805
R11B Standard Open 805
R12 Standard Resistor, 470 Ω, 5% 805
R13 Standard Resistor, 100 kΩ, 5 % 805
R14 Standard Open 805
R16 Standard Resistor, 100 kΩ, 5 % 805
R17 Standard Open 805
R19 Standard Resistor, 15 Ω, 5 % 805
R22 Standard Resistor, 15 Ω, 5 % 805
R24 Standard Resistor, 15 Ω, 5 % 805
R25 Standard Resistor, 220 Ω, 5 % 805
R26 Standard Resistor, 470 Ω, 5 % 805
R27 Standard Resistor, 100 Ω, 5 % 805
Q01~Q06 FDS6612A Transistor, MOSFET, N–ch, 30 V, 8.4 A, 26 mΩ Fairchild SO–8
U1 TPS5140 IC, Quad controller TI TQFP
Table 5. Vendor and Source Information
MATERIAL SOURCE PART NUMBER DISTRIBUTORS
MOSFETS (Q01 Q06)In EVM design FDS6612A (Fairchild) Local Distributor
MOSFETS (Q01– Q06)Second source IRF9410 (International Rectifier)
MAIN DIODES (D5 – D7) In EVM design EC31QS04 (Nihon Inter) 81–3–3342–5407
CERAMIC CAPACITORS(C20, C21, C24 , C25, C26)
In EVM designTMK432BJ106MN(Taiyo Yuden)
http://www.t–yuden.comhttp://www.yuden.co.jp
INDUCTORS (L1 – L4) In EVM design
CDRH125–100CDRH127–6R1CDRH127–100CDRH5D28–220(Sumida)
http://www.sumida.com
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
53POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
EVM Layout
Top Layer
Figure 90. EVM Top Layer
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
54 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
EVM Layout (continued)
2nd Layer
Figure 91. EVM Second Layer
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
55POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
EVM Layout (continued)
3rd Layer
Figure 92. EVM Third Layer
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
56 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
EVM Layout (continued)
Bottom Layer (Top View)
Figure 93. EVM Bottom Layer (Top View)
TPS5140FOUR-CHANNEL DC/DC CONTROLLER FOR NOTEBOOK PC POWER
SLVS305A – DECEMBER 2000 – REVISED JANUARY 2001
57POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATAPAG (S-PQFP-G64) PLASTIC QUAD FLATPACK
0,13 NOM
0,25
0,450,75
Seating Plane
0,05 MIN
4040282/C 11/96
Gage Plane
33
0,170,27
16
48
1
7,50 TYP
49
64
SQ
9,80
1,050,95
11,8012,20
1,20 MAX
10,20SQ
17
32
0,08
0,50 M0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Falls within JEDEC MS-026
PACKAGING INFORMATION
Orderable Device Status (1) PackageType
PackageDrawing
Pins PackageQty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS5140PAG ACTIVE TQFP PAG 64 160 Green (RoHS &no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
TPS5140PAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS &no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
TPS5140PAGR ACTIVE TQFP PAG 64 1500 Green (RoHS &no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
TPS5140PAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS &no Sb/Br)
CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please checkhttp://www.ti.com/productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die andpackage, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHScompatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flameretardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak soldertemperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it isprovided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to theaccuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to takereasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis onincoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limitedinformation may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TIto Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Oct-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1(mm)
W(mm)
Pin1Quadrant
TPS5140PAGR TQFP PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS5140PAGR TQFP PAG 64 1500 346.0 346.0 41.0
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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