Four Channel Portable Electronics

Rubén Conde*, Humberto Salazar*, Oscar Martínez* and L. Villaseñor **

* Facultad de Ciencias FisicoMatematicas, BUAP, Puebla  ** Institute of Physics and Mathematics, University of

Michoacan, Morelia

HAWC Collaboration Meeting

Guadalajara, Méx.Oct 11, 2010

This portable electronics contains A main board Nexys2 (http://www.digitleninc.com)

The Nexys-2 is a powerful digital system design platform built around a Xilinx Spartan 3E FPGA. With 16Mbytes of fast SDRAM and 16Mbytes of Flash ROM, the Nexys-2 is ideally suited to embedded processors like Xilinx's 32-bit RISC Microblaze™. The on-board high-speed USB2 port, together with a collection of I/O devices, data ports, and expansion connectors. A daughter board The daughter boad has 4 Channels – 100MSPS 10Bits ADCs dual AD9216 (http://www.analog.com )

The AD9216 is a dual, 3 V, 10-bit, 65/80/105 MSPS analog-to-digital converter. It features dual high performance sample and hold amplifiers and an integrated voltage reference. Input type is single ended and the DC offset of the input signal can be adjusted by means of a programmable 10Bits DAC

VCC3V3 1

VCC3V3 2

TMS 3

JTSEL 4

TDO 5

FX2-IO1 6

FX2-IO2 7

FX2-IO3 8

FX2-IO4 9

FX2-IO5 10

FX2-IO6 11

FX2-IO712

FX2-IO8 13

FX2-IO9 14

FX2-IO10 15

FX2-IO11 16

FX2-IO12 17

FX2-IO13 18

FX2-IO14 19

FX2-IO15 20

FX2-IO16 21

FX2-IO17 22

FX2-IO18 23

FX2-IO19 24

FX2-IO20 25

FX2-IO21 26

FX2-IO22 27

FX2-IO23 28

FX2-IO24 29

FX2-IO25 30

FX2-IO26 31

FX2-IO27 32

FX2-IO28 33

FX2-IO29 34

FX2-IO30 35

FX2-IO31 36

FX2-IO32 37

FX2-IO33 38

FX2-IO3439

FX2-IO35 40

FX2-IO36 41

FX2-IO37 42

FX2-IO38 43

FX2-IO39 44

FX2-IO40 45

GND 46

CLKOUT 47

GND 48

VCCFX 49

VCCFX 50

SHIELD 51

GND 52

TDO 53

TCK 54

GND 55

GND 56

GND 57

GND 58

GND 59

GND 60

GND 61

GND62

GND 63

GND 64

GND 65

GND 66

GND 67

GND 68

GND 69

GND 70

GND 71

GND 72

GND 73

GND 74

GND 75

GND 76

GND 77

GND 78

GND 79

GND 80

GND 81

GND 82

GND 83

GND 84

GND 85

GND 86

GND 87

GND 88

GND89

GND 90

GND 91

GND 92

GND 93

GND 94

GND 95

CLKIN 96

GND 97

CLKIO 98

VCCFX2 99

SHIELD 100

FX2-100

FX2-100

+5Vin

VDD

CLKA

CLKB

CLKC

CLKD

A0A1A2A3A4A5A6A7A8A9

B0B1B2B3B4B5B6B7B8B9

C0C1C2C3C4C5C6C7C8C9

D0D1D2D3D4D5D6D7D8D9

D0

A[0..9]

B[0..9]

C[0..9]

D[0..9]

CLKAA[0..9]

CLKBB[0..9]

DIN

SYNCSCLK

0AD9216_CONFIG.SchDoc

CLKB

CLKCD1

CLKAA[0..9]

CLKBB[0..9]

DIN

SYNCSCLK

1AD9216_CONFIG.SchDoc

CLKD

DIN0SCLK0SYNC0

DIN1SCLK1SYNC1

DIN1SCLK1SYNC1

DIN0SCLK0SYNC0

AVDD

1 2 3 4 5 6 7 8 9 10

PExt

Header 10

CL

KA

A2

A3

A4

A5

A6

A7

A8

A9

A1

Top Diagram(daughter board )

Block ADCChannel 1 and 2

Block ADCChannel 3 and 4

Con

nect

or

Hir

ose-

FX2

100P

To

Nex

ys2

Block ADC

AGND1

VIN+_A2

VIN-_A3

AGND4

AVDD5

REFT_A6

REFB_A7

VREF8

SENSE9

REFB_B10

REFT_B11

AVDD12

AGND13

VIN-_B14

VIN+B15

AGND16

AV

DD1

7

CL

K_

B18

DC

S1

9

DF

S2

0

PW

DN

_B

21

OE

B_

B22

23

23

24

24

25

25

26

26

D0

_B

(LS

B)

27

DR

GN

D28

DR

VD

D29

D1

_B

30

D2

_B

31

D3

_B

32

D4_B33

D5_B34

D6_B35

D7_B36

D8_B37

D9_B(MSB)38

3939

DRGND40

DRVDD41

4242

4343

4444

4545

D0_A46

D1_A47

D2_A48

D3

_A

49

D4

_A

50

D5

_A

51

DR

VD

D5

2D

RG

ND

53

D6

_A

54

D7

_A

55

D8

_A

56

D9

_A

(MS

B)

57

58

58

OE

B_

A5

9P

WR

D_

A6

0M

UX

_S

EL

61

SH

AR

ED

_A

62

CL

K_

A6

3A

VD

D6

4 AD9216AD9216

AGND

AGND

AGND

AGND

AVDD

VDD

DGND

DGND

DGND

VDD

VDD

0.1uFC0

AGND

0.1uFC1

AGND0.1uFC2 10uF

C3

AVDD

0.1uFC4

AGND

0.1uFC5

AGND0.1uFC6 10uF

C7

0.1uFC9 10uF

C8

AGNDAGND

AGND

AVDD100

A0100

A1100

A2100

A3100

A4100

A5100

A6100

A7100

A8100

A9

100

B0100

B1100

B2100

B3100

B4100

B5100

B6100

B7100

B8100

B9

A0B0B1B2B3B4B5B6B7B8B9

A0A1A2A3A4A5A6A7A8A9

B[0..9]

A[0..9]

CLKB

CLKAAVDD

1K

DC

S_

B

AVDD

AGND

1K

DF

S_

B

AGND

1K

PW

DN

_B AGND

AGND

1K

OE

B_

B1

KM

UX

AGND

1K

PW

DN

_A

AGND

AGND

1K

OE

B_

A

1K

SH

AR

ED

AGND

AVDD

A0

B[0..9]

A[0..9]

DF

SP

WD

N_

BO

EB

_B

SH

AR

ED

PW

RD

_A

OE

B_

A

0.1uF !AIN

25

!RINAGND

0.1uF !AINA

25

!RINAAGND

DAC +OUT

BAD9216_SingleEnd.SchDoc

DAC +OUT

AAD9216_SingleEnd.SchDoc

100pFCDAC1

VoutB

DIN1

49.9

SCL149.9

SYNC1

49.9

VDDVdd

1

GND2

!CS3

SCK4

DIN5

REF6

OUTA7

OUTB8

max7521_cd

MAX5721

VDD

VoutA

VoutA

VoutB

SYNCSCLK

DIN

AD9216-100MSPS Dual

Adder-Inverter A

Adder-Inverter B

Increase Offset for A and B

Adder-Inverter

+OUT

100

R3

5

1

234

PINA

COAX-M

5

67B

84

UAB

8002

50R7

619

R6

50

R11

100pFc0

10R8

10R9

+5V

-5V

619

R4

619

R5

100pFC2

100pF

c1

2

31

84

A

UAA

8002

50R2

619

R1

619

R0DAC

ConnectorLEMO

Top VIEW

Bottom VIEW

Hir

ose

FX

2-10

0

FPGA

JTAG

Serial Port

PCBdaughter

Applications

four independent channels until 100MSPSuse it like two channels of 200MSPS use it like a channel of 400MSPS

All this with control of independent level of offset in each channel

Conclusions DAQ System is in test phase

-4 Channels until 100MSPS -2Channels unttil 200 MSPS-1 Channel under 400 MSPSPrograms for measurements of rate, trace and fix the offset

has been developed.

GPS & Pressure sensor can be added.

Goal

Our proposal is to develop portable DAQ system reliable, low cost and low power consumption that allows to register parameters as the trace, rate and the charge for each signal, among others.