fpccd vertex detector 22 dec. 2006 y. sugimoto kek
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FPCCD Vertex detector
22 Dec. 2006
Y. Sugimoto
KEK
Vertex detector for ILC
Performance goal : Impact parameter resolution;
IP = 5 10/(psin3/2) m ( << c of D, )
This m.s. term is very challenging• Very thin wafer, beam pipe, support • Innermost layer as close to IP as possible High b.g. rate High pixel occupancy
Track density (/cm2/BX)
Vertex detector options If signals of one train (2820 bunches) are accumulated, too many
hits by beam b.g. for 25 m pixels, the pixel occupancy >10% for B=3T and R=20mm
Solutions; Fast readout : Example; Column Parallel CCD @50MHz, 20 frames/train
No time to wait for diffusion in epi-layer after particle incident Fully depleted CCD No diffusion Poor resolution Still smaller pixel size is necessary to recover the resolution Possible effect by RF noise by beam
Analog registers in each pixel (~20/pixel), and readout between trains CMOS: Flexible Active Pixel Sensor (FAPS) CCD: In-situ Storage Image Sensor (ISIS) Fine and complicated structure Large area OK?
Make pixel density x20Fine Pixel CCD (FPCCD)
Vertex detector options
Si Pixel
Readout between
trains
Readout duringtrain
Fine pixel(x20 more
pixels)
Standard pixel(x20 time slice
in 1 train)
Standard pixel(x20 time slice
in 1 train)
FPCCD
ISIS
FAPS
MAPS
CPCCD
DEPFET
SOI
GLD Vertex detector FPCCD vertex detector as the baseline design of GLD
Accumulate hit signals for one train (2840 BX) and read out between trains (200ms) Completely free from EMI
Fine pixel of ~5m (x20 more pixels than “standard” pixels) to keep low pixel occupancy Spatial resolution of ~1.5m even with digital readout
Fully depleted epitaxial layer to minimize the number of hit pixels due to charge spread by diffusion
Two layers in proximity make a doublet (super layer) to minimize the wrong-tracking probability due to multiple scattering
Three doublets (6 CCD layers) make the detector Tracking capability with single layer using hit cluster shape can hel
p background rejection Multi-port readout with moderate (~20MHz) speed (Very fast read
out (>50MHz) not necessary) Simpler structure than FAPS or ISIS Large area No heat source in the image area
Standard CCD Fine Pixel CCD
High Pt
Signal
Low Pt
b.g.
Z
B.G. rejection by hit cluster shape (tracking capability with single layer!)
Challenge of FPCCD Fully depleted Lorentz angle
tan=rHB, rH: Hall coefficient~1, : mobility (m2/Vs), B: Magnetic field (T)
Stronger E-field in dep. layer (>104V/cm = 1V/m) gives saturation of carrier velocity and smaller
Epi layer of ~15m would be OK Radiation tolerance Small pixel ( ~5 m) Fast readout speed ( ~20Mpix/
s ) Multi-port readout
H-Register in image area Low noise:
<50 e (total) < 30 e (CCD)
Low power consumption Metal layer Low drive pulse voltage Output circuit
Large area:10x65mm2( in) /20x100mm2( out)
Thinning( <50 m) Full well capacity
>104 e is OK Readout ASIC
Necessary for proto-type ladder
Lorentz angle
tan=rHB~B (:m2/Vs, B:T), =v/E
~0.1 m2/Vs
~0.07 m2/Vs
~0.14 m2/Vs
R&D for FPCCD Study of fully depleted CCD
Charge spread Lorentz angle Radiation damage
Development of FPCCD 3 rounds expected Prototype ladder in 5 years Collaboration with Hamamatsu
Minimization of material budget Wafer thinning FEA study of support structure
Development of readout ASIC
Supported by Gakujyutu Sousei
R&D Roadmap
2006 2007 2008 2009 2010
DCRDOD LOIConstruction
Study of fullyDepleted CCD
Design of small Prototype of FPCCD
FPCCD fabrication
Sample test Sample test Sample test
2nd round 3rd round (prototype ladder)
Development of readout ASIC for prototype CCD
Wafer thinning and the support structure
Other 2nd priority R&Ds
ILC Project (Detector)
DOD: Detector Outline DocumentDCR: Detector Concept ReportLOI: Letter of Intent (?)
FPCCD VTX
Short term plan Study of fully depleted CCD
New CCDs will be delivered mid December Epi-layer: 30m / 15m Pixel size: 24m
Study of charge spread and Lorentz angle Using green YAG LASER B-field up to 1T
Radiation tolerance Electron / neutron damage Dark current / charge transfer inefficiency
Study of support structure FEA study of Si-RVC-Si sandwich structure (RVC: Reticula
ted Vitreous Carbon)
Study of charge spread
Apparatus
CCD for reference(Front-illumination)
CCD for test(Back-illumination)
Charge spread
Front illumination Standard
Back illumination Deep2
Field simulation
NA=1.0, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0 x1013/cm3
Summary
We have started R&D of FPCCD for GLD vertex detector
Study of fully depleted CCD is on going in FY2006, and will be continued to FY2007
The 1st test sample of FPCCD is expected to be made by Hamamatsu in FY2007
We wish to construct and test prototype ladders of FPCCD by the end of Gakujyutu-Sousei project, but the budget (for r.o. ASIC and support structure) is not enough to complete that goal