fpga based fuzzy logic controller for semi- active suspensions aws abu-khudhair
TRANSCRIPT
FPGA Based Fuzzy Logic Controller for Semi-Active Suspensions
Aws Abu-Khudhair
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Outline
• Types of Suspension Systems• Project Objective
DSP and Reconfigurable Computing Systems
Aws Abu-Khudhair
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Outline
• What is DSP?...• Implementation of Various Algorithms…• Advantages of FPGA in DSP…• Tools available/Mapping DSP onto
FPGA…
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Resources
[1] “A Primer on FPGA-Based DSP Applications”, by Acromag Inc.
[2] “Designing Digital Signal Processing with FPGAs”, by Allen Kinast
[3] “FPGA Implementations of Fast Fourier Transforms for Real-Time Signal and Image Processing”, by I.S. Uzun, A. Amira and A. Bouridane
[4] “Choosing the Right Architecture for Real-Time Signal Processing Designs”, by Leon Adams.
[5] “Digital Signal Processors: Applications and Architectures”, by Kurt Keutzer
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What is DSP?
• Concerned with the manipulation of signals for:– Filtering– Transformation– Decoding/Encoding etc.
• Widely implemented in PDSP
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DSP Applications
• Wireless Communication• Audio Applications • Image Processing/Medical
Imaging• Networking• Weather forecasting
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Various Algorithms
• Finite Impulse Response (FIR) filters
• Fast Fourier Transforms (FFT)
• Infinite Impulse Response (IIR) filters• Forward Error Correction (FEC)• Modulation/Demodulation
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DSP Implementation Comparison
Technology Performance Cost Power Flexibility Design Effort
GPP Low Low Medium High Low
PDSP Medium Medium Medium Medium Medium
FPGA Med-High Medium Low-Med High Medium
ASIC High High Low Low High
Most suitable technology??
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PDSP vs. FPGA
• PDSP– Specialized microprocessor based on the
Von Neumann arch.– Programmed in C/assembly for performance– Suited for complex math-intensive tasks, with
conditional processing.– Limited in performance by the clock rate and
number of operations it can perform per clock cycle.
• e.g. TMS320C6201 has 2 multipliers + 200MHz clock 400M multipliers/second
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PDSP vs. FPGA cont.
• FPGA– Uncommitted gates– Programmed by HDL. – Performance limited by the number of gates
and clock rate.– Suited for a wide range of applications
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Advantages/Disadvantages of FPGA
• Advantages– Parallel Processing (Performance)– Flexible Architecture– Price– Power Demand compared to DSP
• Disadvantages– Higher development cost and increased time
to market than DSP– Implementation of conditional processing
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Important Building Blocks
• Add• Subtract• Multiply• Multiply and Add• Multiply and Accumulate (MAC) Unit
Data Out
Reg
MAC unitCoefficient
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256 Tap FIR Filter
256 Loops needed to process samples1 FIR tap per DSP instruction cycle
Conventional DSP – Serial processing
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256 Tap FIR Filter cont.
All 256 MAC operations in 1 clock cycle
FPGA – Parallel processing
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FPGA Design Flexibility
FPGA – Design Optimization
×
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+×
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D Q ××
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D Q
Parallel Semi-Parallel Serial
Speed Cost
Q = (A x B) + (C x D) + (E x F) + (G x H)
Multiply and Add
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Performance of PDSP VS. FPGA
FeatureConventional
PDSP Virtex –II
Virtex –II pro
Spartan-3
8 x 8 Multiply Accumulate (MAC)
5.7 billion MAC/s0.5 Tera MAC/s
1 Tera MAC/s
0.27 Tera MAC/s
FIR Filter
- 256 taps, linear
phase
- 16-bit
data/coefficients
11.16 MSPS
720 MHz
180 MSPS
180 MHz
300 MSPS
300 MHz
140 MSPS
140 MHz
Complex FFT
- 1024 point, 16-bit
data
8.5 s
720 MHz
0.914 s
140 MHz
0.853 s
150 MHz
0.914 s
140 MHz
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Advanced FPGA Architectures with DSP Resources
Features Virtex-4 Startix II ECP-DSP
Clock Management
DCM – up to 20
PLL – up to 12sysCLOCK
PLL – up to 4
Embedded Memory
BlockRAM up to 10 Mb
TriMatrix memory up to
9 Mb
sysMEM blocks up to 498 Kb
Data Processing
Up to 200K CLBs & 512 XtremeDSP
Slices
Up to 179K LEs, 384
Embedded multipliers & 96
DSP blocks
Up to 4096 PFUs, 32 multiplier
blocks & 8 DSP blocks
Clock Speed Up to 500 MHz Up to 500 MHz Up to 250 MHz
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DSP Design tools
• C, C++• MATLAB / Simulink• HDL (VHDL / Verilog)• Xilinx EDK/ISE
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MATLAB / Simulink
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Simulink
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Simulink + ISE
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Design flow with FPGA
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DSP Design Evolution from HW DSP to FPGA DSP solutions
1. Signal capture and sync.2. Data exchange methodology3. off-the shelf hardware4. Logic Processing5. Price/Feature6. Data/Sample rates7. Debugging8. Use of IP cores9. I/O interface10. Development cycles11. Deployment cost
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Conclusion
• “The primary reason solutions were so expensive to design, slow to develop and prove, and difficult to re-deploy was that the solutions were fixed in hardware” [1]
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Questions?
• Thank you