fpga-based system design: chapter 5 copyright 2004 prentice hall ptr topics n basics of sequential...
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Topics
Basics of sequential machines. Sequential machine specification. Sequential machine design processes.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Sequential machines
Use registers to make primary output values depend on state + primary inputs.
Varieties:– Mealy—outputs function of present state,
inputs;– Moore—outputs depend only on state.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
FSM structure
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Constraints on structure
No combinational cycles. All components must have bounded delay.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Synchronous design
Controlled by clock(s).– State changes at time determined by the clock.
– Inputs to registers settle in time for state change.
– Primary inputs settle in time for combinational delay through logic.
Machine state is determined solely by registers.– Don’t have to worry about timing constraints, events
outside the registers.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Non-functional requirements and optimization
Performance:– Clock period is determined by combinational logic
delay.
Area:– Combinational logic size usually dominates area.
Energy/power:– Often dominated by combinational logic.
– May be improved by latching values.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Models of state machines
Register-transfer:– Combinational equations for inputs to registers.
State transition graph/table:– Next-state, output functions described
piecewise.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
State transition graph
Each transition describes part of the next-state, output functions:
S1
S2
S3
0/010
1/1-0
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Register-transfer structure
Registers fed by combinational logic:
Combinationallogic
D Q
D Q
D Q
D Q
D Q
D Q
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Block diagram
Purely structural description:
B1A
B2
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Symbolic values
A sequential machine description may use symbolic, not binary values.– Symbolic values must be encoded during
implementation.
Encoding may optimize implementation characteristics:– Area.
– Performance.
– Energy.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
STG vs. register-transfer
Each representation is easier for some types of machines.
Example: counter.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Counter state transition graph
Cyclic structure:
01/1
11/2
61/7
7
1/0
…
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Counter register-transfer function
Specify using addition:– Next_count = count + 1.
Regular structure of logic.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Example: 01 string recognizer
Recognize 01 sequence in input string:
recognizer
0
0
1
1
0
1
0
0
1
0
0
1
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Recognizer state transition graph
Bit 1 Bit 20/0
1/1
1/0 0/0
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Mealy vs. Moore machine
Moore machine:– Output a function of state.
Mealy machine:– Output a function of primary inputs + state.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Sequential machine definition
Machine computes next state N, primary outputs O from current state S, primary inputs I.
Next-state function:– N = (I,S).
Output function (Mealy):– O = (I,S).
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Reachability
State is reachable if there is a path from given state.
May be created by state encoding:
s0 s1
s2 s3
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Homing sequence
Sequence of inputs that drives the machine to a given state.
s0 s1
s2
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Equivalent states
States are equivalent if they cannot be distinguished by any input sequence:
s1 s2
s3 s4
0/0
-/0-/1
-/0
1/0
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Networks of FSMs
Functions can be built up from interconnected FSMs:
M1 M2
x
y
I1
O1
I2
O2
External connectionsInternal connections
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Illegal composition of Mealy machines
Com
bina
tion
allo
gic
DQ
Com
binationallogic
DQ
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Communicating FSM states
s1
s2
M1
0/0
1/0-/1
s3
s4
M2
0/0
-/01/1
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Product machine
Two connected machines:
R Si1 o1 i2 o2
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Component STGs
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Behavior of connected machines
R Si1 o1 i2 o2
R1 S10 0 1
R2 S20 1 0
R3 S10 0 0
R3 S10 0 0
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Forming product machine
Form Cartestian product of states:– R1S1, R1S2, R2S1, R2S2, R3S1, R3S2.
For each product state, determine the combined behavior of each product transition:– Required inputs.– Produced output.– Next product state.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
State assignment
Find a binary code for symbolic values in machine.– Optimize area, performance.– May be done on inputs, outputs as well.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Optimizing state assignments
Codes affect the next-state, output logic.– Compute conditions based on state.
Best code depends on the input, output logic and its interaction with state computations.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Encoding a shift register
Symbolic state transition table for shift register:
0 S00 S00 0
1 S00 S10 0
0 S01 S00 1
1 S01 S10 1
0 S10 S01 0
1 S10 S11 0
0 S11 S01 1
1 S11 S11 1
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Bad encoding
Let S00 = 00, S01 = 01, S10 = 10, S11 = 10.
Logic:– Output = S1 S0’ + S1’ S0– N1 = I– N0 = I S1’ + I S1
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Good encoding
Let S00 = 00, S01 = 01, S10 = 10, S11 = 11.
Logic:– Output = S0– N1 = I– N0 = S1
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
One-hot code
N-state machine has n-bit encoding. Ith bit is 1 if machine is in state i. Comparison:
– Easy to tell what state the machine is in.– Easy to get the machine into an illegal state
(0000, 1111, etc.).– Uses a lot of registers.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
Common factors in state coding
Consider this set of transitions:– 0, s1 OR s2 -> s3, 1
Want to choose a code that easily produces s1 OR s2.– S1 = 00, S2 = 01.
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
State codes in n-space
0
s1 code = 111
s2 code = 110
1
1
1
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FPGA-Based System Design: Chapter 5 Copyright 2004 Prentice Hall PTR
State codes and delay