fpga-based weblab infrastructures guidelines and a prototype implementation example
DESCRIPTION
FPGA-based Weblab Infrastructures Guidelines and a prototype implementation example. Authors : Ricardo Costa ( ISEP/CIETI/LABORIS ) ( [email protected] / http://www.laboris.isep.ipp.pt/rjc ) and Gustavo Alves ( ISEP/CIETI/LABORIS ), Mário Zenha-Rela ( FCTUC/CISUC ), - PowerPoint PPT PresentationTRANSCRIPT
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FPGA-based Weblab InfrastructuresGuidelines and a prototype implementation example
Authors:Ricardo Costa (ISEP/CIETI/LABORIS)([email protected] / http://www.laboris.isep.ipp.pt/rjc )
andGustavo Alves (ISEP/CIETI/LABORIS),Mário Zenha-Rela (FCTUC/CISUC),Rob Poley (Heriot-Watt University),Campbell Wishart (Heriot-Watt University)
ICELIE'2009Porto, 3-5
November 2009
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2/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Presentation outline
Introduction
Architectural considerations
Remote access
Implemented prototype
Conclusions and future work
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3/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Introduction
- More labs required for practical work at campus and after classes
status
allow students to interact with real equipments from everywhere at anytime without physically being present in a classical lab
Create more labsProvide access to real experiments through the web
Solutions
Cost !
several hardware and software architectures
i) - only qualified people are able to develop them;ii) - the adopted instruments and modules (I&M) may be expensive with many features not required;iii) - reusing and interface I&M is not simple
problems
feature
use a reconfigurable hardware infrastructure with I&M able to share
solution
+ Flexibility/Reuse of I&M - Price+ Collaboration
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4/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Architectural considerations I
Servidor
Instrumentation Bus
Lab Server
Ethernet
Database
InstrumentRobots
Experiment
InstrumentInstrumentInstrumentation Server
Web Lab infrastructure
usersWEB
Web Interfacesto remotely control a specific
experiment
Pedagogical ContentsAccess Management
Control / Monitorization
Proposal: use FPGA-based
Boards
Typical Weblab architecture:
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5/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Architectural considerations II
Benefits of using FPGAs for replacing the instruments and the instrumentation server:
• costs will be reduced;
• reconfiguration capabilities allow implementing different measurement instruments;
• and provides modularity and flexibility in the construction of weblab infrastructures.
Internet FPGA UUT
usersConceptual weblab architecture
using an FPGA
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6/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Architectural considerations III
FPGA
DedicatedController
Osc
illo
scop
e
Multimeter
FPGAs
Function Generator
UUT
MultimeterF
unct
ion
Gen
erat
or
FPGA
UUT
a) one single FPGA accommodating several modules/instruments
b) one FPGA for each module/instrument
Two solutions for using FPGAs for implementing a Weblab infrastructure:
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7/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Remote access I
Instruments/modules files
Internetweblab
infrastructure
web serverweb server
mainweb interface
web interfaces for each instrument/module
mobile phones, PDAs, smart phones
or PCsE
ther
net
PHY
Generic architecture:
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8/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Remote access II
InternetMicroWeb
Server
Digital I/O
JTAGUUT
Analog
Digitalmodules/instrumentsE
ther
net
PH
Y
I/O
I/O I/O
FPGA-based board D
/A
A/D
Suggested architectures for the Weblab infrastructures:
Internet
D/A
A
/D
modules/instruments
I/O
FPGA-based board
TC
P/IP
CO
RE
UUT
Analog
Digital
Eth
erne
tP
HY
Hybrid approach
SoC approach
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9/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Hybrid approach
SoC approach
Some solutions available in the market:
Remote access III
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10/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Spartan-3E starter kit - XILINXA/D and D/A
Ethernet port I/O portsLCD
display
Lantronix module (MicroWebserver)
I/O ports
Ethernet port
Adopted devices:
Implemented prototype I
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11/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Imp
lem
en
ted
we
bla
b in
fra
str
uc
ture
Implemented prototype II
Function generator
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12/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Physical interfaces used to control the function generator
Control / monitor web interfaces for
controlling / monitoring the function generator
Developed through a collaboration agreement between CIETI/Laboris and an M.Sc. Student from Heriot-
Watt University (Scotland)
Implemented prototype III
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13/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Conclusions
Adopting this architecture will:
- simplify the creation of Weblab infrastructures;
- allow sharing and reusing instruments and modules;
- increase collaboration;
- reduce costs.
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14/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Some difficulties appeared during the collaboration because…
Difficulties to understand/explainall details…
It would be difficult to use the FG on another Weblab infrastructure,
based on the presented architecture…
It was necessary to specify a logical interface !
It defines a set of open, common, network-independent communication interfaces for connecting transducers, will facilitate the implementation and sharing of different instruments/modules, in a compatible weblab infrastructure.
Future work
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Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
THANKS FOR YOUR ATTENTION
Ricardo Costae-mail: [email protected]
webpage: http://www.laboris.isep.ipp.pt/rjc
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16/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Benefits of using FPGAs for replacing the instruments and the instrumentation Server:
•costs will be reduced;
•reconfiguration capabilities allow implementing different measurement instruments;
•and provides modularity and flexibility in the construction of weblab infrastructures.
Internet FPGA UUT
users
Conceptual weblab architecture using an FPGA
But…other solution could be the adoption of μps / μcs !!!
Architectural considerations – extra
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17/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Architectural considerations – extra
Why adopting FPGA
instead of μps / μcs ?
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18/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
FGPA reconfiguration options(Total or Partial Static or Partial Dynamic ?):
Architectural considerations – extra
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19/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
Static-Partial-ReconfigurationSpartan-3E
Dynamic-Partial-ReconfigurationVirtex5
Example of two FPGA-based Boards solutions from Xilinx:
Architectural considerations – extra
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20/15
Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
IEEE 1451.0 Std.
IEEE Standard for a Smart Transducer Interface for Sensors and Actuators—Common Functions, Communication Protocols, and Transducer Electronic Data Sheet (TEDS) Formats(IEEE Std 1451.0™-2007) - It is the basis to interoperate all members of the IEEE 1451 family enabling the control of trigger and status signals, the operation modes definitions, etc.
- all transducers must implement a TIM (transducer interface module) - the Std. defines all functions performed by TIMs;
- all transducers are specified by a TEDS (Transducer Electronic Data Sheets) - the Std. defines all functions to read/write form/to the TEDS;
- Provides a set of Application programming interfaces (APIs) to facilitatecommunications with the TIM and with other applications through a NCAP (Network Capable Application Processor).
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Ricardo Costa - ICELIE’09 - November [email protected] - http://www.laboris.isep.ipp.pt/rjc
FPGA-based Weblab Infrastructures
IEEE 1451.0 Std.