fpga implementation of denoising in ofdm systems using dsp design module
DESCRIPTION
FPGA Implementation of Denoising in OFDM Systems using DSP Design Module. Prof. Brian L. Evans PhD Students Jing Lin, Yousof Mortazavi , Marcel Nassar & Karl Nieman Wireless Networking and Communications Group Department of Electrical and Computer Engineering - PowerPoint PPT PresentationTRANSCRIPT
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FPGA Implementation of Denoising in OFDM Systems using DSP Design Module
Prof. Brian L. EvansPhD Students
Jing Lin, Yousof Mortazavi, Marcel Nassar & Karl NiemanWireless Networking and Communications Group
Department of Electrical and Computer EngineeringCockrell School of Engineering
The University of Texas at Austin
May 10, 2012
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Outline
Part I• Algorithm Description• Project Goals• System Design and ImplementationPart II• DemonstrationPart III• Conclusions and Discussion
2Outline | Background | System Design and Implementation | Conclusions
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Impulsive Noise in Communication Systems
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3.25 3.3 3.35 3.4 3.45 3.5 3.55 3.6x 10
6
-200
-100
0
100
200
samples Index
Vol
tage
Lev
el
Wireless CommunicationSources
Uncoordinated transmission
Computational PlatformClocks, buses and processorsOther embedded transmitters
Antennas
Baseband Processor
Non-CommunicationSources
Electromagnetic radiation
Outline | Background | System Design and Implementation | Conclusions
Noise Measurement
BackgroundNoise
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Impulsive Noise in OFDM Systems
• FFT spreads received impulsive noise across all FFT bins
• SNR of each FFT bin is decreased• Receiver communication performance degrades
IFFT Filter + FFTEqualizer
and detectorVector
of symbolamplitudes(complex)
Outline | Background | System Design and Implementation | Conclusions
Channel
Receiverx y
Gaussian (g) + ImpulsiveNoise (e)
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Impulsive Noise Mitigation (Denoising)
• N FFT bins (tones)• Transmitter null tones have zero power• Received null tones contain noise
• Impulsive noise estimation• Exploit sparse structure of null tones• FJ is over complete dictionary• e is sparse vector• g is complex Gaussian (g = F w)
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IFFT Filter + + FFTEqualizer
and detectorImpulsive
noise estimation
Gaussian (w) + ImpulsiveNoise (e)
Vectorof symbolamplitudes(complex)
+-
Channel
Receiver
J is set of null tones (i.e. xj = 0)F is N x N FFT matrix
x y
|J| x N
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Sparse Bayesian Learning (SBL)Step 1: Maximum likelihood estimate of hyper-parameters
Step 2: Estimate e from posterior mean:
Matrix MultiplyMatrix Inverse
Norm
Outline | Background | System Design and Implementation | Conclusions
-10 -5 0 5 1010
-5
10-4
10-3
10-2
10-1
SNR (dB)
Sym
bol E
rror R
ate
No cancellationSBL w/ null tonesSBL w/ all tones
~10dB~6dB
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Project GoalsFrom theory to implementation:• understand computational requirements• determine real-time constraints in target application• find feasible solution
Steps involved:• develop floating-point model and simulator• fixed-point transformation• hardware/software partitioning• implementation
7Outline | Background | System Design and Implementation | Conclusions
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Chassis
NI Flex RIO(NI PXIe-7965R)SBL
Hardware
FPGA (hardware)
RT Host (software)
SBLSoftware
SimulatorNI Embedded Controller
(NI PXIe-8133)
NI PXIe Chassis(NI PXIe-1082)
System Design and Implementation Using NI Products
NI LabVIEW RT
NI LabVIEW FPGADSP Design Module
Outline | Background | System Design and Implementation | Conclusions
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SBLHardware
SBLSoftware
Current Hardware/Software Partitioning
Outline | Background | System Design and Implementation | Conclusions
SBL Software
SBL Hardware
N = 128M = 32
(diagonal)
scalar
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Computational Requirements for Powerline Communications
Major operations• N-point fast Fourier transform (N=128)• vector dot product (length 32, 128)• matrix-vector multiplication (32x128) x (128x1) • matrix-matrix multiplication (128x32) x (32x128)• matrix inversion (32x32)• multiple iterations per symbol (30 or more)
Real-time requirementprocessing time < OFDM symbol duration (231.7- 2240 µs)
Outline | Background | System Design and Implementation | Conclusions
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FPGA hardware design using NI DSP Design ModuleDSP Diagram implements • FFT (N=128)• accumulators, adders, subtracters, multipliers• vector scaling (element-by-element)• 2-norm calculation (squaring + accumulating)
Outline | Background | System Design and Implementation | Conclusions
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Fixed Point Transformation
Outline | Background | System Design and Implementation | Conclusions
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Fixed Point Model of Computations in FPGA
Outline | Background | System Design and Implementation | Conclusions
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Designing Wordlengths• MATLAB
• Displays statistics • Allows analysis of bit allocation• Graphical control• Automatic Settings
• LabVIEW• Used max/min (absolute value) to understand range at each node• Saturation indicators • Tedious manual process• Better to iterate in LabVIEW RT than on FPGA
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Compile Results
FPGA hardware implementation can exploit parallelism by using more adders and multipliers!
Parallelism and pipelining can increase the maximum frequency.
15Outline | Background | System Design and Implementation | Conclusions
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Advantages of NI DSP Design Module
FPGA implementation is greatly simplified!Good level of abstraction to focus on algorithm development and increase productivity, rather than worry about:• clock domains• FIFOs and sizing• handshaking (e.g. data valid, ready for input, output ready, etc.)• DMA transfers between FPGA and host• etc.
Can do a lot with very little/no LabVIEW FPGA coding
Automatic test bench generation also very useful!
16Outline | Background | System Design and Implementation | Conclusions
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More advanced use of NI DSP Design Module
Matrix operations are not currently supported
May create custom “DSP Blocks” to load in DSP Diagram
Custom (high performance) blocks are coded in LabVIEW FPGA at a lower abstraction (requires more experience)
Implemented a 32x32 matrix-matrix complex multiply using 128 (out of 640) hardware multipliers on Virtex-5 SX95T FPGA
17Outline | Background | System Design and Implementation | Conclusions
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Example 32 Element Vector Dot Product
Can make high performance blocks, with a little wiring!
18Outline | Background | System Design and Implementation | Conclusions
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Example 32x32 Matrix Matrix Multiply
19Outline | Background | System Design and Implementation | Conclusions
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LabVIEW FPGA IP Builder• Fortunately, a new NI product called IP Builder can
simplify custom hardware design using more “software-like” structures
Outline | Background | System Design and Implementation | Conclusions
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DEMO
Outline | Background | System Design and Implementation | Conclusions
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Future Work at UTImplement more blocks in hardware
• Use IP Builder for matrix operations• QR decomposition in FPGA• Inversion with QR
Develop sequential version of algorithm with hardware implementation in mind
Use ADC/DAC and physical channel instead of simulator
Outline | Background | System Design and Implementation | Conclusions
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Thank you for your attention!
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