FPGA IMPLEMENTATION OF TRAPEZIODAL FILTERS

MID PRESENTATIONInstructor: Evgeniy Kuksin

Preformed by: Ziv LandesbergDuration: 1 semester

Project goal from presentation Create a FIR filter that can process pulses

from photon counting detectors and perform Peak Detection using NI Labview FPGA.

Progress so far Plan and build trapeziodal shaper in

Labview Create the trapeziodal shaper on the

FPGA and test it at low clock rate Test the system at high clock rate

(150MHz) , still on computer

Future stages Test the filter on signal recived from

analog signal generator Implement the pulse detector

System description

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Photons

ADC Shaper

PeakDetecto

r

FPGA

ReadoutTo PC

Project Block Diagram

FPGA(150MHz)

A\DNI 5761

14 bit 150 MHz Signal

generator(Preamplifier emulator)

Reasons to use Trapeziodal shaper over other shapers

Trapezoidal can achive optimal noise performance from signal. Trapezoidal Shaper, unlike many analog pulse shaper, immune to “ballistic deficit”, that causes energy distortion in the spectrum.

Coefficients calculation The Coefficients were calculated by the

method at the article of “On nuclear spectrometry pulses digital shaping and processing” , the biexponential pulse part.the method is to inverse the transfer function of the pulse(making it a digital delta) , and then convolute the delta with a trapezoid. Due to the fect that both the inverse function of the pulse and the trapezoid were finite length , the resulted filter was FIR.

The signal generation The input signal was generated at 2 main

stages : 1) create an array with Poisson distributed

digital delta’s in it. It was done by the Poisson noise generator, that each event was transformed to delta, and each none event was transformed to zero.

2 ) transfer the deltas to linear rising- exponential decaying pulse, was done simply by convoluting the array with the response of such pulse(with cut-off values lower than exp(-10 ))

Build filterThe building of the filter in Labview was done using the fir template already existing in the program .

So first stage was to create a fds file to generate filter from.The second stage was to use the automatic filter generation .

The code of previous slide

The generation window

Synthesis result

Device resources

Sucessful results at 150MHz(no noise)

Successful result with noise

Trapezoid in time(no noise, but with quantization effect)

Trapezoid in time(with noise)

System on FPGA

Project requirements (unchanged)

FPGA that can be programmed using LABVIEW

Analog signal generator A\D convertor

Estimated time lines3.Show filter performance at high sample rate.4.Build the pulse detector

31 June

15 June

31 may

15 may

30 April

15 April

31 march

15 march

Estimated dateStage 3Stage 4

Yellow- partially doneRed- need to be done