fpga lesson 3 (host interface)
DESCRIPTION
fpga host interfaceTRANSCRIPT
LabVIEW FPGA and the PXI-7831R Training
Lesson 3Host Interface, Interrupts, FPGA\Host
Synchronization
Chad EvansApplications Engineer
• Used to control and communicate with the FPGA VI from RT or Windows
• Either on RT or Windows, depending on the final Run-Time configuration
Host Interface VI
LabVIEW FPGA Host Functions
• Built on top of VISA (Virtual Instrument Software Architecture)
RIO Host Interface Palette
Open VI Reference
Close VI Reference
Read/Write Control
Invoke Method
Open VI Reference• Edit Time
– Selected Target VI (FPGA VI) used to determine available controls
– Selected VI becomes a hidden subVI of the Open VI Reference
– Uses RIO board 0 by default• Run Time
– Downloads the selected VI (bit file) to FPGA unless already downloaded
– Returns a reference
External VISA Input
• Allows user to programmatically select board
• Useful for built applications
Board Selection (Relative)1. Select FPGA menu item2. Select Board
Close VI Reference
Aborts the VI on the FPGA
Leaves the FPGA VI running
Read/Write Control (Edit Time)
*
Read/Write Control (Run Time)
• The controls (or indicators) are written (or read) in the order they appear in the Read/Write Control
• Reads and Writes are double buffered• Complex data, such as arrays and clusters are supported
Exercise 3.1
• To create a Host Interface VI (to run on the RT PXI Controller) for the VI created in Exercise 2.1 (Digital I/O VI).
• Run• Download (Force Download reinitializes)• Wait on IRQ
• Acknowledge IRQ• Abort
Invoke Method
Wait on IRQ
• Only one should be called at a time• IRQ Number(s) – Will accept an array of IRQ numbers• Timeout – milliseconds, -1 to never timeout• Timed Out – returns true for Timeout, false for interrupt• IRQ(s) Asserted – returns array of all IRQ’s asserted
.
..
0
31M
ASK ...
IRQ Line
Written by this VI
Acknowledge IRQ
• Clears logical interrupts specified by IRQ Number(s)
RIO/Host Synchronization
Host
FPGA
Polling
• Depending on the application, polling may be a better solution than using interrupts.
How do I know if the host is fast enough?
• Ideas for checking that the host is keeping up– See examples
• C:\Program Files\National Instruments\LabVIEW 7.0\examples\FPGA\Host Synchronization
– Compare Loop Timer times– Use handshaking through controls/indicators
• Read an iteration indicator with each read to verify that only one iteration transpired.
– Be clever, build your own!
Exercise 3.2
• To create a Host VI for the FPGA VI created in Exercise 2.2 (Timed AI/AO with Interrupts).
Lesson 3 Summary
• FPGA Interface is what controls and communicates with the FPGA VI
• Use Interrupts for synchronizing FPGA VI and Host VI