fpga manager - enclustra€¦ · software-defined radio smart vision systems motion & drive...

FPGA Manager Streaming made simple

Streaming, made simple.

Enclustra GmbH

Agenda

Enclustra company profile

Reasons for linking a FPGA to a high level language Applications

Types of interaction

Requirements when linking a FPGA to a high level language

Challenges when linking a FPGA to a high level language

Why a standard solution makes perfect sense

FPGA Manager overview

FPGA Manager solutions

FPGA Manager software API

04.04.2017 - 2 -

Enclustra GmbH

Enclustra company profile FPGA Design Center

FPGA System Design Hardware (High-Speed, Analog, RF)

HDL firmware (VHDL, Verilog)

Embedded software (FPGA bezogen)

Focus Areas Embedded Processing

Test & Measurement

Software-defined Radio

Smart Vision systems

Motion & Drive control

Experience ~100 person-years of FPGA hardware, firmware & software design

>50 customers, >200 projects

- 3 - July 23, 2014

Enclustra GmbH

Enclustra company profile FPGA Solution Center

FPGA and SoC modules Mars Familie (MX1, MX2, AX3, ZX3, …) SO-DIMM 67.6 x 30 mm,

Mercury Familie (KX1, CA1, ZX1, ZX5, SA1, …) 56 x 54 bis 72 x 54 mm,

IP Cores and solutions Universal Display Controller IP Core Profinet IP Core Universal Drive Controller IP Core UDP/IP Ethernet IP Core FPGA Manager Solution

- 4 - July 23, 2014

Enclustra GmbH 04.04.2017 - 5 -

Reasons for linking an FPGA to a high level language

Data preprocessing is done in the FPGA, data presentation is done in software

Configuration of the FPGA by the user

User interface is normaly done in software GUIs in high level languages C#/.NET, C++, Java etc

Embedded applications often in C

User interface is normaly runs on a PC

Hardware accelerated software

Distributed systems


Reasons for linking a FPGA to a high level language

Use case 1: Camera with edge detection Data preprocessing in the FPGA becasue of high resolution and very high refresh rate

Display of the preprocessed picture on a PC Data stream from the FPGA to the PC

GUI in C#

PC is remotly connected to the FPGA



Use case 2: Configuration and status monitoring of a drive controller Drive controller in the FPGA for high control loop rates

Configuration of the motion vectors from a PC Write register access of the PC to the FPGA

Status monitoring from a PC

Read register access of the PC to the FPGA

Sending of alarms/events from the drive control to the user Signaling from the FPGA to the PC

Application in C++

PC is remotly connected to the FPGA



Use case 3: Hardware accelerated software Encryption of network traffic in realtime

Encryption of the network traffic by the FPGA Data stream from the PC to the FPGA

Sending of encrypted data by the PC Data stream from the FPGA to the PC

Small application in C, asynchronous transfers

PC and FPGA are one system

FPGA

HostInterface EncryptionStream Stream

HostInterface

Encryption Application

Stream

PC

Stream

Ethernet



Three types of interaction Data stream between FPGA and PC Typically used for data preparation (FPGA to PC) or data processing (PC to FPGA) Data

Stream

Register access on the FPGA by the PC Typically used for writing configuration data or polling status

Memory Mapped

Event signaling from the FPGA to the PC Typically Interrupts (Completion, Errors, etc.)

Signaling


Requirements when linking a FPGA to a high level language (1)

All three types of interaction shall be supported Data Streams Frame Streams, Byte Streams

Appending Metadata to data streams (e.g. Timestamps)

Memory Mapped Read, Write, Read-Modify-Write

Single Access, Burst

Signaling Interrupts

Edge, Level

Priorities



Diversity Multiple different links and bandwidths PCIe Gen1/2/…, USB 2.0/3.0/…, ETH100/1000Mbps/…

Multiple FPGA vendors, CPU architectures, OS and FPGA boards Altera, Xilinx, ... & X86, ARM, ... & Windows, Linux ....

Multiple programming languages C#/.NET, C/C++, Matlab, Java etc.

Uniformity Same API for all links, FPGAs and boards

Same API for different OS

«Same» API for different programming languages (functional identical and where possible also syntactic)

Same interface for the user logic in the FPGA for all links, FPGAs and boards

Use of standardized interface for user logic in the FPGA



Multiplexing Multiple connecting channels over one physical link z.B. 3 Data Stream channels, 2 Memory Mapped channels, 2 Signaling channels over the same

USB 3.0 link

Simultaneous access of multiple applications to different channels

Performance Bandwidth (MB/s)

Latency (s)

CPU load (%)

Flow control

Error Handling Recovery from Non-Fatal-Errors

Fatal-Error handling



Blocking and Nonblocking Support for synchronous und asynchronous transfers

Enumeration Discovery of your devices

Linking to a FPGA shall be simpel for the user!!! The user shall be able to concentrate on his actual task, linking to the FPGA mostly is just a

means to an end.


Challenges when linking a FPGA to a high level language (1)

Diversity vs. Uniformity Unified interfaces over all dimensions (Links, FPGA vendors, CPU architectures,

operating systems and programming languages)

Performance vs. Ressources To achive maximum performance normally more resources are needed

correspondingly

Simplicity vs. Flexibility How simple shall an API be to still give maximum flexibility?



Simplicity vs. Complexity How complex shall the error handling and protocols be to achive maximum stability

with minimum complexity?

Bandwidth vs. Latency vs. Throughput For maximum bandwidth large data packets are optimal, for low latency small

packets are optimal and for maximum throughput as many operations as possible shall be put into one packet.

Compability between Software and Firmware Same version, same generation

backward compatibility



Modularity/maintainability vs. Optimization How much can you optimize before loosing maintability and modularity?

Safety und Security Authentification, encryption of data required?

Mutual influence of the various data streams

Enumeration How do I find my device?

Which of my devices is it?

Bringing all these paradigms under one hat!


Why a standard solution makes perfect sense

All those challenges – and the only thing we want to do is communicating with an FPGA

You „tipically“ start from some kind of refernce design and you end up „wasting“ 50% of your project budget (money, time) and on the other hand getting 90% of your project frustration and stress…

Repeating work: for each link, OS or FPGA again

Communication with the FPGA is often only means to an end


FPGA Manager overview What is FPGA Manager?

A Software Firmware co-solution FPGA Manager Firmware IP solution Acces to user logic in the FPGA

FPGA Manager Software library API for user application


FPGA Manager overview (1)

Covers all the key requirements of a link between a FPGA and a high level language Supports all three connection types (Data stream, Memory Mapped and Signaling)

Supports various links (USB, Ethernet, PCIe, ...)

Supports various operating systems (Windows, Linux)

Supports various high level languages (C # /. NET, C / C ++, Matlab, ...)

Supports different processor architectures (x86, ARM, ...)

Unified software API across all links, operating systems and high level languages

Unified firmware interface across all links (AXI and AXIS)

Multiplexing multiple connecting channels over a physical link

Maximum performance with minimal resource consumption

Simpel but powerful!



Various links require additional chips / drivers / libraries

FPGA Manager, current implementations: USB 2.0/3.0

Gigabit Ethernet

PCIe

Software



USB solutions Require an additional USB Chip (Cypress FX3 oder FTDI 2232H)

Specific link abstraction layer in the FPGA to connect to the USB chip

Specific link abstraction layer in software to access the chip vendors libraries and drivers

Firmware on the USB chips



Ethernet Lösung Requires an Ethernet PHY

Specific link abstraction layer in the FPGA to connect to the PHY via MII/GMII/RGMII

Based on the operation systems socket interface

Uses UDP as transfer protocol

Specific link abstraction layer to access the socket interface



PCIe Lösung Requires a FPGA with PCIe endpoint and und Multi-Gigabit-Transceivers (MGTs)

Specific link abstraction layer in the FPGA to connect to the PCIe endpoint

Specific driver to access the firmware

Specific link abstraction layer in software to access the driver



Software solution Host and Target run on a PC (or SoC)

Target represents a Model of the FPGA (Registerset, Dummy Data Source und Sink) or a real user application

Used especialy during software development before FPGA firmware is ready or for a golden model


FPGA Manager details

All data transfers are handled as streams Data Streams, Memory Mapped und Signaling run over Streams

Custom protocols No dependencies on underlying protocols

Frame based

Only internaly used, not seen by the user

UNISCP Protokoll Used for Data Streaming and Signaling handling

Allows multiplexing, error detection, throttling etc.

UNIMM Protokoll Used for Memory Mapped handling

Encapsulated into UNISCP



FPGA firmware is split up into sveral subcores Link IP Core (UDP/IP/ETH, USB 2.0/3.0, PCIe)

UNISCP IP Core => AXI Stream Upstream/Downstream, Signal Inputs

UNIMM IP Core => AXI Memory Mapped

IP Cores available in plain VHDL, Xilinx Vivado IP and Altera QSYS IP VHDL Flow vs. Block Design Flow



Software library als DLL/Shared Lib MATLAB API

C API

C++ API

C# API

Core in C++ OS independent

Link independent

CPU architecture independent

Memory allocation is done in the user application and data DMAd to/from this buffers


FPGA Manager software API C# – Streaming

void main() { //Create send and receive buffers byte[] receiveArray = new byte[4]; byte[] sendArray = new byte[4] { 1, 2, 3, 4 }; //Open a device with one stream CDevice myDevice = new CDevice("udp://192.168.33.12", 1); //Create Stream 0, Frame based, Upstream Enabled, Downstream Enabled CStream myStream = myDevice.CreateStream(0, true, true, true); //Open myDevice.Open(); myStream.Open(); //Blocking send myStream.Send(ref sendArray, null); //Blocking receive myStream.Receive(ref receiveArray, null); //Close (non-forcing) myStream.Close(false); myDevice.Close(false); }


FPGA Manager software API C# – Memory Mapped

void main() { //Create send and receive buffers byte[] readArray = new byte[4]; byte[] writeArray = new byte[4] { 1, 2, 3, 4 }; //Open a device with one stream CDevice myDevice = new CDevice("udp://192.168.33.12", 1); //Create MmAccess on through Stream 0 CMmAccess myMmAccess = myDevice.CreateMmAccess(0); //Open myDevice.Open(); myMmAccess.Open(); //Blocking write, burst on, address increment on myMmAccess.Write(ref writeArray, 0x12345670, true, false, null); //Blocking read, burst off, address increment on myMmAccess.Read(ref readArray, 0x12345670, false, false, null); //Close (non-forcing) myMmAccess.Close(false); myDevice.Close(false); }


Summary

Connection of FPGAs to high-level languages is a typical application

Anbindung von FPGAs an Hochsprachen ist ein typischer Anwendungsfall

Connection of FPGAs is often only means to an end

Connection shall be simple

Connection shall be flexible

In the majority of cases using a standard solution is cheaper than developing itself

Enclustra GmbH

Referenz Design

04.04.2017 - 32 -

fpga manager - enclustra€¦ · software-defined radio smart vision systems motion & drive...

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