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FPGA-PCI104 Manual

Manufactured by

TRI-M ENGINEERING Engineered Solutions for Embedded Applications

Technical Manual

P/N: FPGA-PCI104 Revision: 6-June-2006

TRI-M ENGINEERING

1407 Kebet Way, Unit 100 Port Coquitlam, BC V3C 6L3

Canada http://www.Tri-M.com

Tel 604.945.9565 North America 800.665.5600

Fax 604.945.9566

6 June 2006 FPGA-PCI104 Manual

Tri-M Engineering Tel: 800.665.5600, 604.945.9565 1407 Kebet Way, Unit 100 Fax: 604.945.9566 Port Coquitlam, BC V3C 6L3 E-mail: [email protected] Canada Web site: www.tri-m.com

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PREFACE

This manual is for integrators of applications of embedded systems. It contains information on hardware requirements and interconnection to other embedded electronics.

DISCLAIMER Tri-M Engineering makes no representations or warranties with respect to the contents of this manual, and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. Tri-M Engineering shall under no circumstances be liable for incidental or consequential damages or related expenses resulting from the use of this product, even if it has been notified of the possibility of such damages. Tri-M Engineering reserves the right to revise this publication from time to time without obligation to notify any person of such revisions. If errors are found, please contact Tri-M Engineering at the address listed on the title page of this document.

COPYRIGHT © 2005-03-027 TRI-M ENGINEERING

No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual, or otherwise, without the express written permission of Tri-M Engineering.



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Table of Contents CHAPTER 1 : PRODUCT FEATURES AND SPECIFICATIONS.........................................................5

CHAPTER 2 : JUMPERS .....................................................................................................................7

CHAPTER 3 : CONNECTORS.............................................................................................................7 3.1 ISP FOR EEPROM - CN1................................................................................................................................................. 8 3.2 JTAG FOR FPGA – CN2................................................................................................................................................. 8 3.3 EXTERNAL POWER INPUT – CN3...................................................................................................................................... 9 3.4 I2C/SMBUS – CN4.......................................................................................................................................................... 9 3.5 DAUGHTER CARDS – CN5, 6, 7, 8.................................................................................................................................... 9 3.6 EXTERNAL REFERENCE CLOCK – CN9 ........................................................................................................................... 10 3.7 EXTERNAL BACKUP BATTERY FOR THE RTC – CN10...................................................................................................... 10 3.8 PCI-104 8-BIT – CN11.................................................................................................................................................. 11

CHAPTER 4 : FPGA FEATURES AND PROGRAMMING.................................................................12 4.1 FPGA DESIGN TOOLS................................................................................................................................................... 13

CHAPTER 5 : FPGA CONNECTIVITY...............................................................................................14 5.1 FPGA ↔ HOST BUS ..................................................................................................................................................... 14 5.2 FPGA ↔ ON-BOARD I/O & SUPPORT CIRCUITS ............................................................................................................. 16

5.2.1 Silicon Serial Number & Real-Time Counter........................................................................................................................16 5.2.2 I2C/SMBus Interface/Accelerator ..........................................................................................................................................16 5.2.3 Reference Clocks ...................................................................................................................................................................16 5.2.4 Power Supply Synchronization..............................................................................................................................................17

5.3 UNUSED PINS ............................................................................................................................................................... 18 5.4 DAUGHTER CARD CONNECTIONS ................................................................................................................................... 18

5.4.1 FPGA ↔ Left-side Daughter Card Connections...................................................................................................................19 5.4.2 FPGA ↔ Right-side Daughter Card Connections ................................................................................................................20 5.4.3 FPGA↔ Daughter Card Clock Signal Pin Outs ...................................................................................................................21

5.5 TEST POINT CONNECTIONS............................................................................................................................................ 21 CHAPTER 6 : CONFIGURATION CIRCUITS ....................................................................................21

6.1 CONFIGURATION CONTROLLER REGISTERS .................................................................................................................... 23 6.1.1 Host Data Clock – Register 0 bit 0........................................................................................................................................23 6.1.2 Host Data – Register 0 bit 1 ..................................................................................................................................................24 6.1.3 Host Chip Select – Register 0 bit 2........................................................................................................................................24 6.1.4 EEProm Data Mode – Register 0 Bit 3 .................................................................................................................................24 6.1.5 FPGA Data Mode – Register 0 Bit 4.....................................................................................................................................24 6.1.6 FPGA Chip Enable – Register 0 Bit 5 ...................................................................................................................................24 6.1.7 FPGA Configure – Register 0 Bit 6.......................................................................................................................................24 6.1.8 FPGA Status – Register 0 Bit 7 .............................................................................................................................................25 6.1.9 FPGA Configuration Mode Select 0, 1 – Register 1 Bits 0, 1 ...............................................................................................25 6.1.10 FPGA Clear – Register 1 Bit 2............................................................................................................................................25 6.1.11 FPGA Output Enable – Register 1 Bit 3..............................................................................................................................25 6.1.12 FPGA Clock User – Register 1 Bit 4 ...................................................................................................................................25 6.1.13 Register 1 Bit 5 ....................................................................................................................................................................25 6.1.14 FPGA Configuration Done – Register 1 Bit 6.....................................................................................................................26 6.1.15 FPGA Initialization Done – Register 1 Bit 7.......................................................................................................................26

6.2 FPGA CONFIGURATION PINS......................................................................................................................................... 26



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CHAPTER 7 : PCI BUS CONFIGURATION.......................................................................................27 7.1 FACTORY-DEFAULT CONFIGURATION ............................................................................................................................. 27

7.1.1 PCI Address Space 0 .............................................................................................................................................................28 7.1.2 PCI Address Space 1 .............................................................................................................................................................29 7.1.3 PCI Address Space 2 .............................................................................................................................................................30 7.1.4 PCI Address Space 3 .............................................................................................................................................................31 7.1.5 PCI Expansion ROM Space...................................................................................................................................................31 7.1.6 GPIO Control ........................................................................................................................................................................31

7.2 TYPICAL PCI BUS CONFIGURATION AFTER POWER-ON ................................................................................................... 32 7.2.1 PCI9030 PCI Configuration Registers..................................................................................................................................32

7.3 PCI9030 LOCAL CONFIGURATION REGISTERS................................................................................................................ 33 APPENDIX 34



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Chapter 1 : Product Features and Specifications Tri-M Engineering’s FPGA-PCI104 is a platform that allows Embedded System builders to harness the power and flexibility of a state-of-the-art FPGA in a standard bus-hosted environment. A key design goal of the FPGA family is to provide as much flexibility as possible on the Input-Output connections to the FPGA.

o The FPGA-PCI104 board is a standard-sized PCI-104 board, with a full 32-bit, 33 MHz PCI v2.2 compliant Target interface (via a PLX 9030 PCI bus interface chip), and an on-board FPGA Configuration Controller (in a CPLD). There is an on-board 32-bit, 60 MHz local bus from the PLX chip, which is mapped into two PCI address blocks by the PLX chip. The full local bus is routed to the FPGA (for use by the user’s IP in the FPGA), in one PCI address block; an 8-bit subset of the local bus is routed to the Configuration Controller, in the other PCI address block.

o The FPGA-PCI104 can operate as either a slave device in a PCI-104 stack, or run stand-alone. o The FPGA-PCI104 is based on the Altera® Cyclone™ EP1C FPGA family (324-pin BGA

package). The FPGA-PCI104 is available in three versions, using the 4,000 Logic Element (LE) EP1C4, 12,000 LE EP1C12, or the 20,000 LE EP1C20 parts. The FPGA on the FPGA-PCI104 is rated at 275 MHz, and commercial temperature range.

o The FPGA-PCI104 utilizes a serial EEProm to initialize the FPGA (1-Mbit Altera EPCS1 is used for the 4,000 LE FPGA, and a 4-Mbit EPCS4 for the 12,000/20,000 LE FPGA). Any portion of the serial EEProm not needed for FPGA configuration purposes may also be used as on-board serial memory.

o The FPGA and the EEPprom can both be programmed via PCI-104 bus. The FPGA can also be programmed via the JTAG connector. The EEPprom can also be programmed via the ISP connector. Both the JTAG and ISP connectors are compatible with Altera’s ByteBlaster™ II programming cable.

o Using appropriate IP in the FPGA, In-Circuit Emulation functions via the JTAG connector are possible.

o I/O pins from the FPGA are brought out to four vertical, polarized headers. The headers permit plugging on various daughter cards, which can provide various types of analog and/or digital I/O functions to the FPGA. See the Tri-M Engineering document FPGA Family Daughter Card Pinout Specifications for more information.

o Standard daughter card sizes are:

QS Quarter Size 1.750" x 1.020" HSV Half Size Vertical 1.750" x 2.120" HSH Half Size Horizontal 3.550" x 1.020" FS Full Size 3.550" x 2.120" PC/104 PC/104 3.550" x 3.775"

o The ordering and arrangement of all pins on each of the four daughter card headers is identical,

which permits the daughter cards to be mounted interchangeably, and in various combinations, depending on size: - QS daughter cards plug onto any header



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- HSH cards plug onto the two top or two bottom headers, and can be rotated 180° - HSV cards plug onto the two left or two right headers - FS cards utilize all four headers, and can be rotated by 180° - PCI-104 cards utilize all four headers and plug on one way only - Two HSH or two HSV cards may be used together - Up to two QS cards can be used in combination with either one HSH or one HSV card - Up to four QS cards may used together

o Matching mounting post locations on the FPGA-PCI104 and daughter cards provide mechanical rigidity. Daughter cards mount on the top of the FPGA-PCI104, with the component side of the daughter cards facing down. The combined FPGA-PCI104 and daughter cards fit within the space constraints of the PCI-104 Standard.

o A cut out area on each side of the FPGA-PCI104 provides additional vertical clearance for components on a portion of the component side of the daughter cards.

o The standard combination of FPGA-PCI104 and daughter cards provides 9 mm clearance between the component sides of the FPGA-PCI104 and daughter cards. Other height clearances may be available on special order.

o A terminal strip on the FPGA-PCI104 allows connection of +5 Volt I2C/SMBus signals. o An on-board Silicon Serial Number and Real-Time Counter chip is connected to the FPGA. IP in

the FPGA can use this device to uniquely identify FPGA-PCI104 boards, and for time-keeping purposes. The Silicon Serial Number has a guaranteed-unique 64-bit number. The RTC is a 32-bit counter, with 1-second resolution and ±2 minutes per month accuracy. An on-board “SuperCap” provides about two weeks backup supply for the RTC. A pin header is also supplied for connecting an external backup battery for the RTC.

o A 60 MHz oscillator provides a reference frequency input clock signal to the FPGA. An SMB connector provides for an external alternate clock signal input. Bus clock signals from the PCI-104 bus provide other clock inputs to the FPGA.

o The FPGA-PCI104 provides all necessary voltage regulation with high efficiency switching regulators. These regulators have output over-voltage crowbar protection, and fold-back over-current limiting. Input power is taken from the +5 Volt supply pins of the PC-104 bus or from an external power supply (6-18 VDC).

Note that, when running off external 6–18 VDC in a PCI-104 stack, power is not supplied to the PCI-104 bus from the FPGA-PCI104 board’s regulators.

o The VIO regulator provides up to 5 Amps of 3.3VDC for use by the FPGA-PCI104 and the daughter cards. The VCORE regulator provides up to 10 Amps of 1.5 VDC to the FPGA core. Both switching regulators free-run at ~220 KHz, but either or both may be synchronized to a clock-out signal from the FPGA, at any frequency between ~200 and ~290 KHz.

o There is no connection on the FPGA-PCI104 between the on-board VIO regulator and the power pins of the FPGA’s I/O banks 2 or 4; all power pins for those banks are connected only to pins on the daughter card headers. The circuitry on the daughter cards controls the supply voltage levels that each the FPGA’s bank 2 and 4 operate at (the user must also select a matching supply level setting in the FPGA IP design tool). Banks 2 and 4, and the daughter card(s) connected to them, can each be set to run at different levels, but all daughter cards connected to bank 2 must run at the same level, and similarly for boards connected to bank 4.



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Chapter 2 : Jumpers The FPGA-PCI104 board has three jumpers, for setting the PCI-104 bus “slot” address of the board.

PCI Slot # JP1 (PCI INT) JP2 (PCI ID) JP3 (PCI CLK) 0 1-2 1-2 1-2 1 2-3 2-3 2-3 2 4-5 4-5 4-5

3 5-6 5-6 5-6 Note: JP1, JP2 & JP3 are 1x6 2mm pin headers, each with pin 1 at the left when the board is oriented with the PCI-104 connector at the top.

Chapter 3 : Connectors

Connector Function CN1 In-System Programming (ISP) connector for EPCSx EEPROM CN2 JTAG connector for FPGA CN3 External Power Input terminal strip CN4 I2C/SMBus terminal strip CN5 Lower Left Daughter Card connector (“Card 1”, FPGA I/O bank 2) CN6 Upper Left Daughter Card connector (“Card 2” , FPGA I/O bank 2) CN7 Lower Right Daughter Card connector (“Card 3”, FPGA I/O bank 4) CN8 Upper Right Daughter Card connector (“Card 4”, FPGA I/O bank 4) CN9 External Reference Clock Input connector (SMB) CN10 External Backup Battery connector for RTC CN11 PCI-104 connector (120 pin) CN14 ** Factory programming connector

* only one of CN13 & T2 can be present (or neither may be) ** CN14 is a factory-use-only special connector for programming the Configuration Controller.



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3.1 ISP for EEProm - CN1 The FPGA-PCI104’s on-board Configuration EEProm is accessed via connector CN1 (a 10-pin header compatible with Altera’s.ByteBlaster.II.cable). Note: All the signals on CN1 go through the on-board Configuration Controller and may be affected by the host-bus controlled EEProm clock/data steering functions of the Configuration Controller. The Configuration Controller automatically enables a path for the ISP clock and data signals, between the EEProm and CN1, whenever a ByteBlaster II cable is plugged in.

Pin Number Signal Name Description Description Signal

Name Pin

Number 1 DCLK Data Clock Signal Signal Ground GND 2

3 CONF_DONE Configuration Status from FPGA Power Supply Vcc 4

5 nCONFIG Configuration Control to FPGA

FPGA Chip Enable nCE 6

7 Data Data Out from EEProm

EEProm Chip Select nCS 8

9 ASDI Data In to EEProm Signal Ground GND 10 Note: CN1 is an edge-mounted header with odd-numbered pins located on the “top” and even numbered pins on the “bottom”. Pin 1 is designated by a white dot on the PCB.

3.2 JTAG for FPGA – CN2 The FPGA JTAG port is accessed via connector CN2 (10-pin header compatible with Altera’s ByteBlaster.II.cable).

Pin Number

Signal Name Description Description Signal

Name Pin

Number 1 TCK Clock Signal Signal Ground GND 2

3 TDO Data Out from FPGA

Power Supply Vcc 4

5 TMS JTAG State Machine Control – – 6

7 – – – – 8 9 TDI Data In to FPGA Signal Ground GND 10

Note: CN2 is an edge-mounted header with odd-numbered pins located on the “top” and even numbered pins on the “bottom”. Pin 1 is designated by a white dot on the PCB.



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3.3 External Power Input – CN3 The FPGA-PCI104 can be powered by supplying +5 VDC through the PCI-104 connector from a PCI-104 power supply, such as an HESC104+. Alternatively, the FPGA-PCI104 can be powered by supplying either a regulated +5 VDC or an unregulated +6 to +18 VDC, to CN3. Note: When the FPGA-PCI104 is supplied +5 VDC via the PCI-104 connector, then +5 VDC from the PCI-104 bus will be present on pin 1 of CN3. If an external +5 VDC supply is connected to pin 1 of CN3, then +5 VDC pins will be supplied to the PCI-104 bus connector, and thus can be used to power other boards on the bus. Note: If an external +6 to +18 VDC supply is used, only the FPGA-PCI104 will be powered.

Pin Number Pin Label Signal 1 PWR +5 VDC Regulated 2 (n/a) GND 3 EXT +6 to +18 VDC Unregulated

Note: CN3 is a 3-position terminal strip, with the two pin labels above the strip. Pin 2 (GND) is the

middle terminal.

3.4 I2C/SMBus – CN4 Terminal strip CN4 provides a +5 VDC level I2C/SMBus electrical interface, to/from a buffer chip between CN4 and the FPGA.

Pin Number Pin Label Signal 1 C GND 2 (none) SDA 3 SCL SCL

Note: CN4 is a 3-position terminal strip and is labelled “I2C”, with the two pin labels above the strip.

Pin 2 (SDA) is the middle terminal.

3.5 Daughter Cards – CN5, 6, 7, 8 See the Tri-M Engineering document FPGA Family Daughter Card Pinout Specifications.



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3.6 External Reference Clock – CN9 An external reference clock input signal for the FPGA may be connected to CN9. Connector CN9 is a 50-ohm, right angle SMB connector. The external clock signal is connected to one of the two clock reference inputs of the FPGA’s PLL1. A 49.9-Ohm resistor terminates this clock signal. In addition, there is a 22-Ohm resistor in series between pin 1 of the connector and the PLL input pin of the FPGA. The external clock signal level must be +3.3 VDC, and must meet the frequency, rise/fall time and other AC specifications of the FPGA in use on the FPGA-PCI104 board (see Table 4-52 in the Cyclone Device Handbook).

Pin Number Signal 1 (centre pin) Reference Clock In 2 (shield ring) GND

Note: CN9 is a 50-ohm, right angle SMB connector, and is labelled “EXT CLK”.

3.7 External Backup Battery for the RTC – CN10 A 0.33 Farad SuperCap supplies backup power for the on-board Silicon Serial Number and Real Time Counter chip (a Dallas/Maxim DS2417P). This backup power is sufficient to maintain the RTC for about two weeks. Optionally, an external power source (3.0 V nominal level) can supply backup power to the RTC for as long as desired.

Pin Number Signal 1 VBATT

2 GND Note: CN10 is a 2-position right angle 0.1” spacing pin header, and is labelled “EXT BAT”. Pin 1 is on

the side closest to the SuperCap (C97); pin 2 is closest to the DC Power In connector (CN3).



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3.8 PCI-104 – CN11 Connector CN11 is the PCI-104 bus with the following signals and power sources.

Pin A B C D 1 GND NC +5V AD00 2 VccIOP AD02 AD01 +5V 3 AD05 GND AD04 AD03 4 C/BE0 AD07 GND AD06 5 GND AD09 AD08 GND 6 AD11 VccIOP AD10 PMEX 7 AD14 AD13 GND AD12 8 +3.3V CBE1 AD15 +3.3V 9 SERR GND SB0 PAR 10 GND PERR +3.3V SDONE 11 STOP +3.3V LOCK GND 12 +3.3V TRDY GND DEVSEL 13 FRAME GND IRDY +3.3V 14 GND AD16 +3.3V C/BE2 15 AD18 +3.3V AD17 GND 16 AD21 AD20 GND AD19 17 +3.3V AD23 AD22 +3.3V 18 – GND – IDSEL2 19 AD24 C/BE3 VccIOP IDSEL3 20 GND AD26 AD25 GND 21 AD29 +5V AD28 AD27 22 +5V AD30 GND AD31 23 – GND N/A VccIOP 24 GND REQ2 +5V N/A 25 – VI/O GNT2 GND 26 +5V – GND N/A 27 CLK_PCI_2 +5V CLK_PCI_3 GND 28 GND INTD +5V RST 29 – – – INTB 30 – NC NC GND



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Chapter 4 : FPGA Features and Programming The Altera® Cyclone™ used on the FPGA-PCI104 board is a state-of-the-art Field Programmable Gate Array chip (FPGA). It is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process. Below is a brief list of the features of the FPGA, extracted from the Altera datasheet for the part. For more detailed information, see the Altera Cyclone Datasheet and Device Handbook.

o Up to 20,060 Logic Elements. o Up to 294,912 RAM bits (36,864 bytes). o Support for various single-ended & differential I/O standards. o Two PLLs provide clock multiplication and phase shifting. o Support for external memory. o Support for various intellectual property (IP) cores, including Altera MegaCore®

functions and Altera Megafunctions Partners Program (AMPPSMSM).

Feature EP1C4 EP1C12 EP1C20 LEs 4,000 12,060 20,060

M4K RAM blocks (128 × 36 bits) 17 52 64 Total RAM bits 78,336 239,616 294,912

M4K RAM Columns x Rows 1 x 17 2 x 52 2 x 64 LAB Columns 17 26 32

PLLs 2 2 2 Speed

(max clock tree frequency) 275 MHz

Operating Temperature (FPGA internal junction) 0° – 85° C

The FPGA contains a two-dimensional row and column based architecture to implement custom logic. Column and row interconnects of varying speeds provide signal interconnects between Logic Array Blocks (LAB) and embedded memory blocks. The logic array consists of LABs, with 10 Logic Elements (LE) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M4K RAM blocks are true dual-port memory blocks with 4K bits of memory plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 200 MHz. These blocks are grouped into columns across the device in between certain LABs. Each FPGA I/O pin is fed by an I/O element (IOE) located at the ends of LAB rows and columns around the periphery of the device. I/O pins support various single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and output-enable signals. Dual-purpose DQS, DQ, and DM pins along with delay chains (used to phase-align DDR signals) provide interface support with external memory devices such as DDR SDRAM, and FCRAM devices at up to 133 MHz (266 Mbps).



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The FPGA provides a global clock network and internal PLLs. The global clock network consists of eight global clock lines that drive throughout the entire FPGA. The global clock network can provide clocks for all resources within the device, such as IOEs, LEs, and memory blocks. The global clock lines can also be used for control signals. The FPGA PLLs provide general-purpose clocking with clock multiplication and phase shifting as well as external outputs for high-speed differential I/O support.

4.1 FPGA Design Tools Altera’s Quartus II software suite is useful for developing applications for the FPGA-PCI104. Quartus II comes in two flavours: the free Web Edition, and the paid-annual-subscription version. The Web Edition is adequate for many users – those who wish to implement custom logic and processing on the FPGA-PCI104 boards, using their own-design IP, Altera’s basic MegaCore® IP library, and IP from various third-party sources. The Web Edition requires a standard PC, running Windows® 2000 or later. For more advanced work, the Subscription version of Quartus II, is available. The Subscription version provides a variety of additional design productivity tools (LogicLock™, RTL Viewer, netlist & synthesis optimizations), and the full IP BASE MegaCore IP library. The Subscription version is also available for use with Solaris, Linux and HP-UX operating systems as well as Windows, and with either a node-lock or floating network license. Below is a comparison of some of the features of Quartus II (version 5.1) Subscription and Web Edition software. For more information, see the Altera web site.

Feature Quartus II Full Quartus II Web EditionLicensing Perpetual 150 days RTL Viewer & Technology Map Viewer Yes No LogicLock™ Regions & Custom Regions Yes No Timing Closure Floorplan Yes Yes Assignment Editor & I/O Checking Features Yes Yes Chip Editor Yes Yes Netlist & Physical Synthesis Optimizations Yes Yes Timing & Resource Optimization Advisors Yes Yes PowerPlay power analysis Yes Yes Project Archive Yes Yes Tcl Scripting Support Yes Yes Fast Fit Yes Yes SignalTap® II Logic Analyzer Yes Yes** SignalProbe™ Feature Yes Yes** STAMP Models Yes Yes Save Intermediate Synthesis Results Yes Yes SOPC Builder Yes Yes Design Assistant Yes Yes Advanced Tutorials Yes No Virtual I/O Pins Yes No Device Migration Yes Yes Enable/Disable Messages Yes Yes IBIS Model Generation Yes Yes Testbench Generation from VWF Files, Testbench Template Generation Yes Yes

** available if the TalkBack feature is enabled



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Other FPGA design tools may also be used, either stand-alone or in combination with Quartus II. Any EDA tool which creates design files in either standard Verilog or VHDL, or which creates a netlist in one of the formats supported by Quartus II, may be used. See the EDA Partners page on Altera’s web site for more information.

Chapter 5 : FPGA Connectivity

5.1 FPGA ↔ Host Bus The FPGA is located “between” the host CPU bus and the Daughter Card headers, and the on-board I/O (SMBus, SSN+RTC) circuits. Architecturally then, the IP in the FPGA can be a simple logic interface between the host bus and the Daughter Cards, or more complex I/O processing and control. The FPGA can also be used as a “slave” processor to the bus-host CPU, with or without use of Daughter Cards and their I/O circuits. On the FPGA-PCI104 board, the Cyclone is connected to the local bus from the on-board PLX Technology PCI9030 PCI interface chip; there is no direct connection to the PCI-104 host bus. All the pins of the 32-bit local bus from the PCI9030 are connected directly to the Cyclone; the PCI9030 also provides +5 to +3.3 VDC voltage translation between the PCI-104 bus & the FPGA. The user’s IP may use all or part of the local bus connections to communicate to & from the host CPU; the Cyclone is located in 3 of the 4 PCI address spaces controlled by the PCI90301. For more information, see the PCI9030 Data Book and various other reference documents, which can be found on the PLX Technology web site (www.plxtech.com), in the I/O Accelerators section of the site. The FPGA-PCI104 board can also be used stand-alone – i.e., not plugged into the PCI-104 bus, and thus operating without a bus-host CPU board.

1 The PCI9030 implements a PCI Target Interface only; thus the FPGA-PCI104 board may never act as a PCI Master. 4 JTAG configuration takes precedence over all other configuration modes (see Chapter 13, Cyclone Device Handbook). Commencing a JTAG configuration sequence will result in the FPGA terminating any other configuration sequence then in progress. The on-board Configuration Controller has no means to detect that a JTAG sequence has begun. Therefore, it is recommended that JTAG configuration be performed only when no other sequence is running.



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The following table provides the pin-out information for the PCI9030 Local Bus connections to the FPGA.

Pin Number

Bank Number

Pin Name/Function

PLX9030 LocalBus Signal

C17 3 IO LAD28 D15 3 IO LAD21 D16 3 IO LAD12 D17 3 IO LAD24 D18 3 IO LAD14 E14 3 IO LAD30 E15 3 IO LAD27 E16 3 IO LAD6 E17 3 IO LAD11 F12 3 IO LAD17 F13 3 IO LBE3x F14 3 IO LBE2x F15 3 IO LBE0x F16 3 IO LBE1x F17 3 IO LAD9 F18 3 IO ALE G12 3 IO LAD22 G13 3 IO LAD13 G14 3 IO LAD15 G15 3 IO LAD10 G16 3 IO LAD19 G17 3 IO LAD7 G18 3 IO LAD3 H13 3 IO LAD31 H14 3 IO LAD29 H15 3 IO LAD5 H16 3 IO LAD4 H17 3 IO LAD2 H18 3 IO LAD1 J13 3 IO LAD25 J14 3 IO LAD26 J15 3 CLK2* BCLKO J16 3 CLK3* INT_OSC L13 3 IO LAD16 L14 3 IO LAD20 L15 3 IO LAD8 L16 3 IO LAD18 L17 3 IO LPMESET L18 3 IO LAD0 M13 3 IO n/c M14 3 IO n/c M15 3 IO LPMINTx M16 3 IO LAD23 M17 3 IO READYx M18 3 IO GPIO8 N12 3 IO n/c N13 3 IO n/c N14 3 IO BTERMx N15 3 IO BLASTx N16 3 IO WRx N17 3 IO RDx N18 3 IO ADSx P14 3 IO LWRx P15 3 IO n/c P16 3 IO LRESETOx P17 3 IO CS1x R15 3 IO LINTI2 R16 3 IO LINTI1 R17 3 IO GPIO1 R18 3 IO GPIO0 T16 3 IO GPIO3/CS3x T17 3 IO GPIO2/CS2x

* these pins are the Reference Clock inputs for the FPGA’s PLL2. They are input-only pins.



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5.2 FPGA ↔ On-Board I/O & Support Circuits The following tables show the connections between the FPGA’s I/O pins & the on-board I/O and support circuits, and the required signal level and pin/logic option settings in Quartus II’s Assignment Editor dialog. Many of the FPGA’s IO pins have alternate functions. The alternate function names are listed whenever they could be used on the FPGA-PCI104.

5.2.1 Silicon Serial Number & Real-Time Counter A 1-Wire® Dallas/Maxim DS2417P chip supplies a one second resolution, ±2 minute per accurate real-time 32-bit counter (RTC), and a guaranteed-unique 64-bit on-chip serial number (SSN). The chip’s RTC is driven by an on-board 32.768 KHz crystal. Backup power for the RTC is provided by an on-board 0.33 Farad SuperCap, and/or an external battery (via CN10). The SuperCap, when fully charged, can provide enough supply current to the RTC for about two weeks of RTC “keep alive” operation. The on-chip serial number provides a way to identify each individual FPGA-PCI104 board. This can be used for various purposes: some examples are:

• Tracking boards for inventory control or maintenance purposes. • Controlling use of licensed IP, allowing it to be run only on boards with specific serial numbers.

FPGA↔ SSN+RTC Circuit Connections

Pin Number

Bank Number

Pin Function

I/O Signal Name

I/O Circuit Function Signal Level

C2 1 IO SNUM_BUS 1-Wire Bus LVCMOS, open-drain and weak pull-up

5.2.2 I2C/SMBus Interface/Accelerator A Linear Technology LTC4300-2 interface chip provides voltage level translation between the FPGA and the external +5 VDC I2C/SMBus signals (connected via CN4). The FPGA controls the rise-time acceleration function of LTC4300-2. See the LTC4300 data sheet for more details.

FPGA↔ I2C/SMBus Circuit Connections Pin

Number Bank

Number Pin

Function I/O.Signal

Name I/O Circuit Function Signal Level R1 1 IO SMBUS_ACC HI ⇒ SMBus Accelerator Enable LVCMOS, weak pull-up T2 1 IO SDA_B SMBus Data LVCMOS, weak pull-up T3 1 IO SCL_B SMBus Clock LVCMOS, weak pull-up

5.2.3 Reference Clocks A 60 MHz crystal oscillator provides a reference clock for the FPGA. This oscillator drives one of the reference clock inputs for one of the FPGA’s two internal Phase Lock Loops (PLL2). The oscillator is enabled by default (via a 10K0 Ohm pull up to the VccIO 3.3 VDC supply), but can be turned off by a clearing a pin on the FPGA.



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An external reference clock signal can drive the other reference clock input for the FPGA’s PLL2. The external Reference Clock signal is connected via CN9.

FPGA↔ PLL Reference Clock Circuit Connections

Pin Number

Bank Number

Pin Function

Internal PLL

I/O Signal Name

I/O Circuit Function Signal Level

J3 3 CLK0 1 EXT_OSC External Clock input (via CN9) – J4 3 CLK1 1 INT_OSC On-board Clock (60 MHz) – N3 3 IO – INT_OSC_EN HI ⇒ On-board Clock Enable LVCMOS

5.2.4 Power Supply Synchronization Two I/O pins from the FPGA are connected to the synchronization input pin on each of the FPGA-PCI104 switching voltage regulators. This allows the operating mode and switching frequency of the regulators to be controlled. The regulators are Linear Technology LTC1735 chips, and generate the board’s VCORE (1.5 VDC) and VIO (3.3 VDC) supplies. By default, the regulators run in continuous synchronization mode (via a 1K Ohm pull-down resistor to GND on the FCB pin), and free-run at a typical frequency of approximately 220 KHz. By using the two IO pins from the FPGA, the regulators may be independently or simultaneously synchronized to a clock signal generated by the FPGA’s PLL2, at any frequency between ~200 KHz and ~290 KHz. Each regulator may also put into Burst Mode™, by setting the matching FPGA pin to HI.

Power Supply Control Pins from FPGA Pin

Number Bank

Number Pin

FunctionOptional Function

I/O SignalName

I/O Circuit Function

K15 3 IO PLL2_OUTp SYNC_1V5 clock signal ⇒ Sync HI ⇒ Burst Mode

K16 3 IO PLL2_OUTn SYNC_3V3 clock signal ⇒ Sync HI ⇒ Burst Mode



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5.3 Unused Pins A number of pins on the FPGA are not used. It is possible to use the IOE cells on these pins for special purposes in the User’s IP – but it is cautioned that there is no way to probe or test these pins, other than via JTAG boundary scan techniques.

Unused FPGA Pins Pin Number

Bank Number

Pin Function EP1C4/12

Pin FunctionEP1C20

D4 1 IO IO E4 1 IO IO E5 1 IO IO F1 1 IO IO F4 1 IO IO F5 1 IO IO F6 1 IO IO F7 1 IO IO G3 1 IO IO G4 1 IO IO G5 1 IO IO G6 1 IO IO H1 1 IO IO H2 1 IO IO H3 1 IO IO H4 1 IO IO H5 1 IO IO H6 1 IO IO L4 1 IO IO L5 1 IO IO L6 1 IO IO L7 1 IO IO M1 1 IO IO M4 1 IO IO M5 1 IO IO M6 1 IO IO M13 3 IO IO N1 1 IO IO N2 1 IO IO N4 1 IO IO N5 1 IO IO N6 1 IO IO N7 1 IO IO N12 3 IO IO N13 3 IO IO P4 1 IO IO P5 1 IO IO P15 3 IO IO

5.4 Daughter Card Connections Each FPGA pin defaults as a general-purpose IO pin. For many of the pins, there are alternate IO functions that may be enabled. These functions are listed for each pin (note that there are some differences between the alternate names for the EP1C4/20 and the EP1C12). Note: All signals to each Daughter Card header come from the same FPGA pin, no matter which size of FPGA is being used on the FPGA-PCI104 board.



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5.4.1 FPGA ↔ Left-side Daughter Card Connections

FPGA Daughter Card

Pin Number

Pin Function

Optional Function EP1C4



External Memory Signal

VREF Bank

Card Number

Pin Number

Signal Name

Optional Signal Name

A4 IO LVDS33n LVDS26n LVDS33n DQ1T6 VREF2B2 1 18 IO17 DB6, DIO5n A6 IO VREF2B2 VREF2B2 VREF2B2 – VREF2B2 1 27 IO6 IOVREF0 A7 IO LVDS39n LVDS31n LVDS39n DQ1T2 VREF2B2 1 30 IO21 DB2, DIO6n A8 IO LVDS41n LVDS33n LVDS41n – VREF1B2 1 39 IO10 DIO3n A9 IO LVDS43n LVDS35n LVDS43n – VREF1B2 1 51 IO14 DIO5n B4 IO LVDS33p LVDS26p LVDS33p DQ1T7 VREF2B2 1 16 IO16 DB7, DIO5p B5 IO DPCLK2 DPCLK2 DPCLK2 DQS1T VREF2B2 1 42 IO25 DQS B6 IO LVDS36n LVDS28n LVDS36n – VREF2B2 1 15 IO2 DIO1n B7 IO LVDS39p LVDS31p LVDS39p DQ1T3 VREF2B2 1 28 IO20 DB3, DIO6p B8 IO LVDS41p LVDS33p LVDS41p – VREF1B2 1 41 IO11 DIO3p B9 IO LVDS43p LVDS35p LVDS43p – VREF1B2 1 53 IO15 DIO5p C5 IO LVDS34n LVDS27n LVDS34n DQ1T4 VREF2B2 1 24 IO19 DB4 C6 IO LVDS36p LVDS28p LVDS36p – VREF2B2 1 17 IO3 DIO1p C7 IO LVDS38p LVDS30p LVDS38p – VREF2B2 1 23 IO5 DIO2p C8 IO LVDS42p LVDS34p LVDS42p – VREF1B2 1 47 IO13 DIO4p C9 IO LVDS44p LVDS36p LVDS44p – VREF1B2 1 46 IO26 – D5 IO LVDS34p LVDS27p LVDS34p DQ1T5 VREF2B2 1 22 IO18 DB5 D6 IO LVDS37p LVDS29p LVDS37p – VREF2B2 1 11 IO1 DIO0p D7 IO LVDS38n LVDS30n LVDS38n – VREF2B2 1 21 IO4 DIO2n D8 IO LVDS42n LVDS34n LVDS42n – VREF1B2 1 45 IO12 DIO4n D9 IO LVDS44n LVDS36n LVDS44n DM1T VREF1B2 1 40 IO24 DM E6 IO LVDS37n LVDS29n LVDS37n – VREF2B2 1 9 IO0 DIO0n E7 IO LVDS40p LVDS32p LVDS40p DQ1T1 VREF2B2 1 34 IO22 DB1, DIO7p E8 IO LVDS40n LVDS32n LVDS40n DQ1T0 VREF2B2 1 36 IO23 DB0, DIO7n E11 IO – – – – VREF1B2 1 48 IO27 – A10 IO LVDS48p LVDS38p LVDS48p – VREF1B2 2 11 IO1 DIO0p A11 IO LVDS51p LVDS40p LVDS51p DM0T VREF1B2 2 40 IO24 DM A12 IO LVDS53p LVDS42p LVDS53p – VREF1B2 2 41 IO11 DIO3p A13 IO LVDS56p LVDS45p LVDS56p – VREF0B2 2 47 IO13 DIO4p A15 IO LVDS62p LVDS48p LVDS62p DQ0T1 VREF0B2 2 34 IO22 DB1, DIO7p B10 IO LVDS48n LVDS38n LVDS48n – VREF1B2 2 9 IO0 DIO0n B11 IO LVDS51n LVDS40n LVDS51n – VREF1B2 2 46 IO26 – B12 IO LVDS53n LVDS42n LVDS53n – VREF1B2 2 39 IO10 DIO3n B13 IO LVDS56n LVDS45n LVDS56n – VREF0B2 2 45 IO12 DIO4n B14 IO DPCLK3 DPCLK3 DPCLK3 DQS0T VREF0B2 2 42 IO25 DQS B15 IO LVDS62n LVDS48n LVDS62n DQ0T0 VREF0B2 2 36 IO23 DB0, DIO7n B16 IO LVDS63p LVDS50p LVDS63p – VREF0B2 2 53 IO15 DIO5p C10 IO LVDS49n LVDS39n LVDS49n – VREF1B2 2 15 IO2 DIO1n C11 IO LVDS52n LVDS41n LVDS52n – VREF1B2 2 21 IO4 DIO2n C12 IO LVDS54p LVDS43p LVDS54p DQ0T7 VREF0B2 2 16 IO16 DB7, DIO5p C13 IO LVDS55p LVDS44p LVDS55p DQ0T5 VREF0B2 2 22 IO18 DB5 C14 IO VREF0B2 VREF0B2 VREF0B2 – VREF0B2 2 27 IO6 IOVREF0 C15 IO LVDS61n LVDS47n LVDS61n DQ0T2 VREF0B2 2 30 IO21 DB2, DIO6n C16 IO LVDS63n LVDS50n LVDS63n – VREF0B2 2 51 IO14 DIO5n D10 IO LVDS49p LVDS39p LVDS49p – VREF1B2 2 17 IO3 DIO1p D11 IO LVDS52p LVDS41p LVDS52p – VREF1B2 2 23 IO5 DIO2p D12 IO LVDS54n LVDS43n LVDS54n DQ0T6 VREF0B2 2 18 IO17 DB6, DIO5n D13 IO LVDS55n LVDS44n LVDS55n DQ0T4 VREF0B2 2 24 IO19 DB4 D14 IO LVDS61p LVDS47p LVDS61p DQ0T3 VREF0B2 2 28 IO20 DB3, DIO6p E13 IO – – – – VREF0B2 2 48 IO27 – E10 IO VREF1B2 VREF1B2 VREF1B2 – VREF1B2 1 & 2 29 IO7 IOVREF1



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5.4.2 FPGA ↔ Right-side Daughter Card Connections

FPGA Daughter Card Pin

Number Pin

Function Optional Function EP1C4



External Memory Signal

VREF Bank

Card Number

Pin Number

Signal Name

Optional Signal Name

P6 IO LVDS123p LVDS97p LVDS123p DQ1B4 VREF2B4 3 28 IO20 DB3, DIO6p P10 IO – – – – VREF1B4 3 48 IO27 – R4 IO DPCLK7 DPCLK7 DPCLK7 DQS1B VREF2B4 3 27 IO6 IOVREF0 R5 IO VREF2B4 VREF2B4 VREF2B4 – VREF2B4 3 42 IO25 DQS R6 IO LVDS122n LVDS96n LVDS122n – VREF2B4 3 39 IO10 DIO3n R7 IO LVDS120n LVDS94n LVDS120n DQ1B0 VREF2B4 3 16 IO16 DB7, DIO5p R8 IO LVDS118n LVDS92n LVDS118n – VREF1B4 3 21 IO4 DIO2n R9 IO LVDS116p LVDS90p LVDS116p DM1B VREF1B4 3 40 IO24 DM T4 IO LVDS127p LVDS100p LVDS127p – VREF2B4 3 47 IO13 DIO4p T5 IO LVDS126p LVDS99p LVDS126p DQ1B7 VREF2B4 3 36 IO23 DB0, DIO7n T6 IO LVDS122p LVDS96p LVDS122p – VREF2B4 3 41 IO11 DIO3p T7 IO LVDS120p LVDS94p LVDS120p DQ1B1 VREF2B4 3 18 IO17 DB6, DIO5n T8 IO LVDS118p LVDS92p LVDS118p – VREF1B4 3 23 IO5 DIO2p T9 IO LVDS116n LVDS90n LVDS116n – VREF1B4 3 46 IO26 – U3 IO LVDS128p LVDS102p LVDS128p – VREF2B4 3 53 IO15 DIO5p U4 IO LVDS127n LVDS100n LVDS127n – VREF2B4 3 45 IO12 DIO4n U5 IO LVDS126n LVDS99n LVDS126n DQ1B6 VREF2B4 3 34 IO22 DB1, DIO7p U6 IO LVDS124n LVDS98n LVDS124n DQ1B5 VREF2B4 3 30 IO21 DB2, DIO6n U7 IO LVDS121p LVDS95p LVDS121p DQ1B3 VREF2B4 3 24 IO19 DB4 U8 IO LVDS119p LVDS93p LVDS119p – VREF1B4 3 17 IO3 DIO1p U9 IO LVDS117p LVDS91p LVDS117p – VREF1B4 3 11 IO1 DIO0p V4 IO LVDS128n LVDS102n LVDS128n – VREF2B4 3 51 IO14 DIO5n V7 IO LVDS121n LVDS95n LVDS121n DQ1B2 VREF2B4 3 22 IO18 DB5 V8 IO LVDS119n LVDS93n LVDS119n – VREF1B4 3 15 IO2 DIO1n V9 IO LVDS117n LVDS91n LVDS117n – VREF1B4 3 9 IO0 DIO0n P12 IO – – – – VREF0B4 4 48 IO27 – P13 IO VREF0B4 VREF0B4 VREF0B4 – VREF0B4 4 27 IO6 IOVREF0 R10 IO LVDS111n LVDS87n LVDS111n – VREF1B4 4 45 IO12 DIO4n R11 IO LVDS109p LVDS86p LVDS109p – VREF1B4 4 41 IO11 DIO3p R12 IO LVDS106n LVDS83n LVDS106n DQ0B6 VREF0B4 4 34 IO22 DB1, DIO7p R13 IO LVDS104n LVDS81n LVDS104n – VREF0B4 4 15 IO2 DIO1n R14 IO LVDS99n LVDS79n LVDS99n DQ0B2 VREF0B4 4 22 IO18 DB5 T10 IO LVDS111p LVDS87p LVDS111p – VREF1B4 4 47 IO13 DIO4p T11 IO LVDS109n LVDS86n LVDS109n – VREF1B4 4 39 IO10 DIO3n T12 IO LVDS106p LVDS83p LVDS106p DQ0B7 VREF0B4 4 36 IO23 DB0, DIO7n T13 IO LVDS104p LVDS81p LVDS104p – VREF0B4 4 17 IO3 DIO1p T14 IO LVDS99p LVDS79p LVDS99p DQ0B3 VREF0B4 4 24 IO19 DB4 T15 IO LVDS97n LVDS76n LVDS97n – VREF0B4 4 9 IO0 DIO0n U10 IO LVDS112p LVDS88p LVDS112p – VREF1B4 4 53 IO15 DIO5p U11 IO LVDS108p LVDS85p LVDS108p DM0B VREF1B4 4 40 IO24 DM U12 IO LVDS107n LVDS84n LVDS107n – VREF1B4 4 21 IO4 DIO2n U13 IO LVDS105n LVDS82n LVDS105n DQ0B4 VREF0B4 4 28 IO20 DB3, DIO6p U14 IO DPCLK6 DPCLK6 DPCLK6 DQS0B VREF0B4 4 42 IO25 DQS U15 IO LVDS98n LVDS78n LVDS98n DQ0B0 VREF0B4 4 16 IO16 DB7, DIO5p U16 IO LVDS97p LVDS76p LVDS97p – VREF0B4 4 11 IO1 DIO0p V10 IO LVDS112n LVDS88n LVDS112n – VREF1B4 4 51 IO14 DIO5n V11 IO LVDS108n LVDS85n LVDS108n – VREF1B4 4 46 IO26 – V12 IO LVDS107p LVDS84p LVDS107p – VREF1B4 4 23 IO5 DIO2p V13 IO LVDS105p LVDS82p LVDS105p DQ0B5 VREF0B4 4 30 IO21 DB2, DIO6n V15 IO LVDS98p LVDS78p LVDS98p DQ0B1 VREF0B4 4 18 IO17 DB6, DIO5n P9 IO VREF1B4 VREF1B4 VREF1B4 – VREF1B4 3 & 4 29 IO7 IOVREF1



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5.4.3 FPGA↔ Daughter Card Clock Signal Pin Outs Pin

Number Bank

Number Pin

Function Optional Pin

Function I/O Signal Name I/O Circuit Function Signal Level K4 1 IO PLL1_OUTp DC_CLK_OUTp Clock Out to all Daughter Cards, pin 35 As required for Daughter Card(s) K5 1 IO PLL1_OUTn DC_CLK_OUTn Clock Out to all Daughter Cards, pin 33 As required for Daughter Card(s)

5.5 Test Point Connections Two test point pads are provided for testing IP. They are located on the right side of the board between the Daughter Card headers CN7 and CN8. These two test pads are directly connected to two pins on the FPGA. Note: There is NO ESD protection on these pads.

FPGA ↔ Test Point Connections Pin

Number Pin

Function Optional Function EP1C4



VREF Bank IO Signal

P7 IO LVDS123n LVDS97n LVDS123n VREF2B4 Upper test point V6 IO LVDS124p LVDS98p LVDS124p VREF2B4 Lower test point

Chapter 6 : Configuration Circuits There are three methods to configure (that is, load IP into) the FPGA: JTAG connector (CN2). Contents of the on-board EEProm serial memory chip. Host CPU over the PCI-104 bus. The contents of the serial EEProm can be loaded either from the Host CPU over the PCI-104 bus, or via the ISP connector (CN1). The FPGA-PCI104 Configuration Controller manages all the non-JTAG4 configuration processing and data flow, as directed by software on the Host CPU over the PCI-104 bus. The Host CPU thus has full control of the FPGA configuration process. The Configuration Controller is implemented in a factory-programmed CPLD. Logically, the Configuration Controller is located between the FPGA, the serial EEProm, the ISP connector, and the Host CPU (see the Block Diagram in the Appendix). By setting and clearing the appropriate bits in the Configuration Controller, the Host CPU can enable the FPGA’s Active Serial configuration mode5, where the FPGA automatically reads in the configuration bit stream from the serial EEProm. Or, the CPU can put the FPGA in Passive Serial mode, in order to load the configuration bit stream directly into the FPGA from the Host CPU. The Active Serial FPGA configuration process occurs automatically at power-up of the FPGA-PCI104 board, or when the host CPU sets/clears the appropriate bits in the Configuration Controller. 5 See the Cyclone Data Handbook, Chapter 13.



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The following diagram shows the top-level schematic of the factory-standard Configuration Controller, for reference.

FPGA-PCI104 Configuration Controller Schematic



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6.1 Configuration Controller Registers The Host CPU interface to the Configuration Controller is two I/O memory mapped 8-bit read-write registers (3 bits which contain status info from the FPGA’s status pins are read-only). The Configuration Controller registers are located in one of the 4 PCI address blocks (Chip Select 0) provided by the PCI9030 chip; the specific addresses for CS0x are determined during the power-up configuration of the PCI9030, either from the on-board NVRAM for that chip, or by the operating system’s plug-n-play configuration process.

Controller Register 0* Bit

Number Bit Name Default Value

0 Host Data Clock 0 1 Host Data 0 2 Host Chip Select 1 3 EEProm Data Mode 0 4 FPGA Data Mode 0 5 FPGA Chip Enable 0 6 FPGA Configure 1 7 FPGA Status **

Controller Register 1*

Bit Number Bit Name Default

Value 0 FPGA Configuration Mode Select 0 0 1 FPGA Configuration Mode Select 1 0 2 FPGA Clear 1 3 FPGA Output Enable 1 4 FPGA Clock User 0 5 (not used) - 6 FPGA Configuration Done ** 7 FPGA Initialization Done **

* offset from base address ** read only

6.1.1 Host Data Clock – Register 0 bit 0 When the EEProm Data Mode bit is set to “1”, the Host Data Clock bit is the clock source for the data being loaded into the EEProm. When the FPGA Data Mode bit is set to “1”, the Host Data Clock bit is the clock source for the configuration data being loaded into the FPGA (EEProm Data Mode bit and the FPGA Data Mode bit should never be set to “1” at the same time) Note: The Host Data Clock bit should normally be left at the value of “0”, except during host-driven read/write of the EEProm or configuration of the FPGA.



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6.1.2 Host Data – Register 0 bit 1 When the EEProm Data Mode bit is set to “1”, the Host Data bit is the source for data being loaded into the EEProm. When the FPGA Configure Mode bit is set to “1”, the Host Data bit is the source for the configuration data being loaded into the FPGA (EEProm Data Mode bit and the FPGA Data Mode bit should never be set to “1” at the same time) The Host Databit should normally be left at the value of “0”, except during host-driven read/write of the EEProm or configuration of the FPGA.

6.1.3 Host Chip Select – Register 0 bit 2 When the EEProm Data Mode bit is set to “1”, the Host Chip Select bit drives the Chip Select pin of the EEProm. The Host Chip Select bit should normally be left at the value of “1”, except during host-driven read/write of the EEProm.

6.1.4 EEProm Data Mode – Register 0 Bit 3 1. When the EEprom Data Mode bit is “0”, the EEProm can be read/written from the FPGA (i.e.,

during power-on/RESET Active Serial configuration, or as a serial memory for IP in the FPGA), or via a ByteBlaster II cable plugged onto the ISP connector (CN1).

2. When the EEprom Data Mode bit is “1”, the PCI-104 Host CPU is the source of the bit stream

to be loaded into the EEProm.

6.1.5 FPGA Data Mode – Register 0 Bit 4 1. When the FPGA Data Mode bit is “0”, and the FPGA Configuration Mode Select 0/1 bits are

set for Active Serial Configuration mode, and the FPGA Configure bit is momentarily set to “0” and then back to “1”, the FPGA will load the configuration bit stream from the EEProm.

2. When the FPGA Data Mode bit is “1”, and the FPGA Configuration Mode Select 0/1 bits are

set for Passive Serial configuration mode, and the FPGA Configure bit is momentarily set to “0” and then back to “1”, the PCI-104 host CPU is the source of the configuration bit stream to be loaded into the FPGA, using the Host Data and Host Data Clock bits.

6.1.6 FPGA Chip Enable – Register 0 Bit 5 The FPGA is enabled when the FPGA Chip Enable bit is set to “0”. The FPGA Chip Enable bit should normally be left at the value of “0”, except during Host CPU configuration of the FPGA.

6.1.7 FPGA Configure – Register 0 Bit 6 A configuration sequence of the FPGA is initiated when the FPGA Configure bit is set to “0”, then back to“1”. The FPGA Configure bit should normally be left at the value of “1”, so the FPGA will be in User Mode, except when initiating a configuration sequence.



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6.1.8 FPGA Status – Register 0 Bit 7 The FPGA Status bit is a read-only copy of the nSTATUS pin of the FPGA. The functions of this pin are defined in the Cyclone Data Handbook.

6.1.9 FPGA Configuration Mode Select 0, 1 – Register 1 Bits 0, 1 The FPGA Configuration Mode Select 0 and 1 bits define the configuration mode of the FPGA.

FPGA Configuration Mode Select Bits Mode Bit Number 1 0 FPGA Configuration Mode

0 0 Active Serial 0 1 Passive Serial 1 0 not valid Value

1 1 not valid

6.1.10 FPGA Clear – Register 1 Bit 2 The FPGA Clear bit drives the nDEV_CLR pin of the FPGA. When the “device-wide reset” function of the nDEV_CLR pin is enabled6, setting the FPGA Clear bit to “0” results in all the registers on the FPGA being cleared. Normally, this bit should be left at the default value of “1”. Alternatively, when the nDEV_CLR function of the nDEV_CLR pin is disabled, the FPGA Clear bit can then be used as a 1-bit wide communication channel from the Host CPU to the FPGA.

6.1.11 FPGA Output Enable – Register 1 Bit 3 The FPGA Output Enable bit drives the DEV_OE pin of the FPGA. When the “device-wide output enable” function of the DEV_OE pin is enabled, setting the FPGA Output Enable bit to “0” results in all I/O pins on the FPGA being tri-stated. Normally, the FPGA Output Enable bit should be left at the value of “1”. Alternatively, when the DEV_OE function of the DEV_OE pin is disabled, the FPGA Output Enable bit can then be used as a 1-bit wide communication channel from the Host CPU to the FPGA.

6.1.12 FPGA Clock User – Register 1 Bit 4 The FPGA Clock User bit drives the CLKUSR pin of the FPGA. If the “user-supplied start-up clock” function of the CLKUSR pin is enabled, the FPGA Clock User bit provides the clock signal for the FPGA during Active Serial configuration. Alternatively, when the CLKUSR function of the FPGA pin is disabled, the FPGA Clock User bit can then be used as a 1-bit wide communication channel from the Host CPU to the FPGA.

6.1.13 Register 1 Bit 5 This bit has no function. Its value when read will be undefined.

6 The functions of the FPGA’s optional-function pins are defined by bits in the configuration bit stream.



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6.1.14 FPGA Configuration Done – Register 1 Bit 6 The FPGA Configuration Done bit is a read-only copy of the CONF_DONE pin of the FPGA. When this bit is “1”, the FPGA has completed the loading of a configuration bit stream (see Chapter 13 of the Cyclone Data Handbook for details).

6.1.15 FPGA Initialization Done – Register 1 Bit 7 The FPGA Initialization Done bit is a read-only copy of the INIT_DONE pin of the FPGA. When the INIT DONE function of the FPGA is enabled, the FPGA Initialization Done bit “1” indicates the FPGA has completed the initialization sequence (see Chapter 13 of the Cyclone Data Handbook for details). Alternatively, if the INIT_DONE function of the FPGA is not enabled, the FPGA Initialization Done bit can be used as a 1-bit wide communication channel from the FPGA to the Host CPU.

6.2 FPGA Configuration Pins The following pins on the FPGA are involved in the configuration of the part. Some have optional host ↔ FPGA communication functions, as noted in the Controller Bit definitions section. Some are pulled up to VccIO (3.3 VDC), or down to GND, as specified in the reference circuit diagrams in the Cyclone Data Handbook.

FPGA Configuration Pins Pin

Number Bank

Number Configuration

Function Alternate Function Direction VREF

Bank Pullup

or down To C3 1 INIT_DONE Output to host Out (open-drain) or IO D3 1 CLKUSR Input to host In or IO H7 1 DATA0 In 10K0 V3V3 J1 1 nCSO Out J2 1 nCONFIG In 10K0 V3V3 J7 1 nCE In 10K0 GND K2 1 nCEO Out K3 1 MSEL0 In 10K0 GND K6 1 ASDO Out K7 1 MSEL1 In 10K0 GND L1 1 DCLK In (Passive Serial) or Out (Active Serial) 10K0 V3V3 B3* 2 DEV_OE Input from host In or IO VREF2B2 10K0 VIO2 C4* 2 DEV_CLRn Input from host In or IO VREF2B2 10K0 VIO2 J17 3 TDI In 1K0 V3V3 K13 3 TDO Out 1K0 V3V3 K14 3 TMS In 1K0 V3V3 K17 3 CONF_DONE Bidirectional (open-drain) 10K0 V3V3 K18 3 TCK In 1K0 GND L12 3 nSTATUS Bidirectional (open-drain) 10K0 V3V3

*Note: since these two pins are in Bank 2, they are not powered unless a supply voltage is connected to the Power In pins of at least one of the Bank 2 Daughter Card headers (left-side, CN4 & 5). If no Daughter Cards are installed on the left-side D-C headers, then a connector-only “power jumpering” Daughter Card should be installed (available from Tri-M, or the user may easily make their own).

Note: all the Configuration signals, except for the JTAG signals, go through the Configuration Controller chip, and so the passage of those signals may be affected by the PCI-104 bus controlled ISP clock/data steering functions of the Configuration Controller. The Configuration Controller automatically enables a direct path for the ISP clock & data signals, between the FPGA and the EEProm and the ISP connector, whenever a ByteBlaster II cable is plugged in to the ISP connector.



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Chapter 7 : PCI Bus Configuration The PLX Technology PCI9030 PCI Bus I/O Accelerator provides all PCI bus interface functions for the FPGA-PCI104 board.

7.1 Factory-Default Configuration The power-on default PCI Device configuration of the FPGA-PCI104 board is defined by the PCI9030, during the normal PCI Bus Configuration Cycle. The specific Device Capabilities reported by the PCI9030 are controlled by certain registers in the PCI9030. The default power-on contents of many of these registers are loaded from a 4Kbit serial EEPROM chip (IC9) on the FPGA-PCI104. This chip is connected directly to the PCI9030; the lower portion of its address space contains the default definitions of the control registers in the PCI9030. The following figures show the factory-default contents of the EEPROM (these figures were obtained with the PLXMon tool, which can be obtained from PLX Technology). Only those settings which are different than the normal defaults defined in the PCI9030 Data Book are shown here. Note that many of these settings can be re-defined by the user, as desired.



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7.1.1 PCI Address Space 0 This is the space used by the FPGA-PCI104’s Configuration Controller. It is defined to be a 4-byte PCI I/O space, at Local Bus Address 0x1020, with relatively conservative timing values and only minimal PCI bus features. All PCI accesses to the Controller must be done in this space.



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7.1.2 PCI Address Space 1 This is one of the 3 spaces available for use by the Cyclone FPGA. It is defined to be a 16-byte PCI I/O space, at Local Bus Address 0x1000, with relatively conservative timing values and only minimal PCI bus features.



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7.1.3 PCI Address Space 2 This is one of the 3 spaces available for use by the Cyclone FPGA. It is defined to be an 8 KB PCI Memory space, 32-bits wide, at Local Bus Address 0x0000, with relatively conservative timing values and only minimal PCI bus features.



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7.1.4 PCI Address Space 3 This is one of the 3 spaces available for use by the Cyclone FPGA. This space is not enabled by the factory-default PCI9030 register settings.

7.1.5 PCI Expansion ROM Space This space is not used on the FPGA-PCI104, and is not enabled by the factory-default PCI9030 register settings.

7.1.6 GPIO Control

These settings enable the CS2 Chip Select pin, in addition to the PCI9030’s normal default settings. If it is desired to enable the CS3 space, or to use the alternate WAIT function of the GPIO1 pin ot he LLOCK function of GPIO1, similar changes in the respective GP I/O sections will need to be made.



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7.2 Typical PCI Bus Configuration after Power-On The following figures show a typical PCI configuration of the FPGA-PCI104 board (which has the factory-default EEPROM setting shown in the previous section), after the host system’s PCI BIOS has completed a PCI Bus Configuration Cycle and the system is up and running (the system in use was an x86 system running Windows® 2000).

7.2.1 PCI9030 PCI Configuration Registers

The above shows that the FPGA-PCI104, through the PCI9030, appears on the PCI Bus in 5 address spaces. The first two, Base Address 0 & 1, are the PCI9030 itself. Details on the meaning of the values shown above can be found in the PCI9030 Data Book. Base Address 2 is the FPGA-PCI104’s Configuration Controller. Base Addresses 3 & 4 are the first two of the spaces available for use by the Cyclone FPGA. Base Addresses 2 & 3 are PCI I/O spaces; Base Address 4 is PCI Memory. While it is possible to change some of the above registers at run time (with PLXMon or the user’s own software), it is not recommended. For example changes in the BAR registers will require a PCI bus BIOS re-scan in order to cause them to take effect, which may affect other parts of the system adversely.



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7.3 PCI9030 Local Configuration Registers

The above shows that the PCI9030’s Local Bus is configured to enable the 3 defined PCI BASE Address Spaces – i.e., Configuration Controller, plus 2 spaces for the FPGA – and that the width, length, timing & PCI features of each of those matches with what was defined in the factory-default EEPROM settings. As with the PCI9030’s PCR registers, it is possible to change some of the above registers at run time (with PLXMon or the user’s own software). Some changes are valid and will take effect immediately; for example, changing wait sate settings in an address space. Others are not recommended, or will have no effect. For example, changes in the Bus Descriptor for a space which has not been defined in a BAR register will have no effect.



34

Appendix

Cyclone FPGA

4K Logic Elements(Opt 12K/20K LEs)

275 MHz(Opt 320/405 MHz)

Commercial Temperature(Opt Industrial)

FPGA-PCI104 Board Block Diagram

PCI-104 Bus

FPGA/EEPROMConfiguration Controller

PC

I Bus

I/O D

augh

ter C

ards

I/O D

augh

ter C

ards

PowerRegulators

External PowerConnector(6-18 VDC)

Vio-IN1(1.2-3.3 VDC)

60 p

in s

ocke

t60

pin

soc

ket

3 I/O

25 I/O

25 I/O

Vio-IN2(1.2-3.3 VDC)

60 p

in s

ocke

t

25 I/O

25 I/O

60 p

in s

ocke

t

3 I/O

Vio-OUT

Vio-OUT

EthernetConnector &Transformer(opt. 10/100

or10/100/1000)

I2C/SmBusI/O

ExternalClockOSCInput

(SMB)

Silicon SerialNumber

&RTC

PCIInterface

Loca

l Bus

FPGAConfiguration

EEPROM

JTAGConnector

ISPConnector

Vio-OUT

Vcore(1.5 VDC)

Vio-OUT(3.3 VDC)

ClockOSC

60 MHz

Alternate I/O Daughter Cards:- ¼ size (max. 4)- ½ size horizontal (max. 2)- ½ size vertical (max. 2)- full size- PC/104 size

Configuration

V2.1 May 30, 2005 DTO

fpga-pci104 manual - tri-m · o the fpga-pci104 is based on the altera® cyclone™ ep1c fpga...

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