fpga technology overview
DESCRIPTION
FPGA Technology Overview. Carl Lebsack. * Some slides are from the “Programmable Logic” lecture slides by Dr. Morris Chang. What’s an FPGA?. FPGA – Field Programmable Gate Array. Logic. Standard Logic. ASIC. Gate Arrays. Programmable Logic Devices. Cell-Based ICs. Full custom ICs. - PowerPoint PPT PresentationTRANSCRIPT
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FPGA Technology Overview
Carl Lebsack
* Some slides are from the “Programmable Logic” lecture slides by Dr. Morris Chang
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What’s an FPGA?
FPGA – Field Programmable Gate Array
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Standard
Logic
Logic
ASIC
Full custom
ICs
Cell-Based
ICs
Gate
Arrays
Programmable
Logic Devices
FPGAsCPLDsSPLDs FPICs
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How do you make a “Programmable” circuit?One time programmable Fuses (destroy internal links with current) Anti-fuses (grow internal links) PROM
Reprogrammable EPROM EEPROM Flash SRAM - volatile
} non-volatile
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How do you program an FPGA?
Create a circuit design Graphic circuit toolVerilogVHDLAHDL
Compile the design for the selected deviceDownload the compiled configuration
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FPGAs offer many advantages over ASICs
Small development overhead
No NRE (non-recurring engineering) costs
Quick time to market
No minimum quantity order
Reprogrammable
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What are the Guts of an FPGA?
Basic ComponentsLUT (look-up-table)Flip-FlopsMultiplexors I/O BlocksProgrammable switching matrices InterconnectClocks
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Configurable Logic Blocks
I/O Blocks
Programmable Interconnects
Xilinx FPGA Structure
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CMOS SRAM Cell
Read orWrite
Data
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3-LUT
01101001
input[0:2]
output
config_in
clock
config_out
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2 Slice CLB
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LE
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LAB
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DIBCKE
CLB0
X
Y
CE A
D R
DIBCKE
CLB1
X
Y
CE A
D R
DIBCKE
CLB2
X
Y
CE A
D R
DIBCKE
CLB3
X
Y
CE A
D R
SwitchingMatrix
Global Vertical
Long Line
GeneralPurpose Lines
Hor izontalLong Line
DirectConnections
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IOB
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More Guts
Additional componentsRAM blocksDedicated multipliersTri-state buffersTransceiversProcessor coresDSP blocks
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Dedicated Arithmetic Structures in FPGAs
AlteraXilinx
QuickLogic
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Power PC in Virtex-II Pro
• Embedded 300+ MHz Harvard Architecture Core• Low Power Consumption: 0.9 mW/MHz• Five-Stage Data Path Pipeline• Hardware Multiply/Divide Unit• Thirty-Two 32-bit General Purpose Registers• 16 KB Two-Way Set-Associative Instruction Cache• 16 KB Two-Way Set-Associative Data Cache• Memory Management Unit (MMU)
- 64-entry unified Translation Look-aside Buffers (TLB)- Variable page sizes (1 KB to 16 MB)
• Dedicated On-Chip Memory (OCM) Interface• Supports IBM CoreConnect™ Bus Architecture• Debug and Trace Support• Timer Facilities
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Excalibur Embedded Solution
ExcaliburProcessor
Logic
HighPerformance
I/O
Memory
Complete SOPC Solution
• Integrates Embedded Processors With Programmable Logic Device
• Delivers System-on-a-Programmable-Chip (SOPC)─ Programmable Flexibility
• PLD Hardware
• Embedded Software
─ Compute Performance
• High Performance Processor
• Data Path Hardware
─ Customer Configuration
• Microprocessor Peripherals
• Hardware Logic
─ Faster Time-to-Market
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ARM in Excalibur
• Industry-standard ARM922T 32-bit RISC processor core operating up to 200MHz
─ ARMv4T instruction set with Thumb extensions
─ Memory management unit (MMU) included for real-time operating systems (RTOS) support
─ Harvard cache architecture with 64-way set associative separate 8-Kbyte instruction and 8-Kbyte data caches
• Embedded programmable on-chip peripherals
─ ETM9 embedded trace module to assistant software debugging
─ Flexible interrupt controller
─ Universal asynchronous receiver/transmitter (UART)
─ General-purpose timer
─ Watchdog timer
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Altera DSP-Block-Configuration Options and Features
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FPGAs come in a wide variety
Xilinx Slices/CLBs PowerPC cores
Altera LEs/LABs ARM cores/Softcores
Numbers of subcomponents varies
Special features vary
Manufacturers use own terminology
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Feature EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 EP1S120
Logic Elements (LEs) 10,570 18,460 25,660 32,470 41,250 57,120 79,040 114,140
M512 RAM Blocks( 512 Bits + Parity)
94 194 224 295 384 574 767 1,118
M4K RAM Blocks(4 Kbits + Parity)
60 82 138 171 183 292 364 520
M512 RAM Blocks(512 Kbits + Parity)
1 2 2 4 4 6 9 12
Total RAM bits 920,448 1,669,248 1,944,576 3,317,184 3,423,744 5,215,104 7,427,520 10,118,016
DSP Blocks 6 10 10 12 14 18 22 28
Embedded Multipliers 48 80 80 96 112 144 176 224
PLLS 6 6 6 10 12 12 12 12
Maximum User I/O Pins 426 586 706 726 822 1,022 1,238 1,314
Engineering Sample Availability
NowUse
ProductionUse
ProductionN/A Now N/A Now 2003
Production Device Availability
March2003
Now Now NowMarch 2003
April
2003
January 2003
2003
Stratix Device Overview
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FPGA Design
Main components are generally done as custom designs
Layout is very regular and automation could assist in cell placement
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Stratix FPGA Layout
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year 1995 1996 1997 2000 2003 2004 ?
Technology 0.6µ 0.35 µ 0.25 µ 0.18 µ 0.13 µ 0.07µ
Gate count 25K 100K 250K 1 M
100K LC*
8Mb RAM
400 18X18 multipliers
Transistor count
3.5M 12M 23M 75M 430M 1B
PLD device density and VLSI technology
*note: Xilinx Virtex-II Pro XC2VP100 (9/16/2003)
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More Information
www.xilinx.com
www.altera.com