fpgas with 28gb/s transceivers built with … interconnect microstrip layout with side shields page...
TRANSCRIPT
© Copyright 2012 Xilinx .
Ephrem Wu and Suresh Ramalingam
FPGAs with 28Gb/s Transceivers Built with
Heterogeneous Stacked-Silicon Interconnects
© Copyright 2012 Xilinx .
Outline
Page 2
1 Key Application
2 Heterogeneous Stacked-Silicon FPGA Family
3 Stacked-Silicon Packaging
4 Two Types of Stacked-Silicon Interconnects
© Copyright 2012 Xilinx .
400Gb/s Line Card Application
Page 3
Line Card Switch Card
Con
ne
cto
r
Con
ne
cto
r
Virtex-7 HT Network
Processor Switch Fabric
Packet Queues and
Lookup Memory
(SRAM, TCAM,
DRAM)
4 x
100G
Op
tical
Inte
rface
Fabric Interface
Up to 72 x 13.1 Gb/s
GTH Transceivers Up to 16 x 28 Gb/s
GTZ Transceivers
© Copyright 2012 Xilinx .
Heterogeneous Stacked-Silicon FPGAs Interposer Floorplans
Page 4
XC7VH870T XC7VH580T XC7VH290T
FPGA
GT
H
GT
H
GTZ-IC (8x28Gb/s)
FPGA G
TH
GT
H
FPGA
GT
H
GT
H
FPGA
GT
H
GT
H
FPGA
GT
H
GT
H
FPGA
GT
H
GT
H
GTZ (28G)
GTH (13G)
8
24
8
48
16
72
Network 2 x 100 Gb/s 2 x 100 Gb/s 4 x 100 Gb/s
GTZ-IC (8x28Gb/s)
GTZ-IC (8x28Gb/s)
GTZ-IC (8x28Gb/s)
© Copyright 2012 Xilinx .
XC7VH580T Under the Hood Industry’s First Heterogeneous FPGA
Page 7
GTZ-IC FPGA
Passive Silicon Interposer
Ceramic Package Substrate
FPGA
Microbumps
C4 Bumps
BGA Balls
© Copyright 2012 Xilinx .
Two Interconnect Types
Page 8
GTZ-IC FPGA
Passive Silicon Interposer
Ceramic Package Substrate
FPGA
Microbumps
C4 Bumps
BGA Balls
Through-Silicon
Via (TSV)
Type I
Between IC and Package
Type II
Between two ICs
© Copyright 2012 Xilinx .
Packaging, Assembly, and Test
Page 9
Package Substrate
28nm FPGA & Interposer
Bump, Die separation
Joining, & Assembly
Final Test of Packaged Part
Top Dice, Interposer, & Package
© Copyright 2012 Xilinx .
Type II Interconnects Inter-IC Interconnect Microstrip Layout with Side Shields
Page 12
IC 2 IC 1
© Copyright 2012 Xilinx .
Type II Interconnects Inter-IC Interconnect Microstrip Layout with Side Shields
Page 13
Microbump
Pad IC 2 IC 1
© Copyright 2012 Xilinx .
Type II Interconnects Inter-IC Interconnect Microstrip Layout with Side Shields
Page 14
Microbump
Pad IC 2 IC 1
Microbump
© Copyright 2012 Xilinx .
Type II Interconnects Inter-IC Interconnect Microstrip Layout with Side Shields
Page 15
Microbump
Pad IC 2 IC 1
Microbump
Microbump
Pad
© Copyright 2012 Xilinx .
Type II Interconnects Inter-IC Interconnect Microstrip Layout with Side Shields
Page 16
Interposer (Dimensions Not to Scale to Show Interconnect Cross Section)
Clock
or
Signal
Microbump
Pad IC 2 IC 1
Microbump
Microbump
Pad
© Copyright 2012 Xilinx .
Type II Interconnects Inter-IC Interconnect Microstrip Layout with Side Shields
Page 17
Interposer (Dimensions Not to Scale to Show Interconnect Cross Section)
Shields
Clock
or
Signal
Microbump
Pad IC 2 IC 1
Microbump
Microbump
Pad
© Copyright 2012 Xilinx .
RC Static Timing Analysis for Productivity Calibrated RC-Based STA Against RLC-Based SPICE
Page 19
GND
Type II Signal
GND
Type II Signal
GND
Type II Signal
GND
…
RLC
RC
SPICE
Static Timing
Analyzer
© Copyright 2012 Xilinx .
Summary
Page 20
1 Presented industry’s first heterogeneous 3D FPGA.
2 FPGA & GTZ-IC create three scalable products.
3 Reviewed stacked-silicon packaging & supply chain.
4 Showed Type I signaling: 28 Gb/s TX over TSVs.
5 Lacked 3D timing tools for Type II signals. Leveraged STA tools calibrated with RLC SPICE runs.