fplds
DESCRIPTION
Lec 22(1)TRANSCRIPT
Three FPLD Types• Simple Programmable Logic Device (SPLD)
– LSI device
– Less than 1000 logic gates
• Complex Programmable Logic Device (CPLD)– VLSI device
– Higher logic capacity than SPLDs
• Field Programmable Gate Array (FPGA)– VLSI device
– Higher logic capacity than CPLDs
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ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
Three FPLD Types• Simple Programmable Logic Device (SPLD)
– PLA or PAL
– Fixed internal routing, deterministic propagation delays
• Complex Programmable Logic Device (CPLD)– Multiple SPLDs onto a single chip
– Programmable interconnect
• Field Programmable Gate Array (FPGA)– An array of logic blocks
– Large number of gates, user selectable interconnection, delays depending on design and routing
– A high ratio of flip-flops to logic resources
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ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
SPLDs
• SPLDs = Simple PLDs• Popular SPLD Architecture Types
– Programmable Logic Array, PLA– Programmable Array Logic, PAL (Vantis)– General Array Logic, GAL (Lattice)– others
• Architecture Differences– AND versus OR implementation– Programmability (e.g., EE)– Fundamental logic block
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ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
SPLDs• We have already taken a close
look at SPLDs• A PLA-like SPLD is illustrated
at left– PAL and GAL devices offered
a somewhat better solution
• SPLDs are good alternative to using SSI and MSI devices– Especially if re-programmable
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Logic Functions
Product Terms
Sums
ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
SPLDs• Conventional programmable logic
– PALs, PLAs, GALs– standard parts like GAL22V10 and PAL16R4 are available from
multiple vendors
• Includes programmable logic cells to a limited degree (programming options in I/O cells, may have fixed AND/OR gates for logic), limited routing network
• Lowest density of all programmable devices, however, can offer very high performance
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ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
• SPLDs have nearly replaced TTL logic which was the dominate approach to logic implementation
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How to Expand SPLD Architecture?• Increase number of inputs and outputs in a
conventional PLD?– e.g., 16V8 → 20V8 → 22V10
– Why not → 32V16 → 128V64 ?
• Problems: – n times the number of inputs and outputs requires n2 as
much chip area – too costly
– logic gets slower as number of inputs to AND array increases
ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
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How to Expand SPLD Architecture?• Solution:
– Multiple SPLDs with a relatively small programmable interconnect
– Less general than a single large PLD
– Can use software “fitter” to partition into smaller PLD blocks
ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
CPLD Architecture
CPLDs• PALs and GALs are available only in small sizes
– equivalent to a few hundred logic gates
• For bigger logic circuits, complex PLDs or CPLDs can be used.
• CPLDs contain the equivalent of several PALs/GALs – linked by programmable interconnections– all in one integrated circuit (IC)
• CPLDs can replace thousands, or even hundreds of thousands, of individual logic gates – increased integration density
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ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
Complex PLDs• Some CPLDs are programmed using a PAL
programmer, but this method becomes inconvenient for devices with hundreds of pins.
• A second method of programming is to solder the device to its printed circuit board, then feed it with a serial data stream from a personal computer.
• The CPLD contains a circuit that decodes the data stream and configures the CPLD to perform its specified logic function.
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ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
• Xilinx, for example:• Xilinx CPLD devices that are cheaper and have fewer
gates than Xilinx FPGAs• Meant for interfacing rather than heavy computation• Built-in flash memory
– Compare to FPGA which needs external configuration memory
• Xess board has XC9572XL part– Approximately $2-$7 in quantities of one – vs. ~$15-20 for the Spartan2 FPGA on the board– Larger quantities much lower– 1600 gates, 72 registers
Complex PLDs versus FPGAs
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ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
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CPLD Architecture• Simplified CPLD
architecture• Small number of largish
PLDs (e.g., “36V18”) on a single chip
• Programmable interconnect between PLDs
• Large number of I/O blocks
• Large number of pins
CPLDs• Composition of Complex PLDs
– typically composed of 2-64 SPLDs
– interconnected using sophisticated logic
– includes macrocells (more about these later)
– includes input/output blocks
• Economical for designing large systems• Fast – switching speed
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ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
CPLDs
• Complex PLD's have arrays of PLD's on one chip, with an interconnection matrix connecting them.
• Timing performance can be more predictable than FPGAs because of simpler interconnect structure.
• Density is normally less than most FPGAs (although high end CPLDs will have about the same density as low-end FPGAs).
ProgrammableLogic Devices
(FPLDs)
CPLDsSPLDs(e.g., PALs) FPGAs
• Performance of CPLDs is usually better than FPGAs, but depends on vendor, number of cells in CPLD, and compared FPGA.
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CPLD Families• Identical individual PLD blocks (Xilinx “FBs”) replicated
in different family members– Different number of PLD blocks
– Different number of I/O pins
Xilinx Xilinx XC9500 XC9500 CPLD CPLD SeriesSeries
Typical CPLD Packages• CPLDs are made using 2 to 64 SPLDs • Packages use 44-pins to over 200-pins (or more)
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Typical CPLD Packages• QFP = Quad Flat Package – A QFP is an IC package with leads extending from each of
the four sides.
– It is used primarily for surface mounting, no socketing
• TQFP = Thin Quad Flat Package • PQFP = Plastic Quad Flat Package • VQFP = Very small Quad Flat Package
• PLCC = Plastic Leaded Chip Carrier – A package related to QFP
– Similar but has pins with larger distance, curved up underneath a thicker body to simplify socketing
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CPLD Package Types• CSP = Chip Scale Package
– IC package with an area no greater than 1.2 times that of the die
• BGA = Ball Grid Array – A type of surface-mount packaging used for ICs
– Pins are replaced by balls of solder stuck to the bottom of the package
– The device is placed on a PCB that carries copper pads in a pattern that matches the solder balls
– The assembly is then heated causing the solder balls to melt
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CPLD Families• Many CPLDs have fewer
I/O pins than macrocells– “Buried” Macrocells – provide
needed logic terms internally but these outputs are not connected externally
– IC package size dictates number of I/O pins but not the total number of macrocells
– Typical CPLD families have devices with differing resources in the same IC package
Xilinx CPLDs• Notice overlap in resource availability in a particular
package.
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XC9572 CPLD Part Numbers• The part number for Xilinx CPLD devices includes
information as follows:
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XC9500 CPLD Block Diagram• The XC9500 CPLD
family provides advanced in-system programming and test capabilities for high performance, general purpose logic integration.
• All devices are in-system programmable for a minimum of 10,000 program/erase cycles.
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9500-Family Function Blocks (FBs)• 18 macrocells per FB• 36 inputs per FB (partitioning challenge, but also
reason for relatively compact size of FBs)• Macrocell outputs can go to I/O cells or back into
switch matrix to be routed to this or other FBs
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9500-Series Macrocell• 18 macrocells per Function Block
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Up to 5 product termsUp to 5 product terms
Programmable inversion Programmable inversion or XOR product termor XOR product term
Global clock or product-term clockGlobal clock or product-term clock
Set controlSet control
Reset controlReset control
OE controlOE control
9500-Series Product-Term Allocator• Share terms from above and below
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programmableprogrammablesteeringsteeringelementselements
XC9500 Family
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• An I/O block is composed of input buffer, output buffer, multiplexer for the output control and grounding control
• Slew rate control is used to smooth the rising and the falling edges of the output pulse.
• Grounding control is used to make the input/output pin (I/O) an earth ground (noise suppression).
• Each input/output pin can handle a 24-mA current.
9500-Series I/O Block• OE Multiplexer (OE
MUX) controls an output enable or stop.
• It is controlled by the signal from the macrocell or the signal from the GTS (Global Three-State control) pin.
• There are four GTS in XC95216 and XC95288 two in the others.
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Switch Matrix for XC95108• Could be anything from a limited set of multiplexers to
a full crossbar– Multiplexer -- small, fast, but difficult fitting
– Crossbar -- easy fitting but large and slow
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Problems with CPLDs• Pin locking
– Small changes, and certainly large ones, can cause the fitter to pick a different allocation of I/O blocks and pinout
– Locking too early may make the resulting circuit slower or not fit at all
• Running out of resources– Design may “blow up” if it doesn’t all fit on a single
device
– On-chip interconnect resources are much richer than off-chip
– Larger devices are exponentially more expensive