fqu11p06 lcd transistor
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©2009 Fairchild Semiconductor Corporation
FQD11P06 / FQU11P0660V P-Channel MOSFET
General DescriptionThese P-Channel enhancement mode power field effecttransistors are produced using Fairchilds proprietary,planar stripe, DMOS technology.This advanced technology has been especially tailored tominimize on-state resistance, provide superior switchingperformance, and withstand a high energy pulse in theavalanche and commutation modes. These devices arewell suited for low voltage applications such as automotive,DC/DC converters, and high efficiency switching for powermanagement in portable and battery operated products.
Features -9.4A, -60V, RDS(on) = 0.185Ω @VGS = -10 V Low gate charge ( typical 13 nC) Low Crss ( typical 45 pF) Fast switching 100% avalanche tested Improved dv/dt capability
Absolute Maximum Ratings TC = 25°C unless otherwise noted
Thermal Characteristics
* When mounted on the minimum pad size recommended (PCB Mount)
Symbol Parameter FQD11P06 / FQU11P06 UnitsVDSS Drain-Source Voltage -60 VID Drain Current - Continuous (TC = 25°C) -9.4 A
- Continuous (TC = 100°C) -5.95 AIDM Drain Current - Pulsed (Note 1) -37.6 AVGSS Gate-Source Voltage ± 30 VEAS Single Pulsed Avalanche Energy (Note 2) 160 mJIAR Avalanche Current (Note 1) -9.4 AEAR Repetitive Avalanche Energy (Note 1) 3.8 mJdv/dt Peak Diode Recovery dv/dt (Note 3) -7.0 V/nsPD Power Dissipation (TA = 25°C) * 2.5 W
Power Dissipation (TC = 25°C) 38 W- Derate above 25°C 0.3 W/°C
TJ, TSTG Operating and Storage Temperature Range -55 to +150 °C
TLMaximum lead temperature for soldering purposes,1/8" from case for 5 seconds
300 °C
Symbol Parameter Typ Max UnitsRθJC Thermal Resistance, Junction-to-Case -- 3.28 °C/WRθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C/WRθJA Thermal Resistance, Junction-to-Ambient -- 110 °C/W
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D
G
I-PAKFQU Series
D-PAKFQD Series G SDG S
D
January 2009 QFET®
• RoHS Compliant
Rev. C6. January 2009
FQD
11P06 / FQU
11P06
Elerical Characteristics TC = 25°C unless otherwise noted
Notes:1. Repetitive Rating : Pulse width limited by maximum junction temperature2. L = 2.1mH, IAS = -9.4A, VDD = -25V, RG = 25 Ω, Starting TJ = 25°C3. ISD ≤ -11.4A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2%5. Essentially independent of operating temperature
Symbol Parameter Test Conditions Min Typ Max Units
Off CharacteristicsBVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -60 -- -- V∆BVDSS/ ∆TJ
Breakdown Voltage Temperature Coefficient
ID = -250 µA, Referenced to 25°C -- -0.07 -- V/°C
IDSS Zero Gate Voltage Drain CurrentVDS = -60 V, VGS = 0 V -- -- -1 µAVDS = -48 V, TC = 125°C -- -- -10 µA
IGSSF Gate-Body Leakage Current, Forward VGS = -25 V, VDS = 0 V -- -- -100 nAIGSSR Gate-Body Leakage Current, Reverse VGS = 25 V, VDS = 0 V -- -- 100 nA
On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA -2.0 -- -4.0 VRDS(on) Static Drain-Source
On-ResistanceVGS = -10 V, ID = -4.7 A -- 0.15 0.185 Ω
gFS Forward Transconductance VDS = -30 V, ID = -4.7 A (Note 4) -- 4.9 -- S
Dynamic CharacteristicsCiss Input Capacitance VDS = -25 V, VGS = 0 V,
f = 1.0 MHz
-- 420 550 pFCoss Output Capacitance -- 195 250 pFCrss Reverse Transfer Capacitance -- 45 60 pF
Switching Characteristics td(on) Turn-On Delay Time VDD = -30 V, ID = -5.7 A,
RG = 25 Ω
(Note 4, 5)
-- 6.5 25 nstr Turn-On Rise Time -- 40 90 nstd(off) Turn-Off Delay Time -- 15 40 nstf Turn-Off Fall Time -- 45 100 nsQg Total Gate Charge VDS = -48 V, ID = -11.4 A,
VGS = -10 V (Note 4, 5)
-- 13 17 nCQgs Gate-Source Charge -- 2.0 -- nCQgd Gate-Drain Charge -- 6.3 -- nC
Drain-Source Diode Characteristics and Maximum RatingsIS Maximum Continuous Drain-Source Diode Forward Current -- -- -9.4 AISM Maximum Pulsed Drain-Source Diode Forward Current -- -- -37.6 AVSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -9.4 A -- -- -4.0 Vtrr Reverse Recovery Time VGS = 0 V, IS = -11.4 A,
dIF / dt = 100 A/µs (Note 4)
-- 83 -- nsQrr Reverse Recovery Charge -- 0.26 -- µC
Rev. C6,January 2009
FQD
11P06 / FQU
11P06
©2009 Fairchild Semiconductor Corporation
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.010-1
100
101
150 Notes :※
1. VGS = 0V 2. 250µs Pulse Test
25
-I DR
, Rev
erse
Dra
in C
urre
nt [
A]
-VSD , Source-Drain Voltage [V]0 10 20 30 40 50
0.0
0.2
0.4
0.6
0.8
Note : T※ J = 25
VGS = - 20V
VGS = - 10V
RD
S(on
) [Ω
],D
rain
-Sou
rce
On-
Res
ista
nce
-ID , Drain Current [A]
2 4 6 8 1010-1
100
101
150
25
-55 Notes :※
1. VDS = -30V 2. 250µs Pulse Test
-I D , D
rain
Cur
rent
[A]
-VGS , Gate-Source Voltage [V]10-1 100 101
10-1
100
101
VGSTop : - 15.0 V - 10.0 V - 8.0 V - 7.0 V - 6.0 V - 5.5 V - 5.0 VBottom : - 4.5 V
Notes :※
1. 250µs Pulse Test 2. TC = 25
-I D,
Dra
in C
urre
nt [A
]
-VDS, Drain-Source Voltage [V]
0 2 4 6 8 10 12 140
2
4
6
8
10
12
VDS = -30V
VDS = -48V
Note : I※ D = -11.4 A
-VG
S, G
ate-
Sour
ce V
olta
ge [V
]
QG, Total Gate Charge [nC]10-1 100 1010
200
400
600
800
1000
1200Ciss = Cgs + Cgd (Cds = shorted)Coss = Cds + CgdCrss = Cgd
Notes :※
1. VGS = 0 V 2. f = 1 MHz
Crss
Coss
Ciss
Cap
acita
nce
[pF]
-VDS, Drain-Source Voltage [V]
Typical Characteristics
Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics
Figure 3. On-Resistance Variation vs.Drain Current and Gate Voltage
Figure 4. Body Diode Forward Voltage Variation vs. Source Current
and Temperature
Figure 2. Transfer CharacteristicsFigure 1. On-Region Characteristics
Rev. C6, January 2009
FQD
11P06 / FQU
11P06
©2009 Fairchild Semiconductor Corporation
1 0 -5 1 0 -4 1 0 -3 1 0 -2 1 0 -1 1 0 0 1 0 11 0 -2
1 0 -1
1 0 0
N o te s :※
1 . Z θ J C( t ) = 3 .2 8 /W M a x .
2 . D u ty F a c to r , D = t1/ t 2 3 . T J M - T C = P D M * Z θ J C( t)
s in g le p u ls e
D = 0 .5
0 .0 2
0 .2
0 .0 5
0 .1
0 .0 1
Z θJC
(t), T
herm
al R
espo
nse
t 1 , S q u a re W a v e P u ls e D u ra t io n [s e c ]
25 50 75 100 125 1500
2
4
6
8
10
-I D, D
rain
Cur
rent
[A]
TC, Case Temperature [ ]100 101 102
10-1
100
101
102
DC
10 ms
1 ms
100 µs
Operation in This Area is Limited by R DS(on)
Notes :※
1. TC = 25 oC 2. TJ = 150 oC 3. Single Pulse
-I D, D
rain
Cur
rent
[A]
-VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 2000.0
0.5
1.0
1.5
2.0
2.5
Notes :※
1. VGS = -10 V 2. ID = -4.7 A
RD
S(O
N),
(Nor
mal
ized
)D
rain
-Sou
rce
On-
Res
ista
nce
TJ, Junction Temperature [oC]
-100 -50 0 50 100 150 2000.8
0.9
1.0
1.1
1.2
Notes :※
1. VGS = 0 V 2. ID = -250 µA
-BV D
SS, (
Nor
mal
ized
)D
rain
-Sou
rce
Brea
kdow
n Vo
ltage
TJ, Junction Temperature [oC]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Currentvs. Case Temperature
Figure 7. Breakdown Voltage Variationvs. Temperature
Figure 8. On-Resistance Variationvs. Temperature
Figure 11. Transient Thermal Response Curve
t1
PDM
t2
Rev. C5, October 2008
FQD
11P06 / FQU
11P06
©2008 Fairchild Semiconductor Corporation
©2008 Fairchild Semiconductor Corporation
Charge
VGS
-10VQg
Qgs Qgd
-3mA
VGS
DUT
VDS
300nF
50KΩ
200nF12V
Same Typeas DUT
Charge
VGS
-10VQg
Qgs Qgd
-3mA
VGS
DUT
VDS
300nF
50KΩ
200nF12V
Same Typeas DUT
VDS
VGS10%
90%
td(on) tr
t on t off
td(off) tfVDD
-10V
VDSRL
DUT
RG
VGS
VDS
VGS10%
90%
td(on) tr
t on t off
td(off) tfVDD
-10V
VDSRL
DUT
RG
VGS
EAS = L IAS2----
21 --------------------
BVDSS - VDD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
-10V DUT
RG
L
I D
t p
EAS = L IAS2----
21EAS = L IAS
2----21----21 --------------------
BVDSS - VDD
BVDSS
VDD
VDS
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
-10V DUT
RG
LL
I DI D
t p
Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
Unclamped Inductive Switching Test Circuit & Waveforms
Rev. C6, January 2009
FQD
11P06 / FQU
11P06
©2009 Fairchild Semiconductor Corporation
1 0 -5 1 0 -4 1 0 -3 1 0 -2 1 0 -1 1 0 0 1 0 11 0 -2
1 0 -1
1 0 0
N o te s :※
1 . Z θ J C( t ) = 3 .2 8 /W M a x .
2 . D u ty F a c to r , D = t1/ t 2 3 . T J M - T C = P D M * Z θ J C( t)
s in g le p u ls e
D = 0 .5
0 .0 2
0 .2
0 .0 5
0 .1
0 .0 1
Z θJC
(t), T
herm
al R
espo
nse
t 1 , S q u a re W a v e P u ls e D u ra t io n [s e c ]
25 50 75 100 125 1500
2
4
6
8
10
-I D, D
rain
Cur
rent
[A]
TC, Case Temperature [ ]100 101 102
10-1
100
101
102
DC
10 ms
1 ms
100 µs
Operation in This Area is Limited by R DS(on)
Notes :※
1. TC = 25 oC 2. TJ = 150 oC 3. Single Pulse
-I D, D
rain
Cur
rent
[A]
-VDS, Drain-Source Voltage [V]
-100 -50 0 50 100 150 2000.0
0.5
1.0
1.5
2.0
2.5
Notes :※
1. VGS = -10 V 2. ID = -4.7 A
RD
S(O
N),
(Nor
mal
ized
)D
rain
-Sou
rce
On-
Res
ista
nce
TJ, Junction Temperature [oC]
-100 -50 0 50 100 150 2000.8
0.9
1.0
1.1
1.2
Notes :※
1. VGS = 0 V 2. ID = -250 µA
-BV D
SS, (
Nor
mal
ized
)D
rain
-Sou
rce
Brea
kdow
n Vo
ltage
TJ, Junction Temperature [oC]
Typical Characteristics (Continued)
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Currentvs. Case Temperature
Figure 7. Breakdown Voltage Variationvs. Temperature
Figure 8. On-Resistance Variationvs. Temperature
Figure 11. Transient Thermal Response Curve
t1
PDM
t2
Rev. C6, January 2009
FQD
11P06 / FQU
11P06
©2008 Fairchild Semiconductor Corporation
©2009 Fairchild Semiconductor Corporation
Rev. C6, January 2009
FQD
11P06 / FQU
11P06Mechanical Dimensions
©2009 Fairchild Semiconductor Corporation
TO-252 (DPAK) (FS PKG Code 36)
1:1Scale 1:1 on letter size paper
Dimensions shown below are in: millimeters
Part Weight per unit (gram): 0.33
Rev. C6. January 2009
FQD
11P06 / FQU
11P06Mechanical Dimensions
Dimensions in Millimeters
I - PAK
©2009 Fairchild Semiconductor Corporation
Rev. I37
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* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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As used herein:1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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.
FQD
11P06 / FQU
11P06
Rev. C6. January 2009
©2009 Fairchild Semiconductor Corporation