fr5_ff_pass
DESCRIPTION
dTRANSCRIPT
MEMORY ELEMENTSFlip-flops and Latches
2
Interpret the following code:signal Y,D,En : std_logic;...........
-- the same with process
How a missing else is interpreted in hardware ? • Exactly as in software! The object should preserve its
value!• OK! But how?
Y <= D when En=‘1’; --else is missing
process (En,D)begin
if (En=‘1’) thenY <= D;
--else is missingend if;
end process;
D
En
D0D1S0
O
U22
MUX2
Y
3
This is a latch!
It is able to store a bit!
A latch is a memory
element.
In fact a latch is never implemented like this!
Recall!
D
En
D0D1S0
O
U22
MUX2
Y
R_bar
QS_bar
Q_bar
En
Y
Y_bar
D
An R-S latch!
4
When Q output will change its value?
The simulator executes the process when there is an event on En or D.
Event means a transition 0→1 or a transition 1→0.The 0→1 transition is called rising edge: ↑The 1→0 transition is called falling edge: ↓
--Latchprocess (En,D)begin
if (En=‘1’) thenQ <= D;
end if;end process;
The simulator executes the process when En↑, En↓, D↑ or D↓
Q <= D when:1. En↑ (0 →1) regardless D2. D↑ and En=‘1’3. D↓ and En=‘1’
En↓ has no effect
5
When the Q output will change its value?--Latchprocess (En,D) -–En↑↓, D↑↓begin
if (En=‘1’) thenQ <= D;
end if;end process;
Q
D Q
G
ILD
6
A small change: remove D from the process’ sensitivity list
process (En) -–En↑↓begin
if (En=‘1’) thenQ <= D;
end if;end process;--no longer equivalent to:Y <= D when En=‘1’;
Q
Q <= D only when En↑ (0 →1)regardless D
En↓ has no effect
7
So, what is this?
It’s a flip-flop!
Usually the control signal of a FF is named CLOCK and is abbreviated CLK:
process (En) -–En↑↓begin
if (En=‘1’) thenQ <= D;
end if;end process;
process (Clk)begin
if (Clk =‘1’) thenQ <= D;
end if;end process;
D Q
FD
8
Let’s simulate!
First behavioral:
Then post place and route:
process (Clk)begin
if (Clk =‘1’) then Q <= D;end if;end process;
It’s a Flip-flop!
It’s a Latch!
9
Why the two simulations disagree?
We’ve got a synthesis warning:==============================================================
* HDL Analysis *
==============================================================
Analyzing Entity <latch> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "D:/Users/John/JohnSchool/DisciplinaVHDL/Curs/FR11_FF/Latch/latch.vhd" line 40:
The following signals are missing in the process sensitivity list: D.
The synthesis adds D to the process’ sensitivity list.
process (Clk )begin
if (Clk =‘1’) then
Q <= D;end if;
end process;
,D)The flip-flop becomes a
latch!
10
Event:
Usually, the synthesis tool ignores the sensitivity list and builds its own list consisting of all signals appearing in the right side of an assignment, if conditions and case selectors.
Consequently, there will be no difference between a Latch description and a FF description.
We need a method to describe Flip-flops!
Solution:
We’ll use a member function for signal class called event.
signal a_signal : std_logic;.....
In synthesis:
a_signal’event returns true if there is an event on a_signal in the current simulation cycle.
11
Event (cont):
a_signal’event returns TRUE for both edges: a_signal↑↓
To select the rising edge only:a_signal’event and a_signal=‘1’
or use the function
rising_edge(a_signal)
To select the falling edge only:a_signal’event and a_signal=‘0’
or use the function
falling_edge(a_signal)
12
Flip-flop description with event:
Latch description:
process (Clk, D) -–Clk↑↓, D↑↓--process (Clk) -–Clk↑↓ works as wellbegin
if rising_edge(Clk) thenQ <= D;
end if;end process;--equivalent to:
Q <= D when rising_edge(Clk);
Q <= D only when Clk↑ (0 →1)
Clk↓, D↑, D↓ are rejected
--Latchprocess (En,D) -–En↑↓, D↑↓begin
if (En=‘1’) thenQ <= D;
end if;end process;
13
Restriction on edge condition:1. In a process, a single edge condition must be tested.
Otherwise we describe something that reacts on many edges:
No hardware counterpart!
signal D1, D2, Clk1, Clk2, Q........................process (Clk1, Clk2 )begin
if ridsing_edge(Clk1) thenQ <= D1;
end if;
if ridsing_edge(Clk2) thenQ <= D2;
end if;end process;
ERROR:Xst:827 - "D:/Users/John/JohnSchool/DisciplinaVHDL/Curs/FR11_FF/Latch/latch.vhd" line 40: Signal Q cannot be synthesized, bad synchronous description.
14
Restriction on edge condition (cont):1. In a process, the edge condition must be the LAST
condition tested in an if elsif elsif instruction. Otherwise we describe something that reacts on many edges:
No hardware counterpart!
signal D, Clk, Q........................process (Clk)begin
if rising_edge(Clk) thenQ <= D;
elseQ <= ‘0’; --falling edge
end if;end process;
ERROR:Xst:827 - "D:/Users/John/JohnSchool/DisciplinaVHDL/Curs/FR11_FF/Latch/latch.vhd" line 40: Signal Q cannot be synthesized, bad synchronous description.
15
Restriction on edge condition, summary:1. In a process, test a single edge condition.
2. In a process, the edge condition must be the LAST condition tested in an if elsif elsif instruction.
3. Don’t mix the edge condition with other tests. Some synthesis tools won’t accept them:
if rising_edge(Clk) and Ce=‘1’ – Woks but is not recommended!
16
Specifying initial value of a Flip-flopBasic FF description:signal Clk, D : std_logic;signal Q : std_logic;--...process(Clk)begin if rising_edge(Clk) then Q <= D; end if;end process;
If a Reset button is not necessary:signal Clk, D : std_logic;signal Q : std_logic ;--...process(Clk)begin if rising_edge(Clk) then Q <= D; end if;end process;
:= ‘0’;
17
Specifying initial value of a Flip-flopIf Reset button is needed:signal Clk, D, Rst : std_logic;signal Q : std_logic;--...process(Clk, Rst)begin if Rst= ‘1’ then
Q <= ‘0’; elsif rising_edge(Clk) then Q <= D; end if;end process;
This type of Reset is asynchronous.
The FF will be reset as soon as Rst becomes active, regardless Clk activity.
The initial value can be ‘1’ instead ‘0’. In this case Rst is usually renamed to Set.
‘1’;
Q <= ‘0’ when Rst= ‘1’ else D when rising_edge(Clk);--equivalent description with conditional signal assignment.--Not recommended!
18
Specifying initial value of a Flip-flopIf Reset button is needed:
signal Clk, D, Rst : std_logic;signal Q : std_logic;--...process(Clk)Begin if rising_edge(Clk) then if Rst= ‘1’ then
Q <= ‘0’; else Q <= D; end if; end ifend process;
This type of Reset is synchronous.
The FF will be reset on the rising edge of Clk only if Rst is ‘1’
The initial value can be ‘1’ instead ‘0’.
‘1’;
19
Specifying initial value of a Flip-flopIf Reset button is needed:
signal Clk, D, Rst : std_logic;signal Q : std_logic;--...process(Clk)Begin if rising_edge(Clk) then if Rst= ‘1’ then
Q <= ‘0’; else Q <= D; end if; end ifend process;
Equivalent description with conditional signal assignment:Q <= ‘0’ when rising_edge(Clk) and Rst= ‘1’ else D when rising_edge(Clk) and Rst= ‘0’;It is not synthesizable by ISE! Don’t use it!
20
A Flip-flop can have a CE = Clock Enable inputIf CE is ‘0’, Clock is ignored!
signal Clk, D, CE: std_logic;signal Q : std_logic;--...process(Clk)Begin if rising_edge(Clk) then if CE= ‘1’ then
Q <= D; end if; end ifend process;
The FF will be written on the rising edge of Clk if and only if CE is ‘1’