freescale mc9s08sh8 hoja de datos

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Freescale Semiconductor, Inc., 2012. All rights reserved.

Freescale Semiconductor MC9S08SH8Rev. 3.1, 05/2012

This is the MC9S08SH8 datasheet set consisting of the following files:

MC9S08SH8 Datasheet Addendum, Rev 1

MC9S08SH8 Datasheet, Rev 3

MC9S08SH8 Datasheet


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MC9S08SH8AD, Rev. 1

Addendum for Revision 3.0

Freescale Semiconductor2

1 Addendum for Revision 3.0

2 Revision HistoryTable 2provides a revision history for this document.

Table 1. MC9S08SH8 Rev 3.0 Addendum

Location Description

Section Control Timing for

Appendix A ElectricalCharacteristics

In Control Timing table, changed minimum value of 'Internal low power oscillator period

parameter from 800 s to 700 s. This value is under 5V VDD, -40o

C to 125o

C temperaturerange condition.

Table 2. Revision History Table

Rev. Number Substantive Changes Date of Release

1.0 Initial release. Changed minimum value of 'Internal low power oscillator period

parameter from 800 s to 700 s, in Control Timing table.

05/2012


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reserved.

MC9S08SH8AD

Rev. 1

05/2012


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8-Bit HCS08 Central Processor Uni t (CPU) 40-MHz HCS08 CPU (central processor unit)

HC08 instruction set with added BGND instruction

Support for up to 32 interrupt/reset sources

On-Chip Memory FLASH read/program/erase over full operating

voltage and temperature

Random-access memory (RAM)

Power-Saving Modes Two very low power stop modes

Reduced power wait mode

Very low power real time interrupt for use in run,wait, and stop

Clock Source Options Oscillator (XOSC) Loop-control Pierceoscillator; Crystal or ceramic resonator range of31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz

Internal Clock Source (ICS) Internal clocksource module containing a frequency-lockedloop (FLL) controlled by internal or externalreference; precision trimmingof internal referenceallows 0.2% resolution and 2% deviation overtemperature and voltage; supports busfrequencies from 2 MHz to 20 MHz.

System Protection

Watchdog computer operating properly (COP)reset with opti/n to run from dedicated 1-kHzinternal clock source or bus clock

Low-voltage detection with reset or interrupt;selectable trip points

Illegal opcode detection with reset

Illegal address detection with reset

FLASH block protect

Development Support Single-wire background debug interface

Breakpoint capability to allow single breakpoint

setting during in-circuit debugging (pluss twomore breakpoints in on-chip debug module)

On-chip, in-circuit emulation (ICE) debug modulecontaining two comparators and nine triggermodes. Eight deep FIFO for storingchange-of-flow address and event-only data.Debug module supports both tag and forcebreakpoints.

Peripherals ADC 12-channel, 10-bit resolution, 2.5s

conversion time, automatic compare function,temperature sensor, internal bandgap reference

channel; runs in stop3 ACMP Analog comparator with selectable

interrupt on rising, falling, or either edge ofcomparator output; compare option to fixedinternal bandgap referencevoltage; output can beoptionally routed to TPM module; runs in stop3

SCI Full duplex non-return to zero (NRZ); LINmaster extended break generation; LIN slaveextended break detection; wake up on active edge

SPI Full-duplex or single-wire bidirectional;Double-buffered transmit and receive; Master orSlave mode; MSB-first or LSB-first shifting

IIC Up to 100 kbps with maximum bus loading;Multi-master operation; Programmable slaveaddress; Interrupt driven byte-by-byte datatransfer; supports broadcast mode and 10-bitaddressing

MTIM 8-bit modulo counter with 8-bit prescalerand overflow interrupt

TPMx Two 2-channel timer pwm modules(TPM1, TPM2); Selectable input capture, outputcompare, or buffered edge- or center-alignedPWM on each channel

RTC (Real-time counter) 8-bit modulus counter

with binary or decimal based prescaler; Externalclock source for precise time base, time-of-day,calendar or task scheduling functions; Freerunning on-chip low power oscillator (1 kHz) forcyclic wake-up without external components, runsin all MCU modes

Input/Output 17 general purpose I/O pins (GPIOs) and 1

output-only pin

8 interrupt pins with selectable polarity

Ganged output option for PTB[5:2] and PTC[3:0];

allows single write to change state of multiple pins Hysteresis and configurable pull up device on all

input pins; Configurable slew rate and drivestrength on all output pins.

Package Options 24-QFN, 20-TSSOP, 20-SOIC, 20-PDIP,

16-TSSOP, 8-SOIC

MC9S08SH8 Features


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MC9S08SH8 MCU Series Data Sheet, Rev. 3

6 Freescale Semiconductor

Revision History

To provide the most up-to-date information, the revision of our documents on the World Wide Web will bethe most current. Your printed copy may be an earlier revision. To verify you have the latest informationavailable, refer to:

http://freescale.com/

The following revision history table summarizes changes contained in this document.

RevisionNumber

RevisionDate

Description of Changes

0.01 3/08/2006 Initial review copy

1 11/2007 Updated Electricals and incorporated revisions from Project sync issues: 2394,2600, 2601, and 2764.

2 3/2008

Corrected SPI module to be version 3. Incorporated fixes for Project Syncissues: 2394, 2600, 2601, 2764, 3237, and 3279; as well as, ADC TemperatureSensor issues 3331 and 3335. Adjusted Features page leading and fixed minorgrammatical errors. Added 20-SOIC package option for the C temp only. Cor-rected package drawing number for 24-QFN.

3 6/2008 Added ICS over Termperature graph to Electricals.Resolved final TBDs.

Freescale Semiconductor, Inc., 2007-2008. All rights reserved.

This product incorporates SuperFlashTechnology licensed from SST.


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Freescale Semiconductor 9

Contents

Section Number Title Page

Chapter 1Device Overview

1.1 Devices in the MC9S08SH8 Series .................................................................................................191.2 MCU Block Diagram ......................................................................................................................201.3 System Clock Distribution ..............................................................................................................22

Chapter 2Pins and Connections

2.1 Device Pin Assignment ...................................................................................................................23

2.2 Recommended System Connections ...............................................................................................242.2.1 Power ................................................................................................................................252.2.2 Oscillator (XOSC) ............................................................................................................262.2.3 RESET ..............................................................................................................................262.2.4 Background / Mode Select (BKGD/MS) ..........................................................................272.2.5 General-Purpose I/O and Peripheral Ports ........................................................................27

Chapter 3Modes of Operation

3.1 Introduction .....................................................................................................................................313.2 Features ...........................................................................................................................................31

3.3 Run Mode ........................................................................................................................................313.4 Active Background Mode ................................................................................................................313.5 Wait Mode .......................................................................................................................................323.6 Stop Modes ......................................................................................................................................32

3.6.1 Stop3 Mode .......................................................................................................................333.6.2 Stop2 Mode .......................................................................................................................343.6.3 On-Chip Peripheral Modules in Stop Modes ....................................................................34

Chapter 4Memory

4.1 MC9S08SH8 Memory Map ............................................................................................................37

4.2 Reset and Interrupt Vector Assignments .........................................................................................384.3 Register Addresses and Bit Assignments ........................................................................................394.4 RAM ................................................................................................................................................464.5 FLASH ............................................................................................................................................46

4.5.1 Features .............................................................................................................................474.5.2 Program and Erase Times .................................................................................................47


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8.1.3 ACMP/TPM Configuration Information .........................................................................1138.1.4 Features ...........................................................................................................................1158.1.5 Modes of Operation ........................................................................................................115

8.1.6 Block Diagram ................................................................................................................1158.2 External Signal Description ..........................................................................................................1178.3 Memory Map ................................................................................................................................117

8.3.1 Register Descriptions ......................................................................................................1178.4 Functional Description ..................................................................................................................119

Chapter 9Analog-to-Digital Converter (S08ADCV1)

9.1 Introduction ...................................................................................................................................1219.1.1 Channel Assignments ......................................................................................................1219.1.2 Alternate Clock ...............................................................................................................122

9.1.3 Hardware Trigger ............................................................................................................1229.1.4 Temperature Sensor ........................................................................................................1229.1.5 Features ...........................................................................................................................1259.1.6 Block Diagram ................................................................................................................125

9.2 External Signal Description ..........................................................................................................1269.2.1 Analog Power (VDDAD) ..................................................................................................1279.2.2 Analog Ground (VSSAD) .................................................................................................1279.2.3 Voltage Reference High (VREFH) ...................................................................................1279.2.4 Voltage Reference Low (VREFL) .....................................................................................1279.2.5 Analog Channel Inputs (ADx) ........................................................................................127

9.3 Register Definition ........................................................................................................................127

9.3.1 Status and Control Register 1 (ADCSC1) ......................................................................1279.3.2 Status and Control Register 2 (ADCSC2) ......................................................................1299.3.3 Data Result High Register (ADCRH) .............................................................................1309.3.4 Data Result Low Register (ADCRL) ..............................................................................1309.3.5 Compare Value High Register (ADCCVH) ....................................................................1319.3.6 Compare Value Low Register (ADCCVL) .....................................................................1319.3.7 Configuration Register (ADCCFG) ................................................................................1319.3.8 Pin Control 1 Register (APCTL1) ..................................................................................1339.3.9 Pin Control 2 Register (APCTL2) ..................................................................................1349.3.10 Pin Control 3 Register (APCTL3) ..................................................................................135

9.4 Functional Description ..................................................................................................................136

9.4.1 Clock Select and Divide Control ....................................................................................1369.4.2 Input Select and Pin Control ...........................................................................................1379.4.3 Hardware Trigger ............................................................................................................1379.4.4 Conversion Control .........................................................................................................1379.4.5 Automatic Compare Function .........................................................................................1409.4.6 MCU Wait Mode Operation ............................................................................................140


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11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................16711.3.3 IIC Control Register (IICC1) ..........................................................................................17011.3.4 IIC Status Register (IICS) ...............................................................................................171

11.3.5 IIC Data I/O Register (IICD) ..........................................................................................17211.3.6 IIC Control Register 2 (IICC2) .......................................................................................172

11.4 Functional Description ..................................................................................................................17311.4.1 IIC Protocol .....................................................................................................................17311.4.2 10-bit Address .................................................................................................................17711.4.3 General Call Address ......................................................................................................178

11.5 Resets ............................................................................................................................................17811.6 Interrupts .......................................................................................................................................178

11.6.1 Byte Transfer Interrupt ....................................................................................................17811.6.2 Address Detect Interrupt .................................................................................................17811.6.3 Arbitration Lost Interrupt ................................................................................................178

11.7 Initialization/Application Information ..........................................................................................180

Chapter 12Modulo Timer (S08MTIMV1)

12.1 Introduction ...................................................................................................................................18312.1.1 MTIM Configuration Information ..................................................................................18312.1.2 Features ...........................................................................................................................18512.1.3 Modes of Operation ........................................................................................................18512.1.4 Block Diagram ................................................................................................................186

12.2 External Signal Description ..........................................................................................................18612.3 Register Definition ........................................................................................................................187

12.3.1 MTIM Status and Control Register (MTIMSC) .............................................................18812.3.2 MTIM Clock Configuration Register (MTIMCLK) .......................................................18912.3.3 MTIM Counter Register (MTIMCNT) ...........................................................................19012.3.4 MTIM Modulo Register (MTIMMOD) ..........................................................................190

12.4 Functional Description ..................................................................................................................19112.4.1 MTIM Operation Example .............................................................................................192

Chapter 13Real-Time Counter (S08RTCV1)

13.1 Introduction ...................................................................................................................................19313.1.1 Features ...........................................................................................................................195

13.1.2 Modes of Operation ........................................................................................................19513.1.3 Block Diagram ................................................................................................................196

13.2 External Signal Description ..........................................................................................................19613.3 Register Definition ........................................................................................................................196

13.3.1 RTC Status and Control Register (RTCSC) ....................................................................19713.3.2 RTC Counter Register (RTCCNT) ..................................................................................198


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Chapter 1 Device Overview



1.3 System Clock Distribution

Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clockinputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the modulefunction.

The following defines the clocks used in this MCU:

BUSCLK The frequency of the bus is always half of ICSOUT.

ICSOUT Primary output of the ICS and is twice the bus frequency.

ICSLCLK Development tools can select this clock source to speed up BDC communications insystems where the bus clock is configured to run at a very slow frequency.

ICSERCLK External reference clock can be selected as the RTC clock source and as thealternate clock for the ADC module.

ICSIRCLK Internal reference clock can be selected as the RTC clock source.

ICSFFCLK Fixed frequency clock can be selected as clock source for the TPM1, TPM2 andMTIM modules.

LPOCLK Independent 1-kHz clock source that can be selected as the clock source for the COPand RTC modules.

TCLK External input clock source for TPM1, TPM2 and MTIM and is referenced as TPMCLKin TPM chapters.

Figure 1-2. System Clock Distribution Diagram

TPM1 TPM2 MTIM SCI

BDCCPU ADC IIC FLASH

ICS

ICSOUT2

BUSCLK

ICSLCLK

ICSERCLK

COP

* The fixed frequency clock (FFCLK) is internally

synchronizedto thebus clock andmust notexceed onehalfof the bus clock frequency.

FLASH has frequencyrequirements for programand erase operation. Seethe electricals appendixfor details.

ADC has min and maxfrequency requirements.See the ADC chapterand electricals appendixfor details.

XOSC

EXTAL XTAL

SPI

FFCLK*ICSFFCLK

RTC1 kHZLPO

TCLK

ICSIRCLK

2 SYNC*

LPOCLK


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Chapter 2 Pins and Connections



Figure 2-5. Basic System Connections

2.2.1 Power

VDDand VSSare the primary power supply pins for the MCU. This voltage source supplies power to allI/O buffer circuitry, ACMP and ADC modules, and to an internal voltage regulator. The internal voltageregulator provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU.

Typically, application systems have two separate capacitors across the power pins. In this case, thereshould be a bulk electrolytic capacitor, such as a 10-F tantalum capacitor, to provide bulk charge storagefor the overall system and a 0.1-F ceramic bypass capacitor located as near to the MCU power pins aspractical to suppress high-frequency noise. Each pin must have a bypass capacitor for best noisesuppression.

BKGD/MS

RESET

OPTIONAL

MANUALRESET

VDD

BACKGROUND HEADER

SYSTEMPOWER

PORTB

PTB0/PIB0/RxD/ADP4

PTB1/PIB1/TxD/ADP5

PTB2/PIB2/SPSCK/ADP6

PTB3/PIB3/MOSI/ADP7

PTB4/TPM2CH1/MISO

PTB5/TPM1CH1/SS

PTB6/SDA/XTAL

PTB7/SCL/EXTAL

PORTC

PTC0/TPM1CH0/ADP8

PTC1/TPM1CH1/ADP9

PTC2/ADP10

PTC3/ADP11

MC9S08SH8

VSS

VDD

CBY0.1F

CBLK10F

+5 V

+

C2C1 X1

RF RS

PORT

A

PTA0/PIA0/TPM1CH0/ADP0/ACMP+

PTA1/PIA1/TPM2CH0/ADP1/ACMP-

PTA2/PIA2/SDA/ADP2

PTA3/PIA3/SCL/ADP3

0.1F

VDD

4.7 k10 k

NOTE 1

NOTES:1. External crystal circuit not required if using the internal clock option.2. RESET pin can only be used to reset into user mode, you can not enter BDM using RESET

pin. BDM can be entered by holding MS low during POR or writing a 1 to BDFR in SBDFRwith MS low after issuing BDM command.3. RC filter on RESET pin recommended for noisy environments.

PTA4/ACMPO/BKGD/MS

PTA5/IRQ/TCLK/RESET


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Chapter 2 Pins and Connections



The voltage measured on the internally pulled up RESET pin will not bepulled to VDD. The internal gates connected to this pin are pulled to VDD. Ifthe RESET pin is required to drive to a VDD level an external pullup shouldbe used.

NOTE

In EMC-sensitive applications, an external RC filter is recommended on theRESET. See Figure 2-5for an example.

2.2.4 Background / Mode Select (BKGD/MS)

During a power-on-reset (POR) or background debug force reset (see Section 5.7.3, System BackgroundDebug Force Reset Register (SBDFR), for more information), the PTA4/ACMPO/BKGD/MS pinfunctions as a mode select pin. Immediately after any reset, the pin functions as the background pin andcan be used for background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1),an internal pullup device is automatically enabled.

The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE isset following any reset of the MCU and must be cleared to use the PTA4/ACMPO/BKGD/MS pinsalternative pin function.

If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of theinternal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standardbackground debug header, it can hold BKGD/MS low during a POR or immediately after issuing abackground debug force reset, which will force the MCU to active background mode.

The BKGD pin is used primarily for background debug controller (BDC) communications using a customprotocol that uses 16 clock cycles of the target MCUs BDC clock per bit time. The target MCUs BDC

clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitanceconnected to the BKGD/MS pin that could interfere with background serial communications.

Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocolprovides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances fromcables and the absolute value of the internal pullup device play almost no role in determining rise and falltimes on the BKGD pin.

2.2.5 General-Purpose I/O and Peripheral Ports

The MC9S08SH8 series of MCUs support up to 17 general-purpose I/O pins and 1 output-only pin, whichare shared with on-chip peripheral functions (timers, serial I/O, ADC, etc).

When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,software can select one of two drive strengths and enable or disable slew rate control. When a port pin isconfigured as a general-purpose input or a peripheral uses the port pin as an input, software can enable apull-up device. Immediately after reset, all of these pins areconfigured as high-impedance general-purposeinputs with internal pull-up devices disabled.


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Chapter 3 Modes of Operation



Table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under variousconditions. The selected mode is entered following the execution of a STOP instruction.

3.6.1 Stop3 ModeStop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Thestates of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.

Stop3 can be exited by asserting RESET if enabled, or by an interrupt from one of the following sources:the real-time counter (RTC), LVD system, ACMP, ADC, SCI, IRQ, or any pin interrupts.

If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after takingthe reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking theappropriate interrupt vector.

3.6.1.1 LVD Enabled in Stop ModeTheLVD system is capable of generating either an interrupt or a reset when the supply voltage dropsbelowthe LVD voltage. For configuring the LVD system for interrupt or reset, refer to 5.6, Low-Voltage Detect(LVD) System. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the timethe CPU executes a STOP instruction, then the voltage regulator remains active during stop mode.

For the ADC to operate in stop mode, the LVD must be enabled when entering stop3.

For the ACMP to operate in stop mode with compare to internal bandgap option, the LVD must be enabledwhen entering stop3.

3.6.1.2 Active BDM Enabled in Stop Mode

Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. Thisregister is described in Chapter 17, Development Support. If ENBDM is set when the CPU executes aSTOP instruction, the system clocks to the background debug logic remain active when the MCU entersstop mode. Because of this, background debug communication remains possible. In addition, the voltageregulator does not enter its low-power standby state but maintains full internal regulation.

Table 3-1. Stop Mode Selection

STOPE ENBDM 1

1 ENBDM is located in the BDCSCR, which is only accessible through BDC commands, see Section 17.4.1.1, BDC Status andControl Register (BDCSCR).

LVDE LVDSE PPDC Stop Mode

0 x x x Stop modes disabled; illegal opcode reset if STOP instruction executed

1 1 x x Stop3 with BDM enabled 2

2 When in Stop3 mode with BDM enabled, The SIDDwill be near RIDDlevels because internal clocks are enabled.

1 0 Both bits must be 1 0 Stop3 with voltage regulator active

1 0 Either bit a 0 0 Stop3

1 0 Either bit a 0 1 Stop2


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Chapter 3 Modes of Operation



Most background commands are not available in stop mode. The memory-access-with-status commandsdo not allow memory access, but they report an error indicating that the MCU is in either stop or waitmode. The BACKGROUND command can be used to wake the MCU from stop and enter activebackground mode if the ENBDM bit is set. After entering background debug mode, all backgroundcommands are available.

3.6.2 Stop2 Mode

Stop2 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. Mostof the internal circuitry of the MCU is powered off in stop2 with the exception of the RAM. Upon enteringstop2, all I/O pin control signals are latched so that the pins retain their states during stop2.

Exit from stop2 is performed by asserting the wake-up pin (PTA5/IRQ/TCLK/RESET) on the MCU.

In addition, the real-time counter (RTC) can wake the MCU from stop2, if enabled.

Upon wake-up from stop2 mode, the MCU starts up as from a power-on reset (POR):

All module control and status registers are reset

The LVD reset function is enabled and the MCU remains in the reset state if VDD is below the LVDtrip point (low trip point selected due to POR)

The CPU takes the reset vector

In addition to the above, upon waking up from stop2, the PPDF bit in SPMSC2 is set. This flag is used todirect user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latcheduntil a 1 is written to PPDACK in SPMSC2.

To maintain I/O states for pins that were configured as general-purpose I/O before entering stop2, the usermust restore the contents of the I/O port registers, which have been saved in RAM, to the port registersbefore writing to the PPDACK bit. If the port registers are not restored from RAM before writing toPPDACK, then the pins will switch to their reset states when PPDACK is written.

For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module thatinterfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled beforewriting to PPDACK, the pins will be controlled by their associated port control registers when the I/Olatches are opened.

3.6.3 On-Chip Peripheral Modules in Stop Modes

When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Evenin the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.2, Stop2

Mode, and Section 3.6.1, Stop3 Mode, for specific information on system behavior in stop modes.


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Chapter 4

Memory

4.1 MC9S08SH8 Memory Map

As shown in Figure 4-1, on-chip memory in the MC9S08SH8 series of MCUs consists of RAM, FLASHprogram memory for nonvolatile data storage, and I/O and control/status registers. The registers aredivided into three groups:

Direct-page registers (0x0000 through 0x007F)

High-page registers (0x1800 through 0x185F)

Nonvolatile registers (0xFFB0 through 0xFFBF)

Figure 4-1. MC9S08SH8 Memory Map

DIRECT PAGE REGISTERS

RAM

HIGH PAGE REGISTERS

512 BYTES

0x0000

0x007F0x0080

0x027F

0x18000x17FF

0x185F

0xFFFF

0x0280

MC9S08SH8

FLASH

8192 BYTES

0x1860

MC9S08SH4

UNIMPLEMENTED

51,104 BYTES

0xE000

0xDFFF

DIRECT PAGE REGISTERS

RAM

HIGH PAGE REGISTERS

256 BYTES

0x0000

0x007F0x0080

0x18000x17FF

0x185F

0xFFFF

FLASH

4096 BYTES

0x1860

0x017F0x0180

0xF000

0xEFFF

UNIMPLEMENTED

5504 BYTES

0x027F0x0280 UNIMPLEMENTED

5504 BYTES

RESERVED256 BYTES

UNIMPLEMENTED

51,104 BYTES

0xE000

0xDFFF

RESERVED

4096 BYTES


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Chapter 4 Memory



4.3 Register Addresses and Bit Assignments

The registers in the MC9S08SH8 are divided into these groups:

Direct-page registers are located in the first 128 locations in the memory map; these are accessible

with efficient direct addressing mode instructions.

High-page registers are used much less often, so they are located above 0x1800 in the memorymap. This leaves more room in the direct page for more frequently used registers and RAM.

The nonvolatile register area consists of a block of 16 locations in FLASH memory at0xFFB00xFFBF. Nonvolatile register locations include:

NVPROT and NVOPT are loaded into working registers at reset

An 8-byte backdoor comparison key that optionally allows a user to gain controlled access tosecure memory

Because the nonvolatile register locations are FLASH memory, they must be erased and

programmed like other FLASH memory locations.Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulationinstructions can be used to access any bit in any direct-page register. Table 4-2is a summary of alluser-accessible direct-page registers and control bits.

The direct page registers in Table 4-2can use the more efficient direct addressing mode, which requiresonly the lower byte of the address. Because of this, the lower byte of the address in column one is shownin bold text. In Table 4-3and Table 4-4, the whole address in column one is shown in bold. In Table 4-2,Table 4-3, and Table 4-4, the register names in column two are shown in bold to set them apart from thebit names to the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0indicates this unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit

locations that could read as 1s or 0s.


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Table 4-2. Direct-Page Register Summary (Sheet 1 of 3)

AddressRegister

NameBit 7 6 5 4 3 2 1 Bit 0

0x0000 PTAD 0 0 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0

0x0001 PTADD 0 0 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0

0x0002 PTBD

PTBD7 PTBD6 PTBD5 PTBD4 PTBD3 PTBD2 PTBD1 PTBD00x0003 PTBDD PTBDD7 PTBDD6 PTBDD5 PTBDD4 PTBDD3 PTBDD2 PTBDD1 PTBDD0

0x0004 PTCD 0 0 0 0 PTCD3 PTCD2 PTCD1 PTCD0

0x0005 PTCDD 0 0 0 0 PTCDD3 PTCDD2 PTCDD1 PTCDD0

0x0006

0x000DReserved

0x000E ACMPSC ACME ACBGS ACF ACIE ACO ACOPE ACMOD1 ACMOD0

0x000F Reserved

0x0010 ADSC1 COCO AIEN ADCO ADCH

0x0011 ADSC2 ADACT ADTRG ACFE ACFGT

0x0012 ADRH 0 0 0 0 0 0 ADR9 ADR8

0x0013 ADRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

0x0014 ADCVH 0 0 0 0 0 0 ADCV9 ADCV8

0x0015 ADCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0

0x0016 ADCFG ADLPC ADIV ADLSMP MODE ADICLK

0x0017 APCTL1 ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0

0x0018 APCTL2 0 0 0 0 ADPC11 ADPC10 ADPC9 ADPC8

0x0019 Reserved

0x001A IRQSC 0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD

0x001B Reserved

0x001C MTIMSC TOF TOIE TRST TSTP 0 0 0 0

0x001D MTIMCLK 0 0 CLKS PS

0x001E MTIMCNT CNT

0x001F MTIMMOD MOD

0x0020 TPM1SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0

0x0021 TPM1CNTH Bit 15 14 13 12 11 10 9 Bit 8

0x0022 TPM1CNTL Bit 7 6 5 4 3 2 1 Bit 0

0x0023 TPM1MODH Bit 15 14 13 12 11 10 9 Bit 8

0x0024 TPM1MODL Bit 7 6 5 4 3 2 1 Bit 0

0x0025 TPM1C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0

0x0026 TPM1C0VH Bit 15 14 13 12 11 10 9 Bit 8

0x0027 TPM1C0VL Bit 7 6 5 4 3 2 1 Bit 00x0028 TPM1C1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0

0x0029 TPM1C1VH Bit 15 14 13 12 11 10 9 Bit 8

0x002A TPM1C1VL Bit 7 6 5 4 3 2 1 Bit 0

0x002B0x0037

Reserved
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0x0038 SCIBDH LBKDIE RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8

0x0039 SCIBDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0

0x003A SCIC1

LOOPS SCISWAI RSRC M WAKE ILT PE PT0x003B SCIC2 TIE TCIE RIE ILIE TE RE RWU SBK

0x003C SCIS1 TDRE TC RDRF IDLE OR NF FE PF

0x003D SCIS2 LBKDIF RXEDGIF 0 RXINV RWUID BRK13 LBKDE RAF

0x003E SCIC3 R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE

0x003F SCID Bit 7 6 5 4 3 2 1 Bit 0

0x0040

0x0047Reserved

0x0048 ICSC1 CLKS RDIV IREFS IRCLKEN IREFSTEN

0x0049 ICSC2 BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN

0x004A ICSTRM TRIM

0x004B ICSSC 0 0 0 IREFST CLKST OSCINIT FTRIM

0x004C

0x004FReserved

0x0050 SPIC1 SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE

0x0051 SPIC2 0 0 0 MODFEN BIDIROE 0 SPISWAI SPC0

0x0052 SPIBR 0 SPPR2 SPPR1 SPPR0 0 SPR2 SPR1 SPR0

0x0053 SPIS SPRF 0 SPTEF MODF 0 0 0 0

0x0054 Reserved 0 0 0 0 0 0 0 0

0x0055 SPID Bit 7 6 5 4 3 2 1 Bit 0

0x0056

0x0057

Reserved

0x0058 IICA AD7 AD6 AD5 AD4 AD3 AD2 AD1 0

0x0059 IICF MULT ICR

0x005A IICC1 IICEN IICIE MST TX TXAK RSTA 0 0

0x005B IICS TCF IAAS BUSY ARBL 0 SRW IICIF RXAK

0x005C IICD DATA

0x005D IICC2 GCAEN ADEXT 0 0 0 AD10 AD9 AD8

0x005E0x005F

Reserved

0x0060 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0

0x0061 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8

0x0062 TPM2CNTL Bit 7 6 5 4 3 2 1 Bit 0

0x0063 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8

0x0064 TPM2MODL Bit 7 6 5 4 3 2 1 Bit 0


0x0066 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8

0x0067 TPM2C0VL Bit 7 6 5 4 3 2 1 Bit 0


AddressRegister

NameBit 7 6 5 4 3 2 1 Bit 0
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0x0069 TPM2C1VH Bit 15 14 13 12 11 10 9 Bit 8

0x006A TPM2C1VL

Bit 7 6 5 4 3 2 1 Bit 00x006B Reserved

0x006C RTCSC RTIF RTCLKS RTIE RTCPS

0x006D RTCCNT RTCCNT

0x006E RTCMOD RTCMOD

0x006F -0x007F

Reserved


AddressRegister

NameBit 7 6 5 4 3 2 1 Bit 0
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4.4 RAM

The MC9S08SH8 includes static RAM. The locations in RAM below 0x0100 can be accessed using themore efficient direct addressing mode, and any single bit in this area can be accessed with the bitmanipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessedprogram variables in this area of RAM is preferred.

The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on thecontents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltagedoes not drop below the minimum value for RAM retention (VRAM).

For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In theMC9S08SH8, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct pageRAM can be used for frequently accessed RAM variables and bit-addressable program variables. Includethe following 2-instruction sequence in your reset initialization routine (where RamLast is equated to thehighest address of the RAM in the Freescale Semiconductor-provided equate file).

LDHX #RamLast+1 ;point one past RAM

TXS ;SP


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4.5.3 Program and Erase Command Execution

The steps for executing any of the commands are listed below. The FCDIV register must be initialized andany error flags cleared before beginning command execution. The command execution steps are:

1. Write a data value to an address in the FLASH array. The address and data information from thiswrite is latched into the FLASH interface. This write is a required first step in any command

sequence. For erase and blank check commands, the value of the data is not important. For pageerase commands, the address may be any address in the 512-byte page of FLASH to be erased. Formass erase and blank check commands, the address can be any address in the FLASH memory.Whole pages of 512 bytes are the smallest block of FLASH that may be erased.

NOTE

Do not program any byte in the FLASH more than once after a successfulerase operation. Reprogramming bits to a byte that is already programmedis not allowed without first erasing the page in which the byte resides ormass erasing the entire FLASH memory. Programming without first erasingmay disturb data stored in the FLASH.

2. Write the command code for the desired command to FCMD. The five valid commands are blankcheck (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase(0x41). The command code is latched into the command buffer.

3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including itsaddress and data information).

A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write tothe memory array and before writing the 1 that clears FCBEF and launches the complete command.Aborting a command in this way sets the FACCERR access error flag, which must be cleared beforestarting a new command.

A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes thepossibility of any unintended changes to the FLASH memory contents. The command complete flag(FCCF) indicates when a command is complete. The command sequence must be completed by clearingFCBEF to launch the command. Figure 4-2is a flowchart for executing all of the commands except forburst programming. The FCDIV register must be initialized before using any FLASH commands. Thismust be done only once following a reset.


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The first byte of a series of sequential bytes being programmed in burst mode will take the same amountof time to program as a byte programmed in standard mode. Subsequent bytes will program in the burstprogram time provided that the conditions above are met. In the case the next sequential address is thebeginning of a new row, the program time for that byte will be the standard time instead of the burst time.This is because the high voltage to the array must be disabled and then enabled again. If a new burstcommand has not been queued before the current command completes, then the charge pump will be

disabled and high voltage removed from the array.

Figure 4-3. FLASH Burst Program Flowchart

1

0FCBEF ?

START

WRITE TO FLASH

TO BUFFER ADDRESS AND DATA

WRITE COMMAND (0x25) TO FCMD

NO

YESFPVIO OR

WRITE 1 TO FCBEF

TO LAUNCH COMMAND

AND CLEAR FCBEF (Note 2)

NO

YESNEW BURST COMMAND ?

1

0FCCF ?

ERROR EXIT

DONE

Note 2: Wait at least four bus cycles before

1

0FACCERR ?

CLEAR ERROR

FACCERR ?

Note 1: Required only once after reset.WRITE TO FCDIV (Note 1)

checking FCBEF or FCCF.

FLASH BURST

PROGRAM FLOW


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4.5.5 Access Errors

An access error occurs whenever the command execution protocol is violated.

Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.

Writing to a FLASH address before the internal FLASH clock frequency has been set by writingto the FCDIV register

Writing to a FLASH address while FCBEF is not set (A new command cannot be started until thecommand buffer is empty.)

Writing a second time to a FLASH address before launching the previous command (There is onlyone write to FLASH for every command.)

Writing a second time to FCMD before launching the previous command (There is only one writeto FCMD for every command.)

Writing to any FLASH control register other than FCMD after writing to a FLASH address

Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41)

to FCMD Writing any FLASH control register other than the write to FSTAT (to clear FCBEF and launch the

command) after writing the command to FCMD

The MCU enters stop mode while a program or erase command is in progress (The command isaborted.)

Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) witha background debug command while the MCU is secured (The background debug controller canonly do blank check and mass erase commands when the MCU is secure.)

Writing 0 to FCBEF to cancel a partial command

4.5.6 FLASH Block ProtectionThe block protection feature prevents the protected region of FLASH from program or erase changes.Block protection is controlled through the FLASH protection register (FPROT). When enabled, blockprotection begins at any 512 byte boundary below the last address of FLASH, 0xFFFF. (See Section 4.7.4,FLASH Protection Register (FPROT and NVPROT)).

After exit from reset, FPROT is loaded with the contents of the NVPROT location, which is in thenonvolatile register block of the FLASH memory. FPROT cannot be changed directly from applicationsoftware so a runaway program cannot alter the block protection settings. Because NVPROT is within thelast 512 bytes of FLASH, if any amount of memory is protected, NVPROT is itself protected and cannotbe altered (intentionally or unintentionally) by the application software. FPROT can be written through

background debug commands, which allows a way to erase and reprogram a protected FLASH memory.

The block protection mechanism is illustrated in Figure 4-4. The FPS bits are used as the upper bits of thelast address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bitsas shown. For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), theFPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotectedmemory. In addition to programming the FPSbits to the appropriate value, FPDIS (bit 0 of NVPROT) must


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be programmed to logic 0 to enable block protection. Therefore the value 0xF8 must be programmed intoNVPROT to protect addresses 0xFA00 through 0xFFFF.

Figure 4-4. Block Protection Mechanism

One use for block protection is to block protect an area of FLASH memory for a bootloader program. Thisbootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Becausethe bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase andreprogram operation.

4.5.7 Vector Redirection

Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vectorredirection allows users to modify interrupt vector information without unprotecting bootloader and resetvector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT registerlocated at address 0xFFBF to zero. For redirection to occur, at least some portion but not all of the FLASHmemory must be block protected by programming the NVPROT register located at address 0xFFBD. Allof the interrupt vectors (memory locations 0xFFC00xFFFD) are redirected, though the reset vector(0xFFFE:FFFF) is not.

For example, if 512 bytes of FLASH are protected, the protected address region is from 0xFE00 through0xFFFF. The interrupt vectors (0xFFC00xFFFD) are redirected to the locations 0xFDC00xFDFD. Now,if an SPI interrupt is taken for instance, the values in the locations 0xFDE0:FDE1 are used for the vectorinstead of the values in the locations 0xFFE0:FFE1. This allows the user to reprogram the unprotected

portion of the FLASH with new program code including new interrupt vector values while leaving theprotected area, which includes the default vector locations, unchanged.

4.6 Security

The MC9S08SH8 includes circuitry to prevent unauthorized access to the contents of FLASH and RAMmemory. When security is engaged, FLASH and RAM are considered secure resources. Direct-pageregisters, high-page registers, and the background debug controller are considered unsecured resources.Programs executing within secure memory have normal access to any MCU memory locations andresources. Attempts to access a secure memory location with a program executing from an unsecuredmemory space or through the background debug interface are blocked (writes are ignored and reads return

all 0s).

Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) inthe FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from FLASHinto the working FOPT register in high-page register space. A user engages security by programming theNVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 statedisengages security and the other three combinations engage security. Notice the erased state (1:1) makes

FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1

A15 A14 A13 A12 A11 A10 A9 A8

1

A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 1 1 1 1


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control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in FLASH memory.Refer to Table 4-3 and Table 4-4 for theabsolute address assignments for all FLASH registers. This sectionrefers to registers and control bits only by their names. A Freescale Semiconductor-provided equate orheader file normally is used to translate these names into the appropriate absolute addresses.

4.7.1 FLASH Clock Divider Register (FCDIV)Bit 7 of this register is a read-only flag. Bits 6:0 may be read at any time but can be written only one time.Before any erase or programming operations are possible, write to this register to set the frequency of theclock for the nonvolatile memory system within acceptable limits.

if PRDIV8 = 0 fFCLK= fBus(DIV + 1) Eqn. 4-1

if PRDIV8 = 1 fFCLK= fBus(8(DIV + 1)) Eqn. 4-2

Table 4-7shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.

7 6 5 4 3 2 1 0

R DIVLDPRDIV8 DIV

W

Reset 0 0 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 4-5. FLASH Clock Divider Register (FCDIV)

Table 4-6. FCDIV Register Field Descriptions

Field Description

7DIVLD

Divisor Loaded Status Flag When set, this read-only status flag indicates that the FCDIV register has beenwritten since reset. Reset clears this bit and the first write to this register causes this bit to become set regardlessof the data written.0 FCDIV has not been written since reset; erase and program operations disabled for FLASH.1 FCDIV has been written since reset; erase and program operations enabled for FLASH.

6PRDIV8

Prescale (Divide) FLASH Clock by 8

0 Clock input to the FLASH clock divider is the bus rate clock.

1 Clock input to the FLASH clock divider is the bus rate clock divided by 8.

5:0DIV

Divisor for FLASH Clock Divider The FLASH clock divider divides the bus rate clock (or the bus rate clockdivided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internalFLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH operations. Program/Erasetiming pulses are one cycle of this internal FLASH clock which corresponds to a range of 5s to 6.7s. Theautomated programming logic uses an integer number of these pulses to complete an erase or programoperation. See Equation 4-1and Equation 4-2.


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4.7.3 FLASH Configuration Register (FCNFG

4.7.4 FLASH Protection Register (FPROT and NVPROT)

During reset, the contents of the nonvolatile location NVPROT are copied from FLASH into FPROT. Thisregister can be read at any time. If FPDIS = 0, protection can be increased (that is, a smaller value of FPScan be written). If FPDIS = 1, writes do not change protection.

Figure 4-8. FLASH Protection Register (FPROT)

Table 4-9. Security States1

1 SEC01:SEC00 changes to 1:0 after successful backdoorkey entry or a successful blank check of FLASH.

SEC01:SEC00 Description

0:0 secure

0:1 secure

1:0 unsecured

1:1 secure

7 6 5 4 3 2 1 0

R 0 0KEYACC

0 0 0 0 0

W

Reset 0 0 0 0 0 0 0 0= Unimplemented or Reserved

Figure 4-7. FLASH Configuration Register (FCNFG

Table 4-10. FCNFG Register Field Descriptions

Field Description

5KEYACC

Enable Writing of Access Key This bit enables writing of the backdoor comparison key. For more detailedinformation about the backdoor key mechanism, refer toSection 4.6, Security.0 Writes to 0xFFB00xFFB7 are interpreted as the start of a FLASH programming or erase command.1 Writes to NVBACKKEY (0xFFB00xFFB7) are interpreted as comparison key writes.

7 6 5 4 3 2 1 0

RFPS(1)

1 Background commands can be used to change the contents of these bits in FPROT.

FPDIS(1)

W

Reset This register is loaded from nonvolatile location NVPROT during reset.


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4.7.5 FLASH Status Register (FSTAT)

Table 4-11. FPROT Register Field Descriptions

Field Description

7:1FPS

FLASH Protect Select Bits When FPDIS = 0, this 7-bit field determines the ending address of unprotectedFLASH locations at the high address end of the FLASH. Protected FLASH locations cannot be erased orprogrammed.

0FPDIS

FLASH Protection Disable0 FLASH block specified by FPS[7:1] is block protected (program and erase not allowed).1 No FLASH block is protected.

7 6 5 4 3 2 1 0

RFCBEF

FCCFFPVIOL FACCERR

0 FBLANK 0 0

W

Reset 1 1 0 0 0 0 0 0

= Unimplemented or Reserved

Figure 4-9. FLASH Status Register (FSTAT)

Table 4-12. FSTAT Register Field Descriptions

Field Description

7FCBEF

FLASH Command Buffer Empty Flag The FCBEF bit is used to launch commands. It also indicates that thecommand buffer is empty so that a new command sequence can be executed when performing burstprogramming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred tothe array for programming. Only burst program commands can be buffered.0 Command buffer is full (not ready for additional commands).1 A new burst program command can be written to the command buffer.

6FCCF

FLASH Command Complete Flag FCCF is set automatically when the command buffer is empty and nocommand is being processed. FCCF is cleared automatically when a new command is started (by writing 1 toFCBEF to register a command). Writing to FCCF has no meaning or effect.0 Command in progress1 All commands complete

5FPVIOL

Protection Violation Flag FPVIOL is set automatically when a command is written that attempts to erase orprogram a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing a 1to FPVIOL.0 No protection violation.1 An attempt was made to erase or program a protected location.


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4.7.6 FLASH Command Register (FCMD)

Only five command codes are recognized in normal user modes as shown in Table 4-13. Refer to Section4.5.3, Program and Erase Command Execution, for a detailed discussion of FLASH programming anderase operations.

All other command codes are illegal and generate an access error.

It is not necessary to perform a blank check command after a mass erase operation. Only blank check isrequired as part of the security unlocking mechanism.

4FACCERR

AccessError Flag FACCERR is set automatically when the proper command sequence is not obeyed exactly(the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register hasbeen initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion ofthe exact actions that are considered access errors, see Section 4.5.5, Access Errors. FACCERR is cleared by

writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.0 No access error.1 An access error has occurred.

2FBLANK

FLASH Verifie as All Blank (erased) Flag FBLANK is set automatically at the conclusion of a blank checkcommand if the entire FLASH array was verified to be erased. FBLANK is cleared by clearing FCBEF to write anew valid command. Writing to FBLANK has no meaning or effect.0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the FLASH array is not

completely erased.1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the FLASH array is

completely erased (all 0xFF).

7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0

W FCMD

Reset 0 0 0 0 0 0 0 0

Figure 4-10. FLASH Command Register (FCMD)

Table 4-13. FLASH Commands

Command FCMD Equate File Label

Blank check 0x05 mBlank

Byte program 0x20 mByteProg

Byte program burst mode 0x25 mBurstProg

Page erase (512 bytes/page) 0x40 mPageErase

Mass erase (all FLASH) 0x41 mMassErase

Table 4-12. FSTAT Register Field Descriptions (continued)

Field Description


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5.4 Computer Operating Properly (COP) Watchdog

The COP watchdog is intended to force a system reset when the application software fails to execute asexpected. To prevent a system reset from the COP timer (when it is enabled), application software mustreset the COP counter periodically. If the application program gets lost and fails to reset the COP counterbefore it times out, a system reset is generated to force the system back to a known starting point.

After any reset, the COP watchdog is enabled (see Section 5.7.4, System Options Register 1 (SOPT1),for additional information). If the COP watchdog is not used in an application, it can be disabled byclearing COPT bits in SOPT1.

The COP counter is reset by writing 0x0055 and 0x00AA (in this order) to the address of SRS during theselected timeout period. Writes do not affect the data in the read-only SRS. As soon as the write sequenceis done, the COP timeout period is restarted. If the program fails to do this during the time-out period, theMCU will reset. Also, if any value other than 0x0055 or 0x00AA is written to SRS, the MCU isimmediately reset.

The COPCLKS bit in SOPT2 (see Section 5.7.5, System Options Register 2 (SOPT2), for additionalinformation) selects the clock source used for the COP timer. The clock source options are either the busclock or an internal 1-kHz clock source. With each clock source, there are three associated time-outscontrolled by the COPT bits in SOPT1. Table 5-1 summaries the control functions of the COPCLKS andCOPT bits. The COP watchdog defaults to operation from the 1-kHz clock source and the longest time-out(210cycles).

Table 5-1. COP Configuration Option

When the bus clock source is selected, windowed COP operation is available by setting COPW in theSOPT2 register. In this mode, writes to the SRS register to clear the COP timer must occur in the last 25%of the selected timeout period. A premature write immediately resets the MCU. When the 1-kHz clocksource is selected, windowed COP operation is not available.

Control BitsClock Source

COP Window1Opens

(COPW = 1)

1 Windowed COP operation requires the user to clear theCOP timer in the last 25% of the selected timeout period. This columndisplays the minimun number of clock counts required before the COP t imer can be reset hen in windowed COP mode(COPW = 1).

COP Overfl w CountCOPCLKS COPT[1:0]

N/A 0:0 N/A N/A COP is disabled

0 0:1 1 kHz N/A 25 cycles (32 ms2)

2 Values shown in in miliseconds based on tLPO = 1 ms. See tLPO in the appendix Section A.12.1, Control Timing for thetolerance of this value.

0 1:0 1 kHz N/A 28cycles (256 ms1)

0 1:1 1 kHz N/A 210cycles (1.024 s1)

1 0:1 Bus 6144 cycles 213 cycles

1 1:0 Bus 49,152 cycles 216 cycles

1 1:1 Bus 196,608 cycles 218 cycles


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The COP counter is initialized by the first writes to the SOPT1 and SOPT2 registers after any system reset.Subsequent writes to SOPT1 and SOPT2 have no effect on COP operation. Even if the application will usethe reset default settings of COPT, COPCLKS, and COPW bits, the user should write to the write-onceSOPT1 and SOPT2 registers during reset initialization to lock in the settings. This will prevent accidentalchanges if the application program gets lost.

The write to SRS that services (clears) the COP counter should not be placed in an interrupt service routine(ISR) because the ISR could continue to be executed periodically even if the main application programfails.

If the bus clock source is selected, the COP counter does not increment while the MCU is in backgrounddebug mode or while the system is in stop mode. The COP counter resumes when the MCU exitsbackground debug mode or stop mode.

If the 1-kHz clock source is selected, the COP counter is re-initialized to zero upon entry to eitherbackground debug mode or stop mode and begins from zero upon exit from background debug mode orstop mode.

5.5 InterruptsInterrupts provide a way to save the current CPU status and registers, execute an interrupt service routine(ISR), and then restore the CPU status so processing resumes where it left off before the interrupt. Otherthan the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware eventssuch as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWIunder certain circumstances.

If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. TheCPU will not respond unless the local interrupt enable is a 1 to enable the interrupt and the I bit in the CCRis 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset whichprevents all maskable interrupt sources. The user program initializes the stack pointer and performs other

system setup before clearing the I bit to allow the CPU to respond to interrupts.

When the CPU receivesa qualified interrupt request, it completes the current instruction before respondingto the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequenceas the SWI instruction andconsists of:

Saving the CPU registers on the stack

Setting the I bit in the CCR to mask further interrupts

Fetching the interrupt vector for the highest-priority interrupt that is currently pending

Filling the instruction queue with the first three bytes of program information starting from theaddress fetched from the interrupt vector locations

While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of anotherinterrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit can be clearedinside an ISR (after clearing the status flag that generated the interrupt) so that other interrupts can beserviced without waiting for the first service routine to finish. This practice is not recommended for anyone


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The status flag corresponding to the interrupt source must be acknowledged (cleared) before returningfrom the ISR. Typically, the flag is cleared at the beginning of the ISR so that if another interrupt isgenerated by this same source, it will be registered so it can be serviced after completion of the current ISR.

5.5.2 External Interrupt Request Pin (IRQ)

External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function isenabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is instop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)can wake the MCU.

5.5.2.1 Pin Configuration Option

The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interruptrequest (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected(IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an eventcauses an interrupt or only sets the IRQF flag which can be polled by software.

The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), the device is a pull-upor pull-down depending on the polarity chosen. If the user desires to use an external pull-up or pull-down,the IRQPDD can be written to a 1 to turn off the internal device.

BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to actas the IRQ input.

NOTE

This pin does not contain a clamp diode to VDDand should not be drivenabove VDD.

The voltage measured on the internally pulled up IRQ pin will not be pulled

to VDD. The internal gates connected to this pin are pulled to VDD. If theIRQ pin is required todrive to a VDD level an external pullup should be used.

5.5.2.2 Edge and Level Sensitivity

The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In theedge and level detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQpin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot becleared) as long as the IRQ pin remains at the asserted level.

5.5.3 Interrupt Vectors, Sources, and Local Masks

Table 5-2provides a summary of all interrupt sources. Higher-priority sources are located toward thebottom of the table. The high-order byte of the address for the interrupt service routine is located at thefirst address in the vector address column, and the low-order byte of the address for the interrupt serviceroutine is located at the next higher address.


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When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interruptenable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit inthe CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPUregisters; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.Processing then continues in the interrupt service routine.

Table 5-2. Vector Summary

Vector

Priority

Vector

Number

Address

(High/Low)

Vector

NameModule Source Enable Description

Lowest

Highest

31 0xFFC0/0xFFC1

30 0xFFC2/0xFFC3 Vacmp ACMP ACF ACIE Analog comparator

29 0xFFC4/0xFFC5

28 0xFFC6/0xFFC7

27 0xFFC8/0xFFC9

26 0xFFCA/0xFFCB Vmtim MTIM TOF TOIE MTIM overflow

25 0xFFCC/0xFFCD Vrtc RTC RTIF RTIE Real-time interrupt

24 0xFFCE/0xFFCF Viic IIC IICIF IICIE IIC control

23 0xFFD0/0xFFD1 Vadc ADC COCO AIEN ADC

22 0xFFD2/0xFFD3

21 0xFFD4/0xFFD5 Vportb Port B PTBIF PTBIE Port B Pins

20 0xFFD6/0xFFD7 Vporta Port A PTAIF PTAIE Port A Pins

19 0xFFD8/0xFFD9

18 0xFFDA/0xFFDB Vscitx SCI TDRE, TC TIE, TCIE SCI transmit

17 0xFFDC/0xFFDD Vscirx SCI IDLE, RDRF,LBKDIE,

RXEDGIF

ILIE, RIE, LDBKDIF,RXEDGIE

SCI receive

16 0xFFDE/0xFFDF Vscierr SCI OR, NF,FE, PF

ORIE, NFIE,FEIE, PFIE

SCI error

15 0xFFE0/0xFFE1 Vspi SPI SPIF, MODF,SPTEF

SPIE, SPIE, SPTIE SPI

14 0xFFE2/0xFFE3 Vtpm2ovf TPM2 TOF TOIE TPM2 overflow13 0xFFE4/0xFFE5 Vtpm2ch1 TPM2 CH1F CH1IE TPM2 channel 1

12 0xFFE6/0xFFE7 Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0

11 0xFFE8/0xFFE9 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow

10 0xFFEA/0xFFEB

9 0xFFEC/0xFFED

8 0xFFEE/0xFFEF

7 0xFFF0/0xFFF1

6 0xFFF2/0xFFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1

5 0xFFF4/0xFFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0

4 0xFFF6/0xFFF7

3 0xFFF8/0xFFF9 Vlvd System

control

LVWF LVWIE Low-voltage warning

2 0xFFFA/0xFFFB Virq IRQ IRQF IRQIE IRQ pin

1 0xFFFC/0xFFFD Vswi Core SWI Instruction Software interrupt

0 0xFFFE/0xFFFF Vreset Systemcontrol

COP,LVD,

RESET pin,Illegal opcode,Illegal address

COPTLVDRE

Watchdog timerLow-voltage detect

External pinIllegal opcodeIllegal address


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5.6 Low-Voltage Detect (LVD) System

The MC9S08SH8 includes a system to protect against low voltage conditions in order to protect memorycontents and control MCU system states during supply voltage variations. The system is comprised of apower-on reset (POR) circuit and a LVD circuit with trip voltages for warning and detection. The LVDcircuit is enabled when LVDE in SPMSC1 is set to 1. The LVD is disabled upon entering any of the stop

modes unless LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enterstop2, and the current consumption in stop3 with the LVD enabled will be higher.

5.6.1 Power-On Reset Operation

When power is initially applied to the MCU, or when the supply voltage drops below the power-on resetrearm voltage level, VPOR, the POR circuit will cause a reset condition. As the supply voltage rises, theLVD circuit will hold the MCU in reset until the supply has risen above the low voltage detection lowthreshold, VLVDL. Both the POR bit and the LVD bit in SRS are set following a POR.

5.6.2 Low-Voltage Detection (LVD) Reset Operation

The LVD can be configured to generate a reset upon detection of a low voltage condition by settingLVDRE to 1. The low voltage detection threshold is determined by the LVDV bit. After an LVD reset hasoccurred, the LVD system will hold the MCU in reset until the supply voltage has risen above the lowvoltage detection threshold. The LVD bit in the SRS register is set following either an LVD reset or POR.

5.6.3 Low-Voltage Warning (LVW) Interrupt Operation

The LVD system has a low voltage warning flag to indicate to the user that the supply voltage isapproaching the low voltage condition. When a low voltage warning condition is detected and isconfigured for interrupt operation (LVWIE set to 1), LVWF in SPMSC1 will be set and an LVW interrupt

request will occur.

5.7 Reset, Interrupt, and System Control Registers and Control Bits

One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register spaceare related to reset and interrupt systems.

Refer to Table 4-2and Table 4-3in Chapter 4, Memory, of this data sheet for the absolute addressassignments for all registers. This section refers to registers and control bits only by their names. AFreescale-provided equate or header file is used to translate these names into the appropriate absoluteaddresses.

Some control bits in the SOPT1 and SPMSC2 registers are related to modes of operation. Although briefdescriptions of these bits are provided here, the related functions are discussed in greater detail inChapter 3, Modes of Operation.


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5.7.2 System Reset Status Register (SRS)

This high page register includes read-only status flags to indicate the source of the most recent reset. Whena debug host forces reset by writing 1 to BDFR in the SBDFR register, none of the status bits in SRS willbe set. Writing any value to this register address causes a COP reset when the COP is enabled except thevalues 0x55 and 0xAA. Writing a 0x55-0xAA sequence to this address clears the COP watchdog timer

without affecting the contents of this register. The reset state of these bits depends on what caused theMCU to reset.

Figure 5-3. System Reset Status (SRS)

7 6 5 4 3 2 1 0

R POR PIN COP ILOP ILAD 0 LVD 0

W Writing 0x55, 0xAA to SRS address clears COP watchdog timer.

POR: 1 0 0 0 0 0 1 0

LVR: u(1)

1 u = unaffected

0 0 0 0 0 1 0

Any otherreset:

0 Note(2)

2 Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bitscorresponding to sources that are not active at the time of reset entry will be cleared.

Note(2) Note(2) Note(2) 0 0 0

Table 5-4. SRS Register Field Descriptions

Field Description

7POR

Power-On Reset Reset was caused by the power-on detection logic. Because the internal supply voltage wasramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred whilethe internal supply was below the LVD threshold.

0 Reset not caused by POR.1 POR caused reset.

6PIN

External Reset Pin Reset was caused by an active-low level on the external reset pin.0 Reset not caused by external reset pin.1 Reset came from external reset pin.

5COP

Computer Operating Properly (COP) Watchdog Reset was caused by the COP watchdog timer timing out.This reset source can be blocked by COPT bits = 0:0..0 Reset not caused by COP timeout.1 Reset caused by COP timeout.

4ILOP

Illegal Opcode Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOPinstruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction isconsidered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.

0 Reset not caused by an illegal opcode.1 Reset caused by an illegal opcode.


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5.7.4 System Options Register 1 (SOPT1)

This high page register is a write-once register so only the first write after reset is honored. It can be readat any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored toavoid accidental changes to these sensitive settings. SOPT1 should be written during the users resetinitialization program to set the desired controls even if the desired settings are the same as the reset

settings.

7 6 5 41

1 Bit 4 is reserved, writes change the value, but will have no effect on this MCU.

3 2 1 0

RCOPT STOPE

0IICPS BKGDPE RSTPE

W

Reset: 1 1 0 0 0 0 1 u2

2 u = unaffected

POR: 1 1 0 0 0 0 1 0

LVR: 1 1 0 0 0 0 1 u

= Unimp

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