freescale powerpoint template - nxp semiconductors · tm 6 • t4240 silicon - supported with jd...

TM

September 2013

TM 2

• The T4240QDS system is a T4240 based development

system architecture developed to serve the internal silicon

validation, performance, test and application teams. This

system is offered stand alone for lab and board farm use or

in a 4u chassis for FAE, marketing and customers. This

common platform replaces both the test card and

development systems used in the past, thus promoting

cost savings and environment for multi-team co-

development.

TM 3

• Block Diagram of T4240

• Block Diagram of T4240QDS

• T4240QDS Features

• Photos

• SERDES

• DDR

• Local Bus (IFC)

• TSEC SPI SDHC USB UART and General IO

• I2C

• System Clocking

• T4240 Requirements and System Power Implementation

• Software Support : SDK v1.4

• Q&A

4 TM

Power Arch™

e6500

D-Cache I-Cache

32 KB 32 KB

D-Cache I-Cache

32 KB 32 KB

2MB Banked L2

D-Cache I-Cache

32 KB 32 KB

D-Cache I-Cache

32 KB 32 KB

Power Arch™

e6500 Power Arch™

e6500 Power Arch™

e6500

CoreNet™ Coherency Fabric

Peripheral

Access Mgmt Unit PAMU PAMU PAMU

32 Lanes up to 10GHz SerDes

PME

SEC QMan

BMan

RMAN

Watchpoint Cross Trigger

Perf Monitor

CoreNet Trace

Aurora

Real Time

Debug

SA

TA

2.0

DCE

FMan Complex

Inte

rlaken L

A-1

RMan

Parse, Classify, Distribute

Buffer

10G 10G

FMan

Parse, Classify, Distribute

Buffer

10G 10G

FMan

PC

Ie

PC

Ie

sR

IO

sR

IO

PC

Ie

PC

Ie S

AT

A 2

.0 DMAx2

2133+ MT/s

512KB

Plat Cache

64b DDR3 w/ECC

512KB

Plat Cache

64b DDR3 w/ECC

512KB

Plat Cache

64b DDR3 w/ECC

Data Path Acceleration

Architecture

• FMan

Parse/Class/Distribute/Policing

• QMan Queuing, Scheduling,

Shaping

• BMan Buffer Manager

• Rman RapidIO Manager

• PME Reg-ex Pattern Matcher

• SEC Wireless, SSL and IPSec

Encryption

• DCE Data Compression Engine

• TCP/IP offload

• 40Gbps IPv4 @ 64B

• 20Gbps IPSec @ IMIX

• 10Gbps RegEx @ IMIX

• 20Gbps Compression @ 4KB

12 x 64-bit, dual-threaded cores w/ AltiVecTM – up to 1.8GHz

Pre-

Fetch

Power Arch™

e6500

D-Cache I-Cache

32 KB 32 KB

D-Cache I-Cache

32 KB 32 KB

2MB Banked L2

D-Cache I-Cache

32 KB 32 KB

D-Cache I-Cache

32 KB 32 KB

Power Arch™

e6500 Power Arch™

e6500 Power Arch™

e6500 Power Arch™

e6500

D-Cache I-Cache

32 KB 32 KB

D-Cache I-Cache

32 KB 32 KB

2MB Banked L2

D-Cache I-Cache

32 KB 32 KB

D-Cache I-Cache

32 KB 32 KB

Power Arch™

e6500 Power Arch™

e6500 Power Arch™

e6500

1G

1G

1G

1G

1G

1G

1G

1G

1G

1G

1G

1G

eOpenPIC

Power Mgmt

SD/MMC

2 x USB2.0 w/PHY

2x DUART

2x I 2 C

SPI

GPIO

PreBoot Loader

Security Monitor

Internal BootROM

CCSR

IFC

Clocks/Reset

5 TM

SER1

SER2

SPI SPI

NO

R

Pro

mJet

XC

VR

PMBus PWR

1.5V/1.35V

NA

ND

IF

C

Card

QIXIS

FPGA

AD

M N

OR

ISO

NET2

NET1

USB1

USB2

SDHC

eMMC

PR

OT

SPI

SDHC

UART

IFC

DDR1

DDR2

DDR3

JTAG

I2C Route +

Volt. Trans I2C1

LDO PWR

VID 4Φ PWR

GVDD

DVDD/

etc.

VDD

LDO PWR SVDD/

XVDD

RMT

CCS

PMBus,

Slots, Devs,

etc.

Symmetricom

IEEE 1588

PR

OT

USB

TSEC PHYs

IDT

840NT4-01

DDRCLK

(option)

SD1

SD2

SD3

SD4

Slot 1: x8

Slot 2: x8 XBAR

Slot 3: x8

Slot 4: x8 XBAR

Slot 5: x16

Slot 6: x8 XBAR

XBAR Slot 7: x16

Slot 8: x8

Aurora

SATA

SDxCLKx

IDT

841NT IDT

841NT IDT

841NT IDT

841NT4

GTX_CLK125x

USBCLK

MU

X

cfg_xyz

T4240

DDR3/3LP 240p DDR3/3LP 240p



PEX / Interlaken

PEX / SRIO

PEX / SRIO /

SATA

PEX

XAUI / HiGig / (Q)SGMII

XAUI / HiGig / (Q)SGMII / XFI



1588_CLKOUT

1588_CLKIN

IDT

840NT4

SYSCLK

DDRCLK

6 TM

• T4240 Silicon - Supported with JD socket, Tyco socket and direct attach.

• DDR Controllers

− Three independent DDR3 controllers supporting data rates up to 2133 MHz.

− Two DDR3/DDR3LP 64-bit/ECC UDIMM or RDIMMs per controller.

− DDR power supplies 1.5V or 1.35V nominal to all devices with automatic tracking of VTT/VREF.

• SerDes

− Two 8x “front side” banks with high-speed crosspoint switch fabric routable to two slots or four

iPass x4 connectors.

SGMII / QSGMII.

HiGig / XAUI / XFI.

iPass connectors allow evaluation via Cisco RDS or board-to-board traffic.

− Two 8x “back side” banks with high-speed crosspoint switch fabric routable to four slots or

Aurora/SATA connectors.

PCI Express 2.0/3.0.

sRIO 2.0.

Interlaken LA.

SATA 2.0.

7 TM

• IFC/Local Bus

− High-speed side.

NAND flash: 8-bit, async or sync, up to 2GB, interposer-based sockting, 16 virtual banks.

NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB.

GASIC: Minimal target (within Qixis FPGA).

IFC Debug/Development card.

− Low-speed side (de-multiplexing handled within FPGA).

NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB, 16 virtual banks.

PromJET rapid memory download support.

• Ethernet

− TSEC1/TSEC2 connect using RGMII to 10/100/1G PHY: VSC8641.

− IEEE-1588 support via Symmetricom board.

• Other IO

− Two USB 2.0 ports with integrated PHYs: one type-A, one micro-AB.

− eSDHC card slot and on-board eMMC device.

− eSPI bootable memory.

− Serial ports (2), I2C ports (4)

8 TM

• Clocks

− System and DDR clock (SYSCLK, “DDRCLK”): IDT co-developed.

Switch selectable to one of 16 common settings in the interval 33MHz-166MHz, SW selectable

to 1MHz increments.

− SERDES clocks.

Provides 100.00, 125.00 or 156.25 MHz clocks to all SerDes blocks and slots.

• QIXIS System Logic FPGA

− Manages system power and reset sequencing.

− Manages DUT, board, clock, etc. configuration for dynamic shmoo.

− Collects V-I-T data in background for code/power profiling.

− General fault monitoring and logging.

− Runs from ATX “hot” power rails allowing operation while system is off.

− Remote control/configuration via I2C (Komodo).

9 TM

• Power Supplies

− Sourced by either Sparkle 750 ATX or 700 1U bulk supplies.

− Dedicated regulator for VDD (Cores + Platfrom).

Adjustable from (0.7V to 1.2V) at ~120A.

Regulators can be controlled by VID via software.

− Dedicated regulator for GVDD (DDR) : 1.35/1.5V at 40A.

Linear regulators provide VTT/MVREF automatically track operating voltage.

− Dedicated regulators/filters for SERDES AVDD supplies.

− POVDD (now called PROG_SFP) (fuse security or repair) support.

− Dedicated regulators for other supplies: OVDD, BVDD, DVDD, LVDD, etc.

• Re-use and scalability

− Interface strategy allows for scalable re-use and high coverage for IP validation.

− Design was highly reused on B4860 for a co-validation and support environment.

12 TM

• SERDES for T4240QDS was co-designed with B4860. Both

share common strategy.

• Challenge of the SERDES design:

− Pin out optimization reduced number of layer to two for all four SERDES blocks.

− 40 db per lane noise requirement.

− PLL and SVDD/XVDD power required 50KHZ – 500MHZ 10mv p-p maximum noise.

Needed to use independent filters and dedicated power supplies to reduce

fundamental and cross conducted noise.

− Stack up and material FR408 was highly optimized for best simulation results for the

SERDES and DDR.

13 TM

Gbps T4240 – 32 lanes

PCI Express Gen 1&2 2.5 / 5 Up to 4 x1 x2 x4 or Dual x8

PCI Express Gen 3 8 Dual x4

SRIO Gen 1&2 1.25** / 2.5 / 3.125 / 5 Dual x1 x2 x4

Interlaken – LA 10.3125 / 6.25 up to Eight x1

SATA Gen 1&2 1.5 / 3 Dual x1

Aurora 2.5 / 3.125 / 5 x1 x2 x4

SGMII ` up to 16 x1

2.5X SGMII 3.125 up to 12 x1

QSGMII 5 up to 4 x1

XAUI 4-lanes @ 3.125 up to 4 x4

HiGig / HiGig+ / HiGig2 4-lanes @ 3.125 / 3.75 up to 4 x4

XFI 10.3125 up to 4 x1

** Test Mode only

14 TM

• T4240 has 32 lanes SERDES

− 4 SERDES Modules with 8 lanes in each Module (Lynx 26)

− “Front Side” SD 1 & 2 are Ethernet protocols

− “Back Side” SD 3 & 4 are other protocols

(PEX/SRIO/SATA/Interlaken/Aurora)

SD 1 SD 2 SD 3 SD 4 A-H A-H A-H A-H

“Front Side”

Ethernet “Back Side”

Others

15 TM

A B C D E F G H

0 1 2 3 4 5 6 7 Module ;

Protocol Freq mapping

XAUIa XAUIa XAUIa XAUIa XAUIb XAUIb XAUIb XAUIb 1;1 XAUI 3.125

HiGiga HiGiga HiGiga HiGiga HiGigb HiGigb HiGigb HiGigb 1;1a :2;1a HiGig 3.125 / HiGig+ 3.75

HiGiga HiGiga HiGiga HiGiga XAUIb XAUIb XAUIb XAUIb 1;1b : 2;1b HiGig 3.125 / HiGig+ 3.75; XAUI 3.125

XAUIa XAUIa XAUIa XAUIa SGMIIa SGMIIb SGMIIc SGMIId

1;2

XAUI 3.125; SGMII 1.25

XAUIa XAUIa XAUIa XAUIa SGMIIa 2xSGMIIb SGMIIc SGMIId XAUI 3.125; SGMIIa,c-d 1.25; SGMIIb 3.125

XAUIa XAUIa XAUIa XAUIa 2xSGMIIa SGMIIb SGMIIc SGMIId XAUI 3.125; SGMIIa 3.125; SGMIIb-d 1.25

XAUIa XAUIa XAUIa XAUIa 2xSGMIIa 2xSGMIIb SGMIIc SGMIId XAUI 3.125; SGMIIa-b 3.125; SGMIIc-d 1.25

XAUIa XAUIa XAUIa XAUIa 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId XAUI 3.125; SGMII 3.125

HiGiga HiGiga HiGiga HiGiga SGMIIa SGMIIb SGMIIc SGMIId

1;2a

HiGig 3.125; SGMII 1.25

HiGiga HiGiga HiGiga HiGiga SGMIIa 2xSGMIIb SGMIIc SGMIId HiGig 3.125; SGMIIa,c-d 1.25; SGMIIb 3.125

HiGiga HiGiga HiGiga HiGiga 2xSGMIIa SGMIIb SGMIIc SGMIId HiGig 3.125; SGMIIa 3.125; SGMIIb-d 1.25

HiGiga HiGiga HiGiga HiGiga 2xSGMIIa 2xSGMIIb SGMIIc SGMIId HiGig 3.125; SGMIIa-b 3.125; SGMIIc-d 1.25

HiGiga HiGiga HiGiga HiGiga 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId HiGig 3.125; SGMII 3.125

HiGiga HiGiga HiGiga HiGiga SGMIIa SGMIIb SGMIIc SGMIId 1;2b HiGig+ 3.75; SGMII 1.25

SGMIIe SGMIIf SGMIIh SGMIIg SGMIIa SGMIIb SGMIIc SGMIId 1;3

1;4

1;5

2;9

SGMIIa-h 1.25

SGMIIe SGMIIf SGMIIh SGMIIg SGMIIa 2xSGMIIb SGMIIc SGMIId SGMIIa,c-h 1.25; SGMIIb 3.125

SGMIIe SGMIIf SGMIIh SGMIIg 2xSGMIIa SGMIIb SGMIIc SGMIId SGMIIa 3.125; SGMIIb-h 1.25

SGMIIe SGMIIf SGMIIh SGMIIg 2xSGMIIa 2xSGMIIb SGMIIc SGMIId SGMIIa-b 3.125; SGMIIc-h 1.25

SGMIIe SGMIIf SGMIIh SGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId SGMIIa-d 3.125; SGMIIe-h 1.25

X X QSGMIIb X X X QSGMIIa X 1;6 : 2;10 QSGMII 5

SGMIIe SGMIIf SGMIIh SGMIIg X X QSGMIIa X

1;7

2;11

1;8

SGMIIe-h 1.25; QSGMII 5

SGMIIe SGMIIf SGMIIh 2xSGMIIg X X QSGMIIa X SGMIIe-f,h 1.25; SGMIIg 3.125; QSGMII 5

SGMIIe SGMIIf 2xSGMIIh SGMIIg X X QSGMIIa X SGMIIe-g 1.25; SGMIIh 3.125; QSGMII 5

SGMIIe SGMIIf 2xSGMIIh 2xSGMIIg X X QSGMIIa X SGMIIe-f 1.25; SGMIIg-h 3.125; QSGMII 5

2xSGMIIe 2xSGMIIf 2xSGMIIh 2xSGMIIg X X QSGMIIa X SGMIIe-h 3.125; QSGMII 5

XAUIa XAUIa XAUIa XAUIa X X QSGMIIa X 1;9 : 2;13 XAUI 3.125; QSGMII 5

HiGiga HiGiga HiGiga HiGiga X X QSGMIIa X 1;9 : 2;13 HiGig 3.125 / HiGig+ 3.75; QSGMII 5

XFIc XFId XFIb XFIa SGMIIa SGMIIb SGMIIc SGMIId 2;3

2;4

XFI 10.3125; SGMII 1.25

XFIc XFId XFIb XFIa 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId XFI 10.3125; SGMII 3.125

XFIc XFId XFIb SGMIIg SGMIIa SGMIIb SGMIIc SGMIId 2;5

2;6 : 2;7

XFI 10.3125; SGMII 1.25

XFIc XFId XFIb 2xSGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId XFI 10.3125; SGMII 3.125

X XFId SGMIIh SGMIIg SGMIIa SGMIIb SGMIIc SGMIId 2;8

XFI 10.3125; SGMII 1.25

X XFId 2xSGMIIh 2xSGMIIg 2xSGMIIa 2xSGMIIb 2xSGMIIc 2xSGMIId XFI 10.3125; SGMII 3.125

X XFId XFIb X X X QSGMIIa X 2;12 XFI 10.3125; QSGMII 5

T4240 “FRONT SIDE”

SERDES Modules 1 / 2

• Each SERDES Module (1

& 2) consists of 8 lanes

shown

• New for T4 SERDES IP: • HiGig, HiGig+,

HiGig2, XFI, QSGMII

• Lane Reversal

supported in XAUI

and HiGig/+ (software

controlled)

• Polarity inversion for

any Ethernet protocol

(software controlled)

16 TM

T4240 “BACK SIDE” -- SERDES Modules 3 / 4

• Each SERDES Module (3 & 4) consists of 8 lanes shown above

• New for T4 SERDES IP: • PEX Gen3 (8Gb), Interlaken (LA)

• Downgrading is feasible both for PEX and for SRIO (e.g. if 4x is

supported, then downgrading for 2x and 1x is possible).

• Polarity inversion for any protocol (software controlled, except PEX

is auto-negotiated)

• Improved Lane Reversal Support:

• Auto-negotiated Lane Reversal for PEX native x4 or x8

• Software programmable Lane Reversal for PEX

(x2/x4/x8), SRIO (x2/x4)

• Lane mapping control in software for Interlaken LA (x4/x8)

• No lane swapping support for Aurora !

A B C D E F G H Freq mapping

0 1 2 3 4 5 6 7 SOC PRTCL

PEXa PEXa PEXa PEXa PEXa PEXa PEXa PEXa T4240;3/4;1 PEX 5/2.5

PEXa PEXa PEXa PEXa PEXb PEXb PEXb PEXb T4240;3/4;2 PEXa 5/2.5; PEXb 8/5/2.5

PEXa PEXa PEXa PEXa SRIOa SRIOa SRIOa SRIOa T4240;3/4;3

PEX 5/2.5; SRIO 5/2.5/1.25

PEXa PEXa PEXa PEXa SRIOa SRIOa SRIOa SRIOa PEX 8/5/2.5; SRIO 3.125

LA LA LA LA LA LA LA LA T4240;3;4 LA 10.3125 / 6.25

LA LA LA LA PEXb PEXb PEXb PEXb T4240;3;5 LA 10.3125 / 6.25; PEX 8/5/2.5

LA LA LA LA SRIOa SRIOa SRIOa SRIOa T4240;3;6 LA 10.3125 / 6.25; SRIO 5 / 3.125 / 2.5

PEXa PEXa PEXa PEXa PEXb PEXb SATAa SATAb T4240;4;4 PEX 5/2.5; SATA 3/1.5

PEXa PEXa PEXa PEXa Aurora Aurora SATAa SATAb T4240;4;5 PEX 5/2.5; Aurora 5/2.5; SATA 3/1.5

PEXa PEXa PEXa PEXa Aurora Aurora SRIOa SRIOa T4240;4;6

PEX 5/2.5; Aurora 5/2.5; SRIO 5/2.5/1.25

PEXa PEXa PEXa PEXa Aurora Aurora SRIOa SRIOa PEX 8/5/2.5; Aurora 3.125; SRIO 3.125

PEXa PEXa PEXa PEXa Aurora Aurora Aurora Aurora T4240;4;7 PEX 5/2.5; Aurora 5/2.5

17 TM

• Vitesse 3316 Crossbar Switch:

− Up to 11.5 Gbps.

− Arbitrary lane assignment provides flexible muxing solution.

− Supports 10Gb XFI (10GBASE_KR), PEX Gen3, and Out-of-Band signal

forwarding for SATA.

− Signal conditioner ( programmable input equalization up to 26dB and output

pre-emphasis up to 9dB.

− LOS (Loss of Signal) Detector on every port.

− I2C and SPI programming interfaces.

− Static Hardware pin strapping of select modes.

• ~ $50.

• 196 pins 15x15mm BGA package.

20 TM

• Three controllers pushed DDR on two sides of the pin out.

− Power delivery of memory and termination is spread out.

− Escape of vertical routes other than DDR are challenged.

− One side of pin out with dual controllers drives overall system layer count.

• Top speed of 2133 is very challenging for DDR3 technology.

− Voltage swing at 1.5V very wide.

− Timing budget pushes more burden on the T4240 controller, while less margin for

system.

21 TM

• Provides a high speed and a low speed segments.

− High speed is lighter loaded and designed to run full speed synchronous or non

synchronous devices.

− Low speed is fully separated and buffered by FPGA, like many customers will

implement. Asynchronous devices and Promjet ROM emulation on this segment.

• Add-in card on high speed side.

− Supports various wide path and or fast synchronous devices such as synchronous

NAND.

− Supports Test port validation card.

22 TM

data

CTRL

AM

C

IFC connectivity

25 ADDR/16 DATA ADM Mux NOR FLASH

64MB/128MB

NAND FLASH 1/2-1GB 0n socket FBGA-63

FPGA AD

[0:3

1],

A[2

6:3

1]

AD[0:7]

AD[0:31],A[26:31]

AD[0:31],A[26:31]

1.8V Muxed Bus

AD[0:24] AD[27:31]

A[26:31]

AVD CLE

WE0 WE1 WE2 WE3 CS0 CS1 CS2 CS3

... OE

T4240 IFC

ADDR DATA

CTRL

DeMux

POR CFG bits

data

ctrl

NOR FLASH 64MB/128MB

ADDR

ctrl

ADDR

FPGA Minimal GAsic support (IO to ~2 registers)

Dynamic boot reassignment of chip selects (All CS route to FPGA)

NOR/PromJet demux inside.

Banks = 16

Banks= 16

GAsic Target (n regs)

RCW BCSR regs

PromJet

Banks = 1

IFC CARD/ Test port Connector

Total Bus

Loads: 4

CBT

23 TM

• Fundamentally the same as P5020/P5040 functionally

− TSECs(RGMII) are on LVDD voltage rail, which is 2.5V or 1.8V(when acting as

GPIOs only).

− I2C and UART are on DVDD voltage rail, which is 2.5 or 1.8V.

− OVDD voltage rail at only 1.8V encompasses a much larger set of interfaces besides

miscellaneous types:

• IFC

• SPI

• SDHC

• Miscellaneous types like SYSCLK, DDRCLK, DMA, IRQ, JTAG , etc….

• 1.8V is becoming predominate general IO voltage

− Adds challenge to open drain bi-directional busses like I2C, when means special

provisions for more complicated sub-systems.

− Many OVDD based signals needed translation to work with rest of system.

24 TM

DUT

QIXIS

IRQ_OUT_B

LVDDOVDD

IRQ[0:11] TRANS PHY_INT_B (2.5V)

TMP_DETECT_B

LP_TMP_DETECT_B

LP_VDD

1.8V domain 2.5V domain

SYMMETRICOM_INT_B (

TRANS

3.3V3.3V domain

25 TM

Port #2

Port #1

Top port

Bottom port

HOT3.3V

QIXIS

UART 2

DUT

UART 1

OCM

DV

DD

LE

VE

L S

HF

T

DVDD-to-3V

POST/IRS

RS

23

2 T

ran

sce

ive

rs

26 TM

DUT

CO

P

TRST_B

TDITCKTMS

TDOAU

RO

RA

QIXIS

eCW

TA

PM

ux

JT

AG

_R

ou

te

COP_xyz

Secondary

cfg_jtag_cascade

CASCADE_xyz

TAP

QDSC

OP

Aurora

Pod

uTAP/

COP/etc.

eCWTAP/Amphisbaena

sw_jtag_route[0:2]

27 TM

• Very extensive on this implementation

− Clocks, crossbars, power supply, add-in cards, power measuring features and more

controlled through I2C.

− Processor and remote host capability

− Dual system validation control link

• Primary I2C bus is 3.3V, but voltage translated and buffered to

T4240 as either 2.5V or 1.8V. A big challenge.

28 TM

PC

A95

47

QIXIS

DUT

I2C1

DVDD:

Headers to Remote Systems

I2C1_CH0L

VL

3.3V

LV

L

HD

RI2C2

LV

LI2C3

HD

RI2C4

HD

RH

DR

1.8 or 2.5V

I2C1_CH7

PC

A9

547

I2C1_CH7_CH0

I2C1_CH7_CH7

Note that I2C4 is NOT translated.

I2C1_CH6

...I2C1_CH1

I2C1_CH7_CH1

I2C1_CH7_CH6

...LVLRST_I2C_B

HD

R

LVL

KomodoController(3.3V I2C)

I2C Monitoringfor BackgroundData C ollection(I-V-T)

29 TM

T4240

SYS CLK

RT CLK

SD1 REFCLK1

= injection/monitoring point EC[1:2] GTX CLK125

USB CLK

= SMA injection/monitoring point

RGMII

PHYs

SYSCLK_DUT (66.67 MHz typ)

SD1_REFCLK 1

1.8 V

3.3 V

2.5V

1.8 V

LVDS

/

3 3.3V 125MHz

1588 CLK OUT

DDR CLK 1.8 V Config

Switches

QIX

IS (

FP

GA

)

33.333

MHz

OSC

VCC_3.3_HOT

Optional

25.78125

MHz

XTAL

(SSC) = Spread Spectrum Clocking Option

IDT840NT

PLL

(SSC)

33 – 200 MHz

N1

N2

Δf = 0.5M

8/16

I2C

SYSCLK

DDRCLK

RTC

PLL 125 MHz

N1

N2

Nfrac

25/125 MHz

24MHz

IDT840NT-01

Optional

25.78125

MHz XTAL

SD1 REFCLK2 SD1_REFCLK 2 LVDS

SD2 REFCLK1 SD2_REFCLK 1

SD2 REFCLK2 SD2_REFCLK 2

Front Side SERDES

(ENET)

SD3_REFCLK 1 SD3_REFCLK1_PB LVDS HCSL

SD3_REFCLK 2

SD3_REFCLK2_PB LVDS

HCSL

Slot 5 (x16)

Slot 6 (x8)

SD3 REFCLK1

SD3 REFCLK2

SD4_REFCLK 1 SD4_REFCLK1_PB HCSL

SD4_REFCLK 2

SD4_REFCLK2_PB

HCSL

Slot 7 (x16)

Slot 8 (x8)

SD4 REFCLK1

SD4 REFCLK2

LVDS

LVDS Aurora

Back Side SERDES

(PCIe, etc)

Test Port

DDRCLK_DUT (133.3 MHz typ)

RTCCLK_DUT (3.125 MHz typ)

CLK OUT SMA

SMA

SMA

EC[1:2]_GTX_CLK125

1588 CLK IN

1.8V CLK125M_DDR (125MHz)

1.8V CLK125M_DDR

1588 Module

125 MHz

125 MHz (modulated)

12.5 MHz typ I2C

24 MHz

2

1.8V CLK USB

SYSCLK_PIXIS

25MHz Ref CLK

I2C1 CH1

CFG CLKS OE

EXT

CLK IN

SMA

CFG SPREAD

HCSL 100 MHZ

IFC CLK1 IFC CLK0 IFC NDDDR CLK

HCSL differential clock

LVPECL differential clock

LVCMOS single-ended clock

LEGEND

V-div

LVDS differential clock

Optional

25.78125

MHz

XTAL

LVDS

LVDS

IDT6V31021

I2C

ICS8535I-31

25MHz

Fanout Buffer

25 MHz

XTAL

IDT8T49N222i-xxx

PLL

100

125

156.25

161.13

MHz

N1

N2

Synthesizer Mode I2C

IDT8T49N222i-yyy

PLL

100

125

156.25

161.13

MHz

N1

N2

High Bandwidth Mode I2C

IDT8T49N222i-yyy

PLL

100

125

156.25

161.13

MHz

N1

N2

High Bandwidth Mode I2C

IDT8T49N222i-xxx

PLL

100

125

156.25

161.13

MHz

N1

N2

Synthesizer Mode

ICS871S1022

PLL

(SSC)

100 MHz HCSL

0x60

0x6C

0x6D

0x6E

0x6F

/

6

LVPECL

25 MHz

XTAL

HCSL

100 MHz

Spread Spectrum Source

CFG

CLK_IN_SEL

I2C

30 TM

• Slew rate requirement for All rails except for PROG_SFP is

24V/ms max. PROG_SFP is 18V/ms max.

• VDD (Cores + Platfrom) has a DC and AC component at 1.0V.

− +- 30mv DC.

− +- 50mv AC (general transient deviation).

− + 100mv AC transient for up to 1us.

− +- Load step static to full on estimated at 30A. (should be the goal for VDD

regulator).

− Customer should plan for a di/dt on the load step of 12A/us. Speculative until

characterization.

• SVDD/XVDD require independent filtering of noise to a max of

10mvp-p from 50KHZ – 500MHZ.

31 TM

• A specific method of selecting the optimum voltage-level to

guarantee performance and power targets.

− QorIQ device contains fuse block registers defining required voltage level. This

EFUSE definition is accessed through the Fuse Status Register (DCFG_FUSESR).

− Customer system must use the VID to change the voltage regulators in the system in

a reliable and safe methodology.

• QorIQ Chassis Architecture Specification, Generation 2 Revision 0.9

defines the general EFUSE definition.

− A set of 24 efuses ([0-23]) that determine the speed bin and voltage requirements for

the device domains.

− The range and steps are much more flexible than actually needed by manufacturing;

only the fuses necessary to provide the required voltages will be implemented.

32 TM

FUSESR - Current Chassis Definition

Bits Field Definition

0-1 - Reserved

2-3 BIN 2’b00 - Speed bin 1 (low)

2’b01 - Speed bin 2 (medium)

2’b10 - Speed bin 3 (high)

2’b11 - Speed bin 4 (premium)

4-8 PLAT_V 5’b00000 – 0.8000V

5’b00001 – 0.8125V

5’b00010 – 0.8250V

5’b00011 – 0.8375V

5’b00100 – 0.8500V

5’b00101 – 0.8625V

5’b00110 – 0.8750V

5’b00111 – 0.8875V

5’b01000 – 0.9000V

5’b01001 – 0.9125V

5’b01010 – 0.9250V

5’b01011 – 0.9375V

5’b01100 – 0.9500V

5’b01101 – 0.9625V

5’b01110 – 0.9750V

5’b01111 – 0.9875V

5’b10000 – 1.0000V

5’b10001 – 1.0125V

5’b10010 – 1.0250V

5’b10011 – 1.0375V

5’b10100 – 1.0500V

5’b10101 – 1.0625V

5’b10110 – 1.0750V

5’b10111– 1.0875V

5’b11000 – 1.1000V

5’b11001 – reserved

…

5’b11111 – reserved

9-13 DA_V Same as PLAT_V

14-18 DB_V Same as PLAT_V

19-23 DC_V Same as PLAT_V

24-31 - Reserved

11111 1.2000

Reserved =1.1+n*12.5mV

11110 1.1875 11101 1.1750 11100 1.1625 11011 1.1500 11010 1.1375 11001 1.1250

11000 1.1125 10111 1.1000

=1V+n*12.5mV (MSB=1)

10110 1.0875 10101 1.0750 10100 1.0625 10011 1.0500 10010 1.0375 10001 1.0250 10000 1.0125 00000 1.0000 Default 00001 0.9875

=1V-n*12.5mV (MSB=0)

00010 0.9750 00011 0.9625 00100 0.9500 00101 0.9375 00110 0.9250 00111 0.9125 01000 0.9000 01001 0.8875 01010 0.8750 01011 0.8625 01100 0.8500 01101 0.8375 01110 0.8250

01111 0.8125 11000 0.8000

Reserved =0.8V-n*12.5mV

(consider change of resolution to 6.25mV, and

use the >1.0V options)

11001 0.7875 11010 0.7750 11011 0.7625 11100 0.7500 11101 0.7375

11110 0.7250

11111 0.7125 Use ALT field

33 TM

• At power up time zero, regulator must come up at default voltage as

defined per product. For T4240, that is 1.0V.

• VERY EARLY in the boot code and before many high speed or other

power hungry features or interfaces are turned on, the

DCFG_FUSESR register is read for the VID information. This value is

translated into whatever commands to program up the new voltage

value for the regulator.

• Once the regulator is sent the new values, a period of time needs to

pass to allow the regulator to change values BEFORE power hungry

features and higher clock rates are enabled/changed.

34 TM

GPIOs.

• Typically a parallel port, simple VRM type regulator. Older AMD and VR11 Intel type regulators are typical, but many other companies.

• Default voltage (in this case 1.0V for T4240), must be configured when GPIOs are at tier one power sequence using pull-up and pull-down resistors.

• Out of reset and into the boot code, new VID is translated and thus GPIOs are programmed and driving regulator to new value.

• May have to use a voltage translator or a open-drain approach to adapt 1.8V GPIOs of T4240.

• Software is responsible for guarding any erroneous voltage values etc…

I2C bus or Power Management Bus (PMBus)

• More sophisticated and perhaps digital control loop device with telemetry.

• Program EEprom or use resistor strapping for default voltage.

• Out of reset, serial commands to regulator to set new voltage level determined by VID.

IFC (Local Bus). Same as GPIOs or even I2C, but with the help of a FPGA or ASIC as the host interface via IFC.

35 TM

Regulator voltage change delay and over current protection (OCP).

• Voltage delay is the time from the regulator receiving a new VID value and changing to the new voltage. Going too fast can cause a fault = shutdown.

• Many regulators, especially later model PMBus, SVID and VR12 types automatically change voltage gradually and in many case the time can be programmable.

• Older VR11 parallel type Intel regulators have to be stepped by software to avoid an OCP event.

Voltage resolution

• Programmable regulators have a resolution from 50mv to 3.25mv steps.

• It costs more to support large VID ranges at 3% percent regulation. Our teams should be careful to not have too broad of range for the customer to have to validate of temperature, load and voltage. The lower the voltage, the more difficult it is to obtain 3% tolerance.

Default Voltage may not be programmable.

• VR11 regulators have a default of 1.1V, which is ok for T4240, but perhaps not for other products.

37 TM

• Provide ample power for schmooing up to 1.2V and a 3 percent

goal.

− 120A VR11 Intel analog VERY FAST response time 4 phase regulator. 6.25mv

resolution.

− Since di/dt of T4240 is not known or characterized, PDN included several low ESR

POSCAPS at 5mohm and 47uf 0805 ceramic XR5 capacitors.

− Current sensing was added on each phase and on a IMON total current

representation.

• Placement and layout was very challenging.

− Since pin out implemented very high speed signals on all four corners, had to place

VDD regulator 3.5 inches away, which limits response due to inductance.

− Use of three power layers to approach inner C5s of T4240. Two 2oz and one 1oz

power plane splits with matching grounds.

− Since heat sinks take up space and cost, optimum output stage FETS and adequate

placement spreading was used to handle thermal loss across system pcb.

38 TM

• Provide very low noise power and PLL filtering. 10mv p-p

50KHZ-500MHZ requirement.

− Use of Low Drop Out regulators exclusive to SVDD and XVDD.

− Filters were chosen to reduce droop and reduce cross IP block noise.

− Coordinated heavily with SERDES team for implementation.

− Added hooks to allow SERDES team to experiment with filtered version of VDD for

SVDD and GVDD for XVDD.

39 TM

T4240

VDD 0.90 – 1.2V

ISL6620CR

VCC_12_BULK PWM Control

Cores & Platfrom

ISL6620CR

100A

T4240 requires programmable regulator at 12.5mv min

steps.

There are four sets of sense pins ganged and

balanced with 10ohm resistors.

ISL6620CR

I2C

Power

Monitor

I2C

Power

Monitor

I2C

Power

Monitor

VDD_CORE_PL PHASE1_CPLVDD

ISL6620CR

I2C

Power

Monitor

Current includes 10% adder for schmooing and worst case silicon.

VCC_xxx = Source of Power

VDD_xxx/AVDD_xxx = Power Rail for Device

PHASE2_CPLVDD

PHASE3_CPLVDD

PHASE4_CPLVDD

Cores & Platfrom

ISL6334IRZ I2C

Power

Monitor

IMON is a current from

regulator that

represents a sum of all

four phase current. 8 BIT VID control

VR11 style.

Total Power capability

is 120A 0.9V-1.1V.

3% percent. Based on

25A step with

estimated slew of

15A/us.

40 TM

OVDD 1.8V T4240

DVDD 1.8 / 2.5V

BVDD 1.8V

LVDD 1.8V GPIO / 2.5V

40A Switcher

1.3 – 2.1 V 5%

PM

Bus

General I/O / SPI / SDHC

0.6

A

UART/ I2C 0.15 A

Integrated Flash Controller

0.5 A

ENET 0.35 A To DIMMs /MVREF/M_VTT

To Devices

To Devices

VDD_OVDD

VDD_DVDD VCC_DVDD

VDD_BVDD

VDD_LVDD

VDD_GVDD VCC_GVDD

Integrated Module

1.8/2.5V 5%

Integrated Module

1.8V 5%

Integrated Module

2.5V 5%

To Devices

.

VCC_5

VCC_1.8

I2C

Power

Monitor

DDR I/O 3.4 A

G1VDD – G3VDD 1.35/1.5

V

ZL6105 GPIO mode tested on TESTER/HSSI thus no 1.8V needed.

To Devices VCC_1.8

VCC_1.8

VCC_GVDD_S


VDD_xxx/AVDD_xxx = Power Rail for Device

VCC_12_BULK

VCCA_2.5 To power LVDD plane and phys

etc.. There is another version called

VCC2_2.5 for other stuff.

USB IO 40 MA

USB1/2_VDD_3P3 3.3V

f2 VDD_USB12_VDD_3P3

VCC_3.3

(ATX PS)

(ATX PS)

f2 f2

VDD_USB12_VDD_1P0

VDD_CORE_PL

f2 VDD_USB12_VDD_1P8

VCC_1.8 USB Core 40 MA

USB1/2_ VDD_1P0 1.0V

USB IO 40MA

USB1/2_VDD_1P8 1.8V

* Ferrite Bead is specifially Murata BLM18PG121SH1.

C = 2.2 uFC = 2.2 uF

Ferrite Bead

C = 0.003 uF

(ATX PS)

41 TM

T4240

X1VDD 1.35/1.5V

0.6A f4 VDD_X1VDD

X2VDD 1.35/1.5V

0.6A f4 VDD_X2VDD

X3VDD 1.35/1.5V

0.6A f4 VDD_X3VDD

X4VDD 1.35/1.5V

0.6A f4 VDD_X4VDD

S1VDD 1.0V

0.34A f4 VDD_S1VDD

S2VDD 1.0V

0.34A f4

S3VDD 1.0V

0.34A f4 VDD_S3VDD

S4VDD 1.0V

0.34A f4 VDD_S4VDD

VDD_GVDD

Linear Reg

1.35/1.5 V

VCC_X12_VDD VCC_X12_VDD_S

VDD_CORE_PL

Linear Reg

1.0V

VCC_S12_VDD VCC_S12_VDD_S

f4

Red resistors are optional stuff in lieu of primary. LDOs primary due to uncertain noise requirements and separation.

LT3070

LT3070


VDD_xxx = Power Rail for Device

VCC_1.8

VCC_1.8

* Ferrite Bead is specifially Murata BLM18PG121SH1.

C = 2.2 uFC = 2.2 uF

Ferrite Bead

C = 0.003 uFFerrite Bead

Linear Reg

1.35/1.5 V

VCC_X34_VDD VCC_X34_VDD_S

Linear Reg

1.0V

VCC_S34_VDD VCC_S34_VDD_S VDD_S2VDD

* All SERDES filter and power noise requirement =

10mv p-p from 50khz to 500MHZ..

42 TM

AVDD_SRDS1_PLL1 1.35-1.5V

T4240

f3

f3

f3

f3

Group1_ PLL1 40mA

AVDD_SRDS1_PLL2

f3

f3

VCC_X1234_VDD_S

R = 0.33 ohm

C = 4.7 uFC = 47 uFC =

0.003uF

Grounds

need

isolation

f3

Group1_ PLL2 40mA

Group2_ PLL1 40mA

AVDD_SRDS1_PLL1

AVDD_SRDS2_PLL1

Group2_ PLL2 40mA

AVDD_SRDS2_PLL2

Group3_ PLL1 40mA

AVDD_SRDS3_PLL1

Group3_ PLL2 40mA

Group4_ PLL1 40mA

Group4_ PLL2 40mA

f3

f3

AVDD_SRDS4_PLL1

AVDD_SRDS4_PLL2

AVDD_SRDS3_PLL2










* All SERDES filter and power noise requirement =

10mv p-p from 50khz to 500MHZ..

43 TM

AVDD_CGA1 1.8V

T4240

IRS_VDD 1.8V

POVDD GND (read)

1.89V (write)

Linear Reg

GND / 1.89 V

f1 GroupA_ PLL1 3mA

f1

R = 5 ohm

C = 1 uFC = 10 uF

IR Sense analog 0.05A

Fuse Prgm

FA_VDD 1.0V Process Detect 0.05A

150mA

AVDD_CC1

VCC_POVDD

VDD_IRS_VDD

VDD_POVDD

FA_VDD

AVDD_CGA2 1.8V f1 GroupA_PLL2 3mA

AVDD_CC2

VDD_LP 1.0V Low Power Security Monitor

VDD_LP

Strict timing and rise time requirements..

AVDD_CGB1 1.8V GroupB_PLL1 3mA f1

AVDD_CGA3 1.8V GroupA_PLL3 3mA f1

AVDD_CGA3

AVDD_CGB1

VCC_1.8

VDD_CORE_PL

VCC_1.8

AVDD_CGB2 1.8V f1 GroupB_PLL2 3mA

AVDD_CGB2

AVDD_DDR 1.8V f1 DDR_PLL 3mA

AVDD_DDR

AVDD_PL 1.8V f1 Platform_PLL 3mA

AVDD_PL



44 TM

Integrated Module

1.2V 5%

Integrated Module

2.5V 5%

VCC_5

VCC_EPHY_1.2



(ATX PS)

VCCB_2.5

Integrated Module

3.3V 5%

Integrated Module

1.5V 5%

VCC_HOT_5

VCC_HOT_3.3

(ATX PS)

VCC_HOT_1.5

45 TM

• T4240/4160 rev 1

• BSC9131 rev 1 and BSC9131RDB

• BSC9132 rev 1 and BSC9132QDS

• G4860 rev 1

• TWR-P1025

• P1020RDB-PD

• P1023RDB-PA

• P1010RDB 1 GHz

• MPC85xx processor and board support removed

• P1020UTM, P1020MBG, P1020RDB-PC, P1024RDB,

P1025RDB, P1023RDS support removed

46 TM

• U-Boot Boot Loader

U-Boot 2013.01

Secure Boot for T4240 and B4860

Cryptographic blob generation commands in ESBC

• Linux Kernel and Virtualization

Linux kernel 3.8.13

Linux Preempt Real-Time (RT) - v3.8.13-rt9

Preempt RT support for B4860QDS and TWR-P1025

Linux Container (LXC) 0.9.0

Libvirt 1.0.3

Kernel-based Virtual Machine (KVM) features:

KVM: e6500 - T4240 and B4860

KVM: QEMU 1.4

KVM: USB pass through

• Yocto and Toolchain

Yocto/Poky 1.4 "Dylan"

gcc-4.7.2, eglibc-2.15, binutils-2.23.1, gdb-7.5.1

Mixed mode builds - ability to build both 32-bit and 64-bit applications with same toolchain

47 TM

• DPAA Offloading driver added [P4080, B4860/4420]

• Ethernet DPAA: ethtool update relating to 3.8 kernel upgrade

• Ethernet DPAA: PAUSE frame run-time control using ethtool

• Ethernet DPAA: netpoll support

• Ethernet DPAA: Linux standard API for hardware timestamping (IEEE1588)

• Ethernet DPAA: Removed the Qdisc support bypass from the standard SDK configuration

• FMan: Virtual Storage Profile using chosen node

• FMan: Pre-silicon support for T4240 and B4860 rev 2

• FMan: Microcode version update

• IEEE1588 driver: P5040 and 64-bit

• PCIe: hot remove/rescan

• PCIe: End Point (EP) support [P4080, T4240]

• QMAN: Pre-silicon support for T4240 and B4860 rev 2

• SEC: QMan Interface for DPAA processors

• Thermal Monitor support [using on-board sensors for T4240QDS, B4860QDS, P1022DS]

• XFI support on B4860QDS

freescale powerpoint template - nxp semiconductors · tm 6 • t4240 silicon - supported with jd...

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