front end circuit.. czt front end electronics interface cztasic front end electronics to processing...
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Front End Circuit.
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CZT FRONT END ELECTRONICS INTERFACE
CZT ASICFRONT END
ELECTRONICS TO PROCESSING ELECTRONICS
-500 V BIAS +/-2V +/-15V
I/O signal
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1. It is fully data driven charge signal acquisition chip.
2. All Analog and Digital outputs are current driven for 1µs.
Each pixel is addressable.
3. Provision of programming for needed parameters of the chip like threshold, shaping time constant and various other parameter.
ClkIn and RegIn are Clock and Input for the Shift-registor.
4. The chip requires +2 and -2 volts for operation.
5. Daisy chaining of chips.
FEATURES OF ASIC XaIm3.2
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Signal levels Remarks
Dvdd + 2 V Digital positive supply.
Dvss - 2 V Digital negative supply.
Avdd +2 V Analog positive supply.
Avss - 2 V Analog negative supply.
Gnd 0 V Analog ground.
Dgnd 0 V Digital ground.
Aoutp 0 to 200µA Pulse height value of hit channel.
Aoutm 0 to -200µA Pulse height value of hit channel.
Mgo 60 µA Magnitude of Mgo determines the no. of hits.
Io#15 – Io#0
0-100 µA To get output in digital form use transimpedence amplifier. Logic 1 = 100 µA, Logic 0 = 0µA
MaRes p 100 mV Resets the ASIC.
Reg In +/- 2 V Logic 1 = +2 V, Logic 0 = -2 V
Clk in +/- 2 V Data at Reg In is sampled at falling edge of clock.
Reg Out +/- 2 V Logic 1 = +2 V, Logic 0 = -2 V
I/O Interface to Front End Electronics
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ASIC control signalsSignal Description Adjustement
Vthr Discriminator threshold voltage
Int. DAC, ext. overriding possible.
Ifs Bias current feedback resistance shaper
Ifp Bias current feedback resistance preamp
TrigWbias Bias-current for data-output duration
Sha_bias Bias-current for shaper
Ls_bias Ref. voltage for analog output buffer
TrigDelBias Bias-current for delay of trigger
Mbias Bias-current for internal bias generation network
Int. DAC.
ResWbias Bias-current for internal reset duration External overriding possible.
Ota_bias Bias-current for peak-hold and discriminator
MaResP Reset of the chip + 100mV
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Outline of Amplifier channel
aout
ctout
in
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Functional Block Diagram
Analoguechannel
aout
ctout
in
Ch Addr
Fixedcurent
Control register
Analoguechannel
aout
ctout
in
Ch Addr
Fixedcurent
Dummy channel
aout
RO unit
Reg In
Clk In
Reg Out
Trigger&
MultihitMGO
Aoutp
Aoutm
No 0
No 127
vfp vfs Thresh
16 bitaddress
o/p
9 bit ASICidentifier
7 bit hitpixel addr
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Data acquisition in ASIC at each event Hit pixel collected charge
pulse is amplified & filtered in pre-amp & shaper.
Peak detector detects the peak of the pulse.
If peak value is larger than threshold, trigger signal will be generated.
Hit pixel trigger signal + Analogue peak value + Channel address. (Readout period = 1µs).
The chip resets itself after Readout period.
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3 2 1
DAISY CHAINING OF ASIC
Upto 512 chips can be daisy chained on a common shared bus.
Options for us:-
•128 individual lines for each ASIC.
•128 ASIC daisy chained.
•32 ASIC daisy chained, so 4 quadrant.(32 x 4)
REG INREG INREG IN
REG OUTREG OUTREG OUT
CLK IN CLK IN CLK IN
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Sequence of Serial shift register mask
back
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Power Rails : DVdd = +2V,DVss = -2V AVdd = +2V,AVss = -2V Read out = Self triggered & data
driven Analog output = 0-200 µA Read out time = 1 µS Channels = 128 Peaking time = Nominal : 0.5 µS Adjustable : 0.35 µS – 1 µS Power Dissipation = 3.2 mW / channel Can be easily daisy chained.
ASIC Specifications
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M1 M2 M3 Mn
ADDR BUS
DATA BUS
TRIG & MULTI HIT
DATA
CLOCK
ENERGY PULSE