• This is a picture of the waveforms from the ModelSim simulator, running the relevant part of the FPGA firmware for the AFEII

• It may not be easy to see, but the cursors show the current situation on the AFEII. – First cursor is start of integration cycle= 0ns– Second cursor is end of integration cycle= 70ns– Third cursor is start of next integration cycle =420ns

(this is because sim is running at 100Mhz instead of 106.1Mhz)

• This is a picture of the waveforms from the ModelSim simulator, running the NEW FPGA firmware for the AFEII for MICE

• It may not be easy to see, but the cursors show the new situation.

• First cursor is start of integration cycle= 0ns– Second cursor is end of integration cycle= 120ns– Third cursor is start of next integration cycle =280ns

(this is because sim is running at 100Mhz instead of 106.1Mhz)

• I can do a little better with some fiddling, but not much.